KR101394356B1 - Apparatus and method for managing flash memory by recognizing write data pattern - Google Patents

Abstract

Disclosed is a flash memory management apparatus and method by writing data pattern recognition. The data analysis unit analyzes a bit storage pattern stored in each cell of the flash memory, and the data matching unit matches the replacement pattern corresponding to the bit storage pattern according to the analysis result of the data analysis unit. According to the present invention, the reliability and durability of the NAND flash memory can be improved by storing a minimum number of "0" bits in the page by the flash memory bit pattern storage technique based on the stored data pattern recognition. Also, it is easy and simple to apply the technique because it can be managed by the memory controller without changing the structure and cell arrangement of the NAND flash device.

Description

[0001] Apparatus and method for managing flash memory by writing data pattern recognition [

The present invention relates to a flash memory management apparatus and method, and more particularly, to a flash memory management apparatus and method for improving the reliability and durability of a flash memory.

Flash memory is widely used in portable devices such as digital cameras, MP3 players, mobile phones, and PDAs due to advantages such as low power and miniaturization. Recently, the capacity of flash memory has greatly increased, and its use has reached the level of replacing the use of personal computer or server hard disk storage device.

The flash memory performs an erase-before-write operation due to its own physical characteristics. When a write operation is performed on a page, the flash memory can perform a write operation only after erasing the block to which the page belongs, if there is data already stored in the page. Unlike hard disks, flash memory does not support overwriting, so it takes more time to write. Overwriting causes Garbage Collection, Merge Operation, and so on, and dramatically increases the Write Amplification Factor. Also, if erase operation is performed more than a predetermined number of times for the same block in the flash memory, the erase operation should be avoided in the specific block because the block can not be used any more.

Because NAND flash memory is more expensive per capacity than hard disk, it uses technology to increase the density of the cell and to increase the storage bits per cell to increase price competitiveness. These technologies have contributed to lowering the cost of NAND flash devices, but they have resulted in a significant reduction in durability and reliability of NAND flash memories.

The NAND flash memory has a gate structure for managing electrons in units of cells. The gate consists of two control gates and a floating gate, storing data in a way that stores and emits electrons in a thin oxide layer between two gates. However, since these gates are bound to one word line, there is a characteristic that the durability is changed in a block unit. Therefore, in order to improve the reliability and durability of the NAND flash memory, a program / erase cycle must be managed on a block-by-block basis. Furthermore, a method for reducing cell-to-cell electron movement in a more detailed manner should be proposed.

There is a conventional cell to cell interference cancellation technique. In order to change the cell bit pattern of the NAND flash memory, a large voltage higher than a certain voltage should be applied. The application of such a strong voltage affects not only the specific cell to which the bit pattern is to be changed but also all the cells belonging to the same word line as the corresponding cell. The bit pattern of the neighboring cell can be operated without error by maintaining a constant voltage, but the durability and reliability of the NAND flash memory is deteriorated due to the inter-cell signal noise. In order to solve this problem, a cell to cell interference cancellation scheme is used in which a voltage stored in a neighboring cell is recognized and a voltage obtained by removing signal noise is applied to a specific cell. This technique reduces the influence of voltage fluctuations on the eight surrounding cells, improving the reliability and durability to less than 2 times, but increasing the complexity to perform the operations required for voltage application.

Another conventional method is a stored data randomization technique, which reduces the influence of all cells belonging to the same word line. Reliability and durability of the NAND flash memory are fixed on a block basis, but in the worst case, there is a problem that durability is largely deteriorated by a bit storage pattern in a cell unit. When "0" is stored repeatedly in a certain cell in a word line, the durability of the whole block is lowered. In order to solve this problem, a technique of randomly switching and storing data stored in units of pages is used. In this case, the worst case can be avoided, but the durability is fixed to the average value and the operation is complicated by recovering the data through the seed value.

The reliability and durability of the next-generation NAND flash memory is significantly lower than that of the conventional flash memory, and the conventional cell-to-cell interference cancellation technique and the storage data randomization technique greatly improve durability and reliability. .

SUMMARY OF THE INVENTION The present invention provides a flash memory management apparatus and method for improving the reliability and durability of a flash memory.

According to another aspect of the present invention, there is provided a computer readable recording medium storing a program for causing a computer to execute a flash memory management method for improving the reliability and durability of a flash memory.

According to an aspect of the present invention, there is provided an apparatus for managing a flash memory by recognizing a write data pattern, the apparatus comprising: a data analyzer for analyzing a bit storage pattern stored in each cell of the flash memory; And a data matching unit for matching a replacement pattern corresponding to the bit storage pattern according to an analysis result of the data analysis unit.

According to another aspect of the present invention, there is provided a method of managing a flash memory using write data pattern recognition, the method comprising: analyzing a shape of a bit storage pattern stored in each cell of a flash memory; And a data matching step of matching a replacement pattern corresponding to the bit storage pattern according to an analysis result of the data analysis step.

According to another aspect of the present invention, there is provided an apparatus for managing a flash memory by recognizing a write data pattern, comprising: a data analyzer for analyzing a bit storage pattern stored in each cell of a flash memory; And a data matching unit for generating a substitute pattern matching the bit storage pattern according to an analysis result of the data analysis unit.

According to the apparatus and method for managing flash memory according to the present invention, the reliability and durability of the NAND flash memory can be improved by storing a small number of "0" In addition, it is easy and simple to apply the technique because it can be managed by the memory controller without changing the structure and cell arrangement of the NAND flash device.

1 is a block diagram showing a configuration of a preferred embodiment of a flash memory management device by recognition of a write data pattern according to the present invention;
FIG. 2 is a block diagram showing a configuration of a preferred embodiment of the position of a flash memory management apparatus by recognition of write data patterns according to the present invention in the entire system;
3 is a diagram illustrating a case where a bit storage pattern of write data is recognized and matched to a replacement pattern, and
4 is a flowchart illustrating an operation of a flash memory management apparatus according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of a flash memory management apparatus and method according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a flash memory management device by recognition of write data patterns according to the present invention.

1, a flash memory management apparatus according to the present invention includes a data input unit 110, a data analysis unit 120, a data matching unit 130, a memory access unit 140, and a storage unit 150 .

Data to be written in response to a write request from the outside is input to the data input unit 110.

The data analysis unit 120 analyzes a bit storage pattern in which write target data to which a write request is input is stored in each cell of the flash memory. As an example of the analysis method, it is possible to calculate the number of times the bit storage pattern stored in each cell of the flash memory of the write target data is repeated.

The data matching unit 130 matches the replacement pattern corresponding to the bit storage pattern stored in each cell of the flash memory of the write target data. For example, the data matching unit 130 may determine a replacement pattern so that the number of "1" bits included in the replacement pattern increases according to the number of times the bit storage pattern of the same type is repeated. Specifically, when the number of times "0100" is repeated in the bit storage pattern is the greatest, the replacement pattern corresponding to the bit storage pattern "0100 " When the number of times of repetition of "0001" in the bit storage pattern is the next, the bit storage pattern "0001" can be matched to any one of "1110 "," 1101 ", " 1011 & have.

The data matching unit 130 arranges the replacement patterns determined in correspondence with the respective bit storage patterns in the form of a replacement pattern matching table and the storage unit 150 stores the replacement pattern matching table generated by the data matching unit 130 . The size of the substitute pattern matching table can be adjusted considering the capacity of the memory. That is, it is not necessary to determine a replacement pattern corresponding to all types of bit storage patterns, and a replacement pattern may be determined only for a bit storage pattern having a repetition number of times or more.

Meanwhile, the data matching unit 130 may determine a substitution pattern by analyzing the repetition times of the bit storage pattern as described above, or may use a preset substitution pattern according to the type of the bit storage pattern. In this case, a function of obtaining a substitute pattern from a form of a table or a bit storage pattern matched with a bit storage pattern and a substitute pattern is stored in the storage unit 150 in advance, and the data matching unit 130 stores data The replacement pattern is determined from the bit storage pattern.

Finally, the memory access unit 140 stores the matched replacement pattern in the storage space of the flash memory.

When a read request for write target data stored from the outside is input, the flash memory management apparatus according to the present invention can generate a bit store pattern from a substitute pattern using a substitute pattern matching table or function stored in the storage unit 150 .

FIG. 2 is a block diagram showing a configuration of a preferred embodiment of the position of a flash memory management apparatus by recognition of write data patterns according to the present invention in the entire system.

In FIG. 2, the write / read command requested through the host reaches the flash conversion layer via the command queue of the NAND flash memory based storage device. On the other hand, when the requested write data is temporarily stored in the buffer of the NAND flash memory based storage device and is mapped to the actual NAND area by the flash conversion layer, the flash program operation is performed.

The flash memory management apparatus according to the present invention performs encoding / decoding of a data pattern by being implemented as a data pattern recognition memory access engine in a control layer in which a flash program operates. When the controller is located inside the NAND flash memory device, the flash memory management device according to the present invention may be located in the controller of the chip. Alternatively, it is possible to implement the data pattern recognition memory access engine as a hardware module, or to place an alternative pattern matching table referenced by the engine in the SRAM.

3 is a diagram illustrating a case where a bit storage pattern of write data is recognized and matched to a replacement pattern. As described above, the substitute pattern matching table exists in the storage unit 150 of the present invention, that is, in the data pattern recognition memory access engine, and the data matching unit 130 maps the bit storage pattern and the substitute pattern to be actually stored one to one . The Huffman algorithm can be used as an alternative pattern generation technique to be stored in the actual flash area.

The Huffman code is coded so as to have the shortest code code with respect to the data pattern that occurs most frequently, whereas in the present invention, the pattern is generated in the form of the most "1" In addition, overhead is minimized by using inversion techniques for stored data where the number of "0" In this case, simple information such as an inversion flag bit is led to be stored in the spare area of the NAND flash memory.

The size of the substitute pattern matching table can be adjusted in consideration of the capacity of the memory, and the substitute pattern shape may be expressed as a function form of a bit storage pattern instead of storing the form of the substitute pattern as described above.

Another analysis method for the write target data into which the write request is input is an analysis method for calculating the number of "0" bits included in the data pattern in which the write target data is stored in the page of the flash memory.

When storing data to be written by such an analysis method, the data matching unit 130 sets the number of "0" bits included in the data pattern stored in the page of the flash memory to be the write target data, The access unit 140 may cause each bit included in the data pattern to be inverted and stored. In general, the file system metadata has a data pattern with a large number of "0" bits. This is because the meta data stores the map table and the setting register of the overall data of the file system, and uses the necessary part and fills the entire other reserved area with "0" bits.

In view of these characteristics, when a data pattern in which a "0" bit is stored at a predetermined threshold value or more occurs, a storage technique of inverting the bits of the entire page stored is very useful. That is, if the number of "0" bits included in the data pattern stored in the page is equal to or greater than a predetermined threshold value, the "0" bit is converted to "1" bit and the "1" bit is converted to "0" bit. When storing a page, a "1" bit or a "0" bit can be stored in the spare area to add an inversion flag bit indicating whether or not to invert.

Alternatively, there is an analysis method for determining whether the write target data includes a continuous "0" bit in a data pattern stored in a page of the flash memory. In a case where the data to be written as the analysis result includes a plurality of "0" bits continuous to the data pattern stored in the page of the flash memory, the data matching unit 130 of the flash memory management apparatus according to the present invention includes a memory access unit 140 may cause the plurality of "0" bits to be inverted and stored in the flash memory. That is, the data pattern to be stored is sequentially scanned and encoded so as to have a pattern of a large number of "1" bits. In the worst case, if the "1" bit and the "0" bit inversion continue, the encoded data may be all "0" bits, but in this case the number of "1" Can be increased.

4 is a flowchart illustrating an operation of a flash memory management apparatus according to an embodiment of the present invention.

Data to be written in response to a write request from the outside is input to the data input unit 110 (S110).

The data analysis unit 120 analyzes the bit storage pattern in which the write target data to which the write request is input is stored in each cell of the flash memory (S120). As an example of the analysis method, an analysis method of calculating the number of times the bit storage pattern stored in each cell of the flash memory of the write target data is repeated can be performed as described above.

The data matching unit 130 matches the replacement pattern corresponding to the bit storage pattern stored in each cell of the flash memory of the data to be written (S130). The replacement pattern can be determined so that the number of "1" bits included in the replacement pattern increases according to the number of times the same type of bit storage pattern is repeated.

The storage unit 150 stores an alternative pattern matching table in which a bit storage pattern or a data pattern and a replacement pattern are recorded together. The size of the substitute pattern matching table can be adjusted considering the capacity of the memory.

Finally, the memory access unit 140 stores the matched replacement pattern in the storage space of the flash memory (S140).

As described above, the present invention intends to maximize the number of "1" bits and store the NAND flash memory in the NAND flash memory. Therefore, the reliability and durability of the NAND flash memory can be improved 10 times or more.

According to the flash memory management method of the present invention, when data to be written is stored, a pattern of existing data already stored in a storage location corresponding to address information of a flash memory in which data to be written is to be stored, It is also possible to use a method of storing only the changed bits among the patterns converted from the data. Since the present invention can be implemented without changing the structure of the flash memory device.

Specifically, an XOR operation is performed between a pattern of the existing data and the converted pattern to calculate differential data indicating the changed bit from the existing data, and the differential data may be compressed and stored in a separate storage medium.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and may be implemented in the form of a carrier wave (for example, transmission via the Internet) . The computer-readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation in the embodiment in which said invention is directed. It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims (19)

A data analysis unit for analyzing a bit storage pattern stored for each analysis unit consisting of a plurality of cells determined in advance among the cells of the flash memory; And
And a data matching unit for matching a substitution pattern corresponding to the bit storage pattern according to an analysis result of the data analysis unit,
Wherein the data analyzer calculates the number of times the same type of bit storage pattern is repeated for each analysis unit,
Wherein the data matching unit determines the type of the replacement pattern so that the number of '1' bits increases corresponding to the number of repetition of the bit storage pattern. The method according to claim 1,
Further comprising a storage unit in which a replacement pattern corresponding to the bit storage pattern is set in advance in a form of a table or a function for the bit storage pattern,
Wherein the data matching unit associates the replacement pattern stored in the storage unit with the bit storage pattern. delete The method according to claim 1,
Further comprising a storage unit for storing a replacement pattern determined corresponding to each bit storage pattern of the write target data. delete delete delete Data analysis step of analyzing the stored bit pattern is stored by each analysis unit comprising a plurality of cells which are determined in advance among the cells of the flash memory; And
And a data matching step of matching a substitution pattern corresponding to the bit storage pattern according to an analysis result of the data analysis step,
Calculating a number of times that the same type of bit storage pattern is repeated for each of the analysis units in the data analysis step,
Wherein the type of the replacement pattern is determined in the data matching step such that the number of '1' bits increases corresponding to the number of repetition of the bit storage pattern. 9. The method of claim 8,
A replacement pattern corresponding to the bit storage pattern is preset and stored in a form of a table or a function of the bit storage pattern,
And in the data matching step, associating the previously stored replacement pattern with the bit storage pattern. delete 9. The method of claim 8,
Further comprising a storing step of storing a replacement pattern determined in correspondence with each bit storage pattern of the data to be written. delete delete delete A computer-readable recording medium storing a program for causing a computer to execute the flash memory management method according to any one of claims 8, 9, and 11. A data analysis unit for analyzing a bit storage pattern stored for each analysis unit consisting of a plurality of cells determined in advance among the cells of the flash memory; And
And a data matching unit for generating a substitute pattern matching the bit storage pattern according to an analysis result of the data analysis unit,
Wherein the data analyzer calculates the number of times the same type of bit storage pattern is repeated for each analysis unit,
Wherein the data matching unit generates the type of the replacement pattern so that the number of '1' bits increases corresponding to the number of repetition of the bit storage pattern. delete delete delete

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