KR101387973B1 - Method, multicore processor, computing device and computer readable storage medium for implementing distributed-type markov chain monte carlo procedure - Google Patents

Abstract

Embodiments and techniques for the distributed Markov chain Monte Carlo are generally disclosed.

Description

METHOD, MULTICORE PROCESSOR, COMPUTING DEVICE AND COMPUTER READABLE STORAGE MEDIUM FOR IMPLEMENTING DISTRIBUTED-TYPE MARKOV CHAIN MONTE CARLO PROCEDURE}

Unless stated otherwise herein, the approaches described in this section are not prior art of the claims in this application and are not admitted to be prior art by inclusion in this section.

The Markov chain Monte Carlo procedure can be used in many fields, including engineering, physics, astronomy, biology, finance, cryptography, statistics, social sciences and medicine. Markov chain Monte Carlo applications usually use a significant amount of processing power. As a result, the Markov chain Monte Carlo application can run on a high performance computing system.

Some exemplary methods, apparatus, and systems relate to a distributed-type Markov chain Monte Carlo. Such a method may include generating, via a swap proposal core, a plurality of swap proposals associated with a distributed Markov chain Monte Carlo procedure. One or more of the swap proposals may be received from the swap proposal core via a first chain core. A plurality of random numbers may be generated through the first chain core. The current iteration of the first chain portion of the distributed Markov chain Monte Carlo procedure may be processed through the first chain core based at least in part on the plurality of random numbers. The first chain core may wait, based at least in part on one or more of the swap proposals, for the current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure associated with the second chain core to reach a corresponding iteration. The generation of the random number can proceed through the first chain core without interruption while waiting for the second chain core to reach the corresponding iteration of the distributed Markov chain Monte Carlo procedure.

Some examples may include a multicore processor that includes a plurality of processor cores, and the multicore processor may include a swap proposal core and a first chain core. The swap proposal core may be configured to generate a plurality of swap proposals associated with the distributed Markov chain Monte Carlo procedure. The first chain core receives one or more of the swap proposals from the swap proposal core, generates a plurality of random numbers, and the current iteration of the first chain portion of the distributed Markov chain Monte Carlo procedure based at least in part on the plurality of random numbers. And wait for the current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure associated with the second chain core based at least in part on one or more of the swap proposals to reach the corresponding iteration. The second chain core may be configured to handle the current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure. The first chain core may be further configured to continue generating a random number without interruption while waiting for the second chain core to reach the corresponding iteration of the distributed Markov chain Monte Carlo procedure.

Some examples may include a computing device that includes a plurality of processor cores, and the computing device may include system memory configured to communicate with the multi-core processor via a multi-core processor, a memory bus, a memory bus. The multi core processor may include a swap proposal core and a first chain core. The swap proposal core may be configured to generate a plurality of swap proposals associated with the distributed Markov chain Monte Carlo procedure. The first chain core receives one or more of the swap proposals from the swap proposal core, generates a plurality of random numbers, and the current iteration of the first chain portion of the distributed Markov chain Monte Carlo procedure based at least in part on the plurality of random numbers. And wait for the current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure associated with the second chain core based at least in part on one or more of the swap proposals to reach the corresponding iteration. The second chain core may be configured to handle the current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure. The first chain core may be further configured to continue generating a random number without interruption while waiting for the second chain core to reach the corresponding iteration of the distributed Markov chain Monte Carlo procedure.

The foregoing summary is exemplary only and is not intended to be limiting in any way. In addition to the exemplary aspects, embodiments, and features described above, additional aspects, embodiments, and features will become apparent by reference to the drawings and detailed description that follows.

This subject matter is particularly noted and clearly claimed in the conclusion section of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings. It is understood that these drawings illustrate only a few embodiments in accordance with the present disclosure, and therefore should not be considered as limiting the scope thereof, and that the present disclosure is described in more detail and detail through use of the accompanying drawings. Will be.
1 is an illustration of an exemplary computing device including a multi-core processor configured to implement a distributed Markov chain Monte Carlo procedure;
2 is an illustration of an example process for operation of a multi-core processor configured to implement a distributed Markov chain Monte Carlo procedure;
3 is an illustration of an example process for operation of a multi-core processor configured to implement a distributed Markov chain Monte Carlo procedure;
4 is an illustration of an exemplary computer program product;
5 is a block diagram illustrating an example computing device, all arranged in accordance with at least some embodiments of the present disclosure.

The following disclosure presents various examples in accordance with specific details in order to provide a thorough understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter may be practiced without some or more of the specific details disclosed herein. In addition, in some circumstances, well known methods, procedures, systems, configurations and / or circuits are not described in detail in order to avoid unnecessarily obscuring the claimed subject matter. In the following detailed description, reference is made to the accompanying drawings which form a part hereof. In the drawings, like reference numerals identify generally similar components, unless otherwise indicated in the context. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Without departing from the scope and spirit of the objects set forth herein, other embodiments may be utilized and other modifications may be made. It is to be understood that aspects of the present disclosure, as generally described herein and shown in the figures, may be arranged, substituted, combined, and designed in a variety of different configurations, all of which are clearly considered herein and become part of the present disclosure. will be.

The present disclosure relates, inter alia, to methods, apparatuses, and systems related to implementing a distributed Markov chain Monte Carlo procedure.

As will be described in more detail below, an improved implementation of the distributed Markov chain Monte Carlo procedure may be provided for a multi-core processor. The term "distributed Markov chain Monte Carlo" as used herein may refer to any number of Markov chain Monte Carlo procedures that support multiple parallel threads of execution. For example, the distributed Markov chain Monte Carlo procedure may include the Metropolis-coupled-type Markov chain Monte Carlo procedure, (e.g., April 2008, IEEE International Symposium on Parallel and Distributed Processing). Reducing the runtime of MCMC programs by multithreading on SMP by Symposium on Parallel and Distributed Processing 2008 (IPDPS 2008), JMR Byrd, S. Jarvis, A. Bhalerao. speculative-move-type Markov chain Monte Carlo procedure) (e.g., J.Comp.Graph.Stats, vol. 15, no. 1, 2006, A. Brockwell). Prefetch Markov chain Monte Carlo, such as "Parallel Markov chain Monte Carlo simulation by pre-fetching" Procedures and the like.

The distributed Markov chain Monte Carlo procedure can perform operations on multiple chains. Various chains may consider swapping states with other chains periodically. At least one of the chains may be a "cold" chain, which may provide a target distribution. The use of swapping states can improve the opportunity to cover complex search space. Assuming some synchronization ensures that state swap occurs between chains of the same iteration, the chains can run in parallel. One challenge addressed here is to use as many available cores as possible while maintaining the semantics of the distributed Markov chain Monte Carlo procedure, which helps this synchronization to be maintained.

As described in more detail below, the methods, apparatus, and systems may operate so that the various chains may not be required to be synchronized simultaneously. In some examples a dedicated "swap" core may host two threads, a swap proposal generation thread and a swap proposal distribution thread. Such a swap proposal core may be configured to generate a swap proposal and to distribute such swap proposal information to a targeted chain. Thus, the chain can run almost independently, and a particular chain can be stopped if a swap is proposed for it in a given iteration.

Also, with some Markov chain Monte Carlo procedures, at least two and sometimes all cores are idle, stopping chain operations, while waiting for information to determine if a single swap should occur or exchanging the state data itself. You can wait for it to finish. As will be described in more detail below, the methods, devices, and systems may operate such that a core with a waiting chain does not need to be idle. Instead, if the chain waits, the core of the chain can be used for random bit generation for future use. In some examples, individual "chain" cores may host two threads, a random number generating thread and a chain thread. As the random number generating thread and the chain thread are separated, the chain core may continue to process the random number generating thread and may not need to wait for the operation of the chain thread. Similarly, as the swap proposal generation thread and the swap proposal distribution thread are separated, the swap proposal core may continue to process the swap proposal generation thread and may not need to wait for the swap proposal distribution thread to operate.

1 is an illustration of an example computing device that includes a multi-core processor 100 arranged in accordance with at least some embodiments of the present disclosure. Multi-core processor 100 may be configured to implement a distributed Markov chain Monte Carlo procedure. In the example shown, the multi core processor 100 may comprise a single integrated circuit having a processing core array. In other examples, the multi-core processor 100 may include a processor core on a separate integrated chip. In addition to or in place of the multi core processor 100, a distributed computing environment system (not shown) is utilized to perform all or part of the functionality described herein for the multi core processor 100. Can be. For example, such a distributed computing environment system (not shown) may be a plurality of (eg, desktop computers, laptop computers, workstations, server devices, storage units, etc.) that can be operatively coupled together via a network. It can include a computing device.

Multi-core processor 100 may include several (N) processing cores 104 (1)-104 (N). Any suitable number of processing cores 104 may be provided. For example, the multi-core processor 100 may have four (4) processing cores, dozens of processing cores 104 and even hundreds or more processing cores 104. Some multi-core processors 100 may be homogenous such that each of the processing cores 104 uses a single type of core design. The other multi-core processor 100 may have one or more of the processing cores 104 different from one or more of the other processing cores 104, and may be a separate processing core 104 or a subset of the processing cores 104. subsets may be heterogeneous so that they can be designed for different roles in the multi-core processor 100.

Processing core 104 may include a non-shared L1 cache and L2 cache (s) and shared system memory, either shared or nonshared. Individual processing core 104 may support one or more hardware threads. The processing core 104 may not be exclusively utilized to process the Markov chain Monte Carlo procedure.

1 is an exemplary schematic diagram of a multi-core processor and does not depict the physical location of the components shown. It is appreciated that the multi-core processor 100 described herein is illustrative and that examples and modifications are possible. For example, design choices can be made based on consideration of hardware size and complexity versus performance, thermal energy and heat dissipation, processor speed, overall throughput, and the like.

In the example shown, the multi-core processor 100 may include a plurality of processor cores 104 including a plurality of chain cores 108, 110, 112 and a swap suggestion core 106 configured to communicate with each other. Any suitable number of chain cores 108, 110, 112 may be provided.

In some examples, swap proposal core 106 may host two threads, swap proposal generation thread 114 and swap proposal distribution thread 116. Such swap proposal core 106 may be configured to generate a swap proposal and distribute such swap proposal information to a target chain associated with the chain cores 108, 110, 112. As the swap proposal generation thread 114 and the swap proposal distribution thread 116 are separated, the swap proposal core 106 can continue to process the swap proposal generation thread 114, and You may not have to wait for action.

As used herein, the term "swap proposal" refers to the first chain portion of the distributed Markov chain Monte Carlo procedure, the second chain portion of the distributed Markov chain Monte Carlo procedure, and the specifics of the distributed Markov chain Monte Carlo procedure. It may refer to information related to repetition. For example, swap proposal thread 114 may generate a swap proposal between two chains at some specific interval. This swap proposal data is a series of swap proposal triples {<i, j, k> ₁ ,... }, Which indicates that in iteration i the state of the first chain j can be swapped with the state of the second chain k.

In order to generate such a swap suggestion data sequence, the swap suggestion core 106 may generate a random bit. For example, swap proposal generation thread 114 may generate a random bit for use in determining (inter-chain) state swap. One of a hardware random bit generator or a pseudo-random, software-implemented bit generator may be used for random bit generation.

In some examples, individual chain cores 108, 110, 112 may host two threads, random number generating thread 118 and chain thread 120, respectively. Processes involving random number generation thread 118 and chain thread 120 are pinned to their designated chain cores 108, 110, 112 (eg, via processor affinity or similar instructions). Can be. Such pinning can help chain thread 120 preserve cache locality when searching for space.

As the random number generating thread 118 and the chain thread 120 are separated, the chain core 108 may continue to process the random number generating thread 118 and may not need to wait for the operation of the chain thread. The random number generation thread 118 may generate random bits for use in determining the (intra-chain) state transition. One of a hardware random bit generator or a pseudo random, software implemented bit generator may be used for random bit generation.

Swap proposal core 106 may include a swap proposal generation queue 122. The swap proposal generation queue 122 may be configured to store one or more of the swap proposals generated via the swap proposal generation thread 114. The swap proposal generation queue 122 may be implemented as a core-specific buffer or the like. The swap proposal core 106 may be configured to distribute one or more of the swap proposals from the swap proposal generation queue 122 to the chain cores 108, 110, 112 through the swap proposal distribution thread 116.

As the resulting swap proposals can be used at any time after they are created, the swap proposal core 106 can begin to generate swap proposals at any time, and the swap proposal generation queue 122 continuously or nearly continuously. You can continue to populate Swap proposal core 106 may also process swap proposal distribution thread 116 to distribute swap proposals to chain cores 108, 110, 112, which host chain threads 120. For example, for a request from chain thread 120, swap proposal distribution thread 116 may distribute one or more swap proposals to its chain thread 120. The swap proposal distribution thread 116 may operate as a dequeuer of swap proposals from the swap proposal generation queue 122.

The first chain core 108 may include a swap proposal distribution queue 124. The swap proposal distribution queue 124 may be configured to store one or more of the swap proposals received via the first chain core 108. The swap proposal distributed queue 124 may be implemented with a core specific buffer or the like. The individual chain threads 120 associated with the individual chain cores 108 may obtain the closest swap proposal (eg, the closest swap proposal for the current iteration) from the swap proposal core 106. For example, the swap proposal distribution queue 124 associated with the chain thread 120 may have a queue of swap proposals associated with the first chain core 108. Chain threads associated with other chain cores 110 and 112 may be responsible for keeping each swap suggestion distribution queue filled. For example, the second swap proposal distribution queue 126 may be associated with the second chain core 110. The second swap proposal distribution queue 126 may be configured to store one or more of the swap proposals received via the second chain core 126.

The first chain core 108 may include a random bit queue 128. The random bit queue 128 may be configured to store one or more of the random numbers generated via the random number generation thread 118. The random bit queue 128 may be implemented with a core specific buffer or the like. Similarly, the second random bit queue 130 may be associated with the second chain core 110. The random bit queue 130 may be configured to store one or more of the random numbers generated through the random number generation thread associated with the second chain core 110.

Since the random numbers can be used at any time after they are generated, the random number generation thread 118 can run freely on any schedule, filling the random bit queue 128 on any schedule. Thus, an individual chain core 108 can usually access the associated random bit queue 128, and the associated chain thread 120 can remove the random number from the random bit queue 128.

In operation, the associated chain core 108 is free to process the chain thread 120 (and the random number generation thread 118) before the chain thread 120 reaches the next proposed swap iteration. When the chain core 108 reaches a particular iteration (eg, the iteration associated with the received swap proposal), the chain thread 120 may cause the proposed swap chain thread (eg, the chain thread associated with the second chain core 110) to be replaced. You can wait to share enough information to determine if a swap should happen and wait to swap state if necessary. The communication about potential swap may be point-to-point communication (eg, chain thread to chain thread). The random number generated by the random number generation thread 118 and stored in the random bit queue 128 may be consumed while determining whether swap should occur. In some examples, chain thread 120 may request one or more additional swap proposals while waiting for another chain thread to be proposed for potential swap. On the other hand, the chain core 108 may continue to process the random number generation thread 118. With the exception of chain cores (eg, first chain core 108 and second chain core 110) that currently consider potential swaps, the remaining chain cores (eg, chain core 112) are random number generating threads and Both chain threads can be free to continue. During or after the evaluation of a particular swap proposal, the chain cores (eg, first chain core 108 and second chain core 110) currently considering potential swaps (eg, each swap proposal distribution queue 124). And 126 may be empty) to receive additional swap proposals from the swap proposal core 106. After the swap is complete, the chain cores 108 and 110 may resume processing the associated chain thread 120. With the decentralization and point-to-point synchronization of the foregoing efforts, high chain core utilization can be achieved with relatively small inter-core communication.

2 is an illustration of an example process 200 for operation of a multi-core processor to maintain the use of a core during implementation of a distributed Markov chain Monte Carlo procedure, arranged in accordance with at least some embodiments of the present disclosure. In the example shown, process 200 and other processes described herein may be performed by one or more of hardware, software, and / or firmware, including processing steps, functional operations, events, and the like. Present various functional blocks or actions that can be described as actions or the like. In view of the present disclosure, those skilled in the art will recognize that many alternatives to the functional blocks shown in FIG. 2 may be implemented in various implementations. For example, although the process 200 shown in FIG. 2 includes blocks or actions in a particular order, the order in which these blocks or actions are presented does not necessarily limit the claimed subject matter in any particular order. Likewise, without departing from the scope of the claimed subject matter, intervening actions not shown in FIG. 2 and / or additional actions not shown in FIG. 2 may be used and / or some of the actions shown in FIG. 2 may be removed. Can be. Process 200 may include one or more of operations 202, 204, 206, 208, and / or 210.

As shown, process 200 may be implemented for operation of a multi-core processor to maintain the use of cores during the implementation of the distributed Markov chain Monte Carlo procedure. Processing may begin at operation 202 of “generating a swap proposal”, where a plurality of swap proposals associated with a distributed Markov chain Monte Carlo procedure may be generated through the swap proposal core 106 (see FIG. 1). . For example, a swap suggestion thread 114 (see FIG. 1) associated with the swap suggestion core 106 (see FIG. 1) may generate such a swap suggestion.

Processing may continue with operation 204 to “receive a swap proposal” in operation 202, where one or more of the swap proposals are from the swap proposal core 106 (see FIG. 1), the chain cores 108, 110. , 112) (see FIG. 1). For example, the swap proposal may be distributed from the swap proposal generation queue 122 (see FIG. 1) and received by one or more of the chain cores 108, 110, 112.

Act 206 may occur after, along with, and / or before acts 202-204. In an operation 206 of “generating a random number”, a random number may be generated through one or more of the chain cores 108, 110, 112 (see FIG. 1). For example, random number generation thread 118 (see FIG. 1) associated with chain core 108 (see FIG. 1) may generate such a random number.

Processing may continue at operation 206 with operation 208, "processing the chain," where the current iteration of the chain portion of the distributed Markov chain Monte Carlo procedure is performed by chain cores 108, 110, 112 (FIG. 1). May be processed through one or more of the above). Such a chain portion may be processed based at least in part on the random number generated in operation 206. For example, chain thread 120 (see FIG. 1) associated with chain core 108 (see FIG. 1) may handle such chain portions.

Processing may continue with operation 210 "waiting" at operation 208, where the chain thread 120 (see FIG. 1) is coupled with a second chain core (eg, chain core 110 of FIG. 1). The current iteration of the second chain portion of the associated distributed Markov chain Monte Carlo procedure may wait for a corresponding iteration to arrive. Such a wait may be based at least in part on one or more of the swap proposals. For example, a given swap proposal may be a chain part (e.g., chain part and chain core 110 associated with chain core 108) proposed for the swap of information and status information related to a particular iteration of a distributed Markov chain Monte Carlo procedure. Information associated with a specific pair of chains (see FIG. 1).

In operation, process 200 may proceed to generate random numbers through chain core 108 without interruption in standby of chain core 108 in operation 210. Likewise, process 200 may proceed to generate a swap proposal through swap proposal core 106 without interruption in standby of chain core 108 in operation 210. Additionally, process 200 may proceed to generate a swap proposal through swap proposal core 106 without interruption during distribution of swap proposal distribution thread 116 in operation 204. Process 200 may also preserve the statistical performance of the distributed Markov chain Monte Carlo procedure. For example, compared to the result of not utilizing the process 200, due to the use of the process 200, there may be no need for statistical adjustments to the results of the distributed Markov chain Monte Carlo procedure.

3 is an illustration of an example process 300 for operation of a multi-core processor to maintain the use of cores during the implementation of a distributed Markov chain Monte Carlo procedure, arranged in accordance with at least some embodiments of the present disclosure. In the illustrated example, process 300 and other processes described herein are described as processing steps, function operations, events and / or actions, and the like, which may be performed by one or more of hardware, software, and / or firmware. It presents various functional blocks or actions that can be made. One of ordinary skill in the art in view of the present disclosure will appreciate that many alternatives to the functional blocks shown in FIG. 3 may be implemented in various implementations. For example, although the process 300 shown in FIG. 3 includes blocks or actions in a particular order, the order in which these blocks or actions are presented does not necessarily limit the claimed subject matter to any particular order. Likewise, without departing from the scope of the claimed subject matter, intermediate operations not shown in FIG. 3 and / or additional operations not shown in FIG. 3 may be used and / or some of the operations shown in FIG. 3 may be eliminated. . Process 300 may be one or more of operations 302, 304, 306, 308, 310, 312, 314, 316, 322, 324, 326, 328, 330, 332, 334, 336, 338, 340, and / or 342. It may include.

As shown, process 300 may be implemented for operation of a multi-core processor to maintain the use of cores while implementing distributed Markov chain Monte Carlo procedures. Processing may begin with an operation 302 of "generating and / or storing a swap proposal", where a plurality of swap proposals associated with a distributed Markov chain Monte Carlo procedure may be generated through the swap proposal core 106. For example, a swap proposal generation thread 114 associated with the swap proposal core 106 may generate such a swap proposal. In addition, such a swap proposal can be stored. For example, such a swap proposal may be stored in the swap proposal creation queue 122 (see FIG. 1).

Processing may continue with operation 304 to “distribute the swap proposal” at operation 302, where one or more of the swap proposals are passed through the chain core 108, 110 and / or 112 through the swap proposal core 106. It may be dispersed in one or more of. For example, the swap proposal may be distributed from the swap proposal generation queue 122 (see FIG. 1).

Processing may continue to operation 306 to “save swap proposal” in operation 304, where such distributed swap proposal may be received by chain core 108 and potentially stored for later use. Can be. For example, such a distributed swap proposal may be stored via the swap proposal distribution queue 124 (see FIG. 1). In some examples, similar operations 308 and 310 may occur through chain cores 110 and 112, respectively.

Operations 312-316 can occur after, alongside, and / or before operations 302-306. In an operation 312 of "generating and / or storing a random number", a random number may be generated via the chain core 108 and stored via the random bit queue 128 (see FIG. 1) for later use. Can be. For example, random number generation thread 118 associated with chain core 108 may generate and / or store such random numbers. In some examples, similar operations 314 and 316 may occur via random number generation threads 318 and 319, respectively.

Processing may continue with operation 322 to “process the chain” in operation 306, where a current iteration of the chain portion of the distributed Markov chain Monte Carlo procedure may proceed through the chain core 108. Such a chain portion may be processed based at least in part on the random number stored in the random bit queue 128 (see FIG. 1). For example, chain thread 120 associated with chain core 108 may handle such chain portions. In some examples, similar operations 324 and 326 can occur via chain threads 320 and 321, respectively.

Processing may continue with operation 328, "waiting" at operation 322, where the chain thread 120 is subject to the distributed Markov chain Monte Carlo procedure associated with the second chain core (e.g., the chain core 110). It is possible to wait for the current iteration of the two chain parts to reach the corresponding iteration. Such a wait may be based at least in part on one or more of the swap proposals. For example, a given swap proposal may be a chain part (e.g., chain part and chain core 110 associated with chain core 108) proposed for the swap of information and status information related to a particular iteration of a distributed Markov chain Monte Carlo procedure. It may include information related to a particular pair of chain portion associated with).

Processing may continue with operation 330 to “exchange information” at operation 328, where the chain thread 120 is sufficient for another chain thread (eg, chain thread 320) to determine if a swap should occur. Exchange information with

Operations 332-336 may occur after, along and / or before operations 328-330. In operation 332, "request a swap proposal", the chain thread 120 may request one or more additional swap proposals. For example, chain thread 120 may request one or more additional swap proposals while waiting for another chain thread (eg, chain thread 320) proposed for potential swap. In some examples, similar operations 334 may occur via chain thread 320. Processing may continue with operation 336 to “distribute swap proposals” in operations 332 or 334, where one or more additional swap proposals are requested via chained cores 108, 110 via swap proposal core 106. , And / or 112). For example, the swap proposal may be distributed from the swap proposal creation queue 122 (see FIG. 1), received by the chain core 108, and swap proposal distribution queue 124 (FIG. 1) for later use. Can potentially be stored.

Processing may continue to operation 338, in operation 330, "determining whether to swap states", where a determination may be made whether or not to swap states. For example, the first chain core 108 and / or the second chain core 110 may be configured to include a proposed swap based at least in part on one or more of the swap proposals stored in the swap proposal distribution queue 124 (see FIG. 1). It may be a target. One of the chain cores (eg, the first chain core 108 and / or the second chain core 110) subject to the proposed swap may determine whether to swap based at least in part on the exchange information of operation 330. have.

Processing may continue with operation 340 to “process the chain” in operation 338, where subsequent iterations of the first chain portion may be processed through the chain core 108. For example, where states are swapped, subsequent iterations of the first chain portion may be processed based at least in part on the random number stored in the random bit queue 128 (see FIG. 1) and the states swapped from the second chain. . For example, the chain thread 120 associated with the chain core 108 may process such chain portion based at least in part on a state swapped from the second chain thread 320 associated with the second chain core 110. In some examples, similar operations 342 may occur via chain thread 320.

In operation, process 300 may proceed to generate a random number through chain core 108 without interruption in standby of chain core 108 in operation 328. Similarly, process 300 may proceed to generate a swap proposal through swap proposal core 106 without interruption in standby of chain core 108 at operation 328. Additionally, process 300 may proceed to generate swap proposals through swap proposal core 106 without interruption during distribution of swap proposal distribution thread 116 in operations 304 and 336. In addition, process 300 can preserve the statistical performance of the distributed Markov chain Monte Carlo procedure. For example, compared to the result of not utilizing the process 300, the use of the process 300 may not require statistical adjustments to the results of the distributed Markov chain Monte Carlo procedure.

4 illustrates an example computer program product 400 arranged in accordance with at least some embodiments of the present disclosure. Computer program product 400 may include a signal bearing medium 402. The signal bearing medium 402, if executed by one or more processors, can cause multiple crashes of a multi-core process that may enable the computing device to provide the functionality described above with respect to FIGS. 1, 2, and / or 3. One or more machine-readable instructions 404 may be included to facilitate communication between multiple collision domain networks. Thus, for example, referring to the system of FIG. 1, the multi-core processor 100 may perform one or more of the operations shown in FIGS. 2 and / or 3 in response to the instructions 404 carried by the medium 402. Can be performed.

In some implementations, signal bearing media 402 can include, but is not limited to, computer readable media 406, such as hard disk drives, compact disks (CDs), digital video disks (DVDs), digital tapes, memories, and the like. It doesn't work. In some implementations, the signal bearing medium 402 can include, but is not limited to, a recordable medium 408 such as a memory, read / write (R / W) CD, R / W DVD, and the like. In some implementations, the signal bearing medium 402 can include a communication medium 410 such as digital and / or analog communication media (eg, fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). May be, but is not limited thereto.

5 is a block diagram illustrating an example computing device 500 arranged in accordance with at least some embodiments of the present disclosure. In one exemplary basic configuration 501, computing device 500 may include one or more processors 510 and system memory 520. Memory bus 530 may be used to communicate between processor 510 and system memory 520.

Depending on the configuration desired, the processor 510 may be of any type including, but not limited to, a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Do not. The processor 510 may include one or more levels of a cache, such as a level 1 cache 511, a level 2 cache 512, a processor core 513, and a register 514. The processor core 513 may include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP Core), or any combination thereof. Memory controller 515 may also be used with processor 510, or in some implementations, memory controller 515 may be an internal part of processor 510.

Depending on the configuration desired, the system memory 520 may be of any type including volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof, Do not. System memory 520 may include an operating system 521, one or more applications 522, and program data 524. The application 522 performs the functions and / or operations as described herein, including the functional blocks and / or operations described with respect to the process 200 of FIG. 2 and / or the process 300 of FIG. 3. And cores usage maintenance algorithm 523, which may be arranged to. Program data 524 may include swap proposal data 525 for use with the core usage management algorithm 523. In some demonstrative embodiments, application 522 may be arranged to operate on program data 524 on operating system 521 such that an implementation of core usage management may be provided as described herein. This described basic configuration is illustrated by its components in dashed line 501 in FIG.

Computing device 500 may have additional features or functionality, and additional interfaces to facilitate communication between the basic configuration 501 and any desired devices and interfaces. For example, bus / interface controller 540 may be used to facilitate communication between basic configuration 501 and one or more data storage devices 550 via storage interface bus 541. The data storage device 550 may be a removable storage device 551, a non-removable storage device 552, or a combination thereof. Examples of removable storage devices and non-removable storage devices include magnetic disk devices such as flexible disk drives and hard disk drives (HDD), compact disk (CD) drives, or digital versatile disks (DVD) An optical disk drive such as a drive, a solid state drive (SSD), and a tape drive. Exemplary computer storage media includes volatile and nonvolatile removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules, or other data, Media.

System memory 520, removable storage 551, and non-removable storage 552 are all examples of computer storage media. Computer storage media may include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROMs, digital versatile disks (DVDs) or other optical storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices or other magnetic storage devices, or Any other medium that can be used to store the required information and can be accessed by the computing device 500 includes, but is not limited to. Any such computer storage media may be part of device 500.

Computing device 500 also provides an interface bus (e.g., an interface bus) to facilitate communication from various interface devices (e.g., output interfaces, peripheral interfaces, and communication interfaces) to underlying configuration 501 via bus / interface controller 540. 542). Exemplary output interface 560 may include a graphics processing unit 561 and an audio processing unit 562 that may be coupled to one or more A / V ports 563 to communicate with various external devices, Lt; / RTI &gt; The exemplary peripheral interface 570 may include a serial interface controller 571 or a parallel interface controller 572 which may be coupled to an input device (e.g., a keyboard, a mouse, a pen, A voice input device, a touch input device, etc.) or other peripheral device (e.g., a printer, a scanner, etc.). Exemplary communication interface 580 includes network controller 581, which may be arranged to facilitate communication with one or more other computing devices 590 via network communication via one or more communication ports 582. . A communication connection is one example of a communication medium. Communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information delivery media can do. A "modulated data signal" may be a signal having one or more characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media may include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared (IR) , But is not limited thereto. The term computer readable media as used herein may include both storage media and communication media.

Computing device 500 may be a mobile phone, personal data assistant (PDA), personal media playback device, wireless web-watch device, personal headset device, special purpose device, or any of the above functions. It can be implemented as part of a small form factor portable (mobile) electronic device, such as a fusion device including that of. Computing device 500 may also be implemented as a personal computer that includes both a laptop computer and a non-laptop computer configuration. In addition, computing device 500 may be implemented as part of a wireless base station or other wireless system or device.

Portions of the foregoing detailed description are presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored in a computing system memory, such as a computer memory. These algorithmic descriptions or representations are examples of techniques that those skilled in the data processing arts may use to convey the substance of their work to others skilled in the art. Here and in general, an algorithm is considered to be a consistent sequence of operations or similar processing leading to a desired result. In this context, operation or processing involves physical manipulation of physical quantities. Usually, but not necessarily, such amounts can take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared or otherwise manipulated. It has proven convenient sometimes to refer to such a signal as bits, data, values, elements, symbols, characters, terms, numbers or numbers, etc., It is to be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, as will be apparent from the following discussion, the use of terms such as “processing”, “computing”, “calculation”, “determination”, and the like throughout the discussion herein refers to memory of a computing device. , Registers, or other information storage devices, transmission devices, or display devices, are recognized as being related to the operation or process of a computing device that manipulates or transforms data represented by physical, electronic or magnetic quantities.

The foregoing detailed description has described various embodiments and / or processes of the apparatus via block diagrams, flow charts, and / or examples. As long as such block diagrams, flowcharts, and / or examples include one or more functions and / or actions, those skilled in the art will recognize that each function and / or operation in such block diagrams, flowcharts, or examples may be implemented in hardware, software, firmware, It will be appreciated that they may be implemented individually and / or collectively by a wide range of any combination thereof. In one embodiment, some portions of the subject matter described in this disclosure may be implemented in the form of an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), or other integrated form. However, those skilled in the art will appreciate that some aspects of embodiments of the present disclosure may be implemented as a combination of one or more computer programs (e.g., one or more programs running on one or more computer systems) running on one or more computers, It will be appreciated that the invention may be implemented in an integrated circuit, in whole or in part, even with more than one program (e.g., one or more programs running on one or more microprocessors), firmware or substantially any combination thereof, And / or the design of the circuitry will be apparent to those skilled in the art in light of this disclosure. It will also be understood by those skilled in the art that the mechanisms of the subject matter of the present disclosure may be distributed in various types of program products, and examples of objects of the present disclosure include signal bearings medium &lt; / RTI &gt; Examples of signal bearing media include readable type media such as floppy disks, hard disk drives, CD, DVD, digital tape, computer memory, etc., digital and / or analog communication media Wired communication link, wireless communication link, etc.), but is not limited thereto.

The objects described herein sometimes represent different components included or connected to different different components. It should be understood that such an architecture shown is merely exemplary and that many other architectures that achieve substantially the same functionality can be implemented. Conceptually, any arrangement of components to achieve the same functionality is effectively "associated " to achieve the desired functionality. Thus, any two components coupled here to achieve a particular function can be seen as "associated" with each other so that the desired functionality is achieved, independent of the architecture or intermediate components. Likewise, the two associated components may also be considered "operatively connected" or "operatively linked" to one another to achieve the desired functionality, and any two components that may be associated therewith also Can be seen as "operatively connectable" to one another to achieve the desired functionality. Specific examples of operatively linkable include components that are physically compatible and / or physically interacting and / or wirelessly interacting and / or wirelessly interacting with components and / But are not limited to, components that interact and / or logically interact.

As used herein with respect to the use of substantially any plural and / or singular terms, those skilled in the art can interpret plural as singular and / or plural singular, as appropriate for the context and / or application. The various singular / plural substitutions may be explicitly described herein for clarity.

Those skilled in the art will recognize that the terms used in this disclosure in general and specifically used in the appended claims (e.g., the appended claims) generally refer to terms "open" Will be understood to imply the inclusion of a feature or function in a given language, such as, but not limited to, the word " having " It will also be appreciated by those of ordinary skill in the art that if a specific number of the recited items is intended, such intent is expressly set forth in the claims, and that such recitations, if any, are not intended. For example, to facilitate understanding, the following claims are intended to incorporate the claims, including the use of introduction phrases such as "at least one" and "one or more". It is to be understood, however, that the use of such phrases is not intended to limit the scope of the present invention to the use of an indefinite article "a" or "an" And should not be construed to limit the inclusion of a particular claim and should not be construed to imply that the same claim is not to be construed as an admission that it has been disclosed as an adverbial phrase such as "one or more" or "at least one" and " Quot; one "should be interpreted generally as meaning" at least one "or" at least one "). This also applies to the case of articles used to introduce claims. It will also be appreciated by those skilled in the art that, even if a specific number of the recited claims is explicitly recited, those skilled in the art will recognize that such recitation is generally based on at least the recounted number (e.g., "Quot; means &lt; / RTI &gt; at least two entries or more than one entry). Also, where rules similar to "at least one of A, B and C, etc." are used, it is generally intended that such interpretation is intended to be understood by those skilled in the art (e. C has at least one of A, B, C alone, A and B together, A and C together, B and C together, or A , B, and C together). If a rule similar to "at least one of A, B, or C" is used, then generally such interpretation is intended to assume that a person skilled in the art will understand the rule (e.g., A " and " B " together, A and C together, B and C together, or A, B, C together). It will also be understood by those skilled in the art that substantially any disjunctive word and / or phrase that represents more than one alternative term, whether in the detailed description, the claims or the drawings, , Or any combination of the terms &lt; RTI ID = 0.0 &gt; and / or &lt; / RTI &gt; For example, the phrase "A or B" will be understood to include the possibility of "A" or "B" or "A and B".

Although specific example techniques have been described and illustrated herein using various methods and systems, it should be understood by those skilled in the art that various other modifications can be made, and equivalents may be substituted, without departing from the claimed subject matter. In addition, many modifications may be made to adapt a particular situation to the teachings of the claimed subject matter without departing from the central concept described herein. Thus, although the claimed subject matter is not limited to the specific examples disclosed, it is intended that such claimed subject matter may also include all embodiments falling within the scope of the appended claims and their equivalents.

Claims (20)

As a method for implementing a distributed-type Markov chain Monte Carlo procedure,
Generating, via a swap proposal core, a plurality of swap proposals associated with the distributed Markov chain Monte Carlo procedure;
Receiving one or more of the swap proposals from the swap proposal core via a first chain core;
Generating a plurality of random numbers through the first chain core;
Processing, via the first chain core, a current iteration of the first chain portion of the distributed Markov chain Monte Carlo procedure based at least in part on the plurality of random numbers; And
Waiting through the first chain core, the current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure associated with the second chain core based at least in part on one or more of the swap proposals to reach a corresponding iteration. Including;
The generation of the random number through the first chain core is interrupted while waiting for the second chain core through the first chain core to reach a corresponding iteration of the distributed Markov chain Monte Carlo procedure. A method for implementing a distributed Markov chain Monte Carlo procedure. The method of claim 1,
The generation of the swap proposal through the swap proposal core proceeds without interruption while waiting for the second chain core to reach the corresponding iteration of the distributed Markov chain Monte Carlo procedure via the first chain core. , Method for implementing a decentralized Markov chain Monte Carlo procedure. The method of claim 1,
Storing one or more of the swap proposals through a swap proposal generation queue; And
Distributing, through the swap proposal core, one or more of the swap proposals from the swap proposal generation queue to the first chain core.
Method for implementing a distributed Markov chain Monte Carlo procedure further comprising. The method of claim 1,
Storing, via a first swap proposal distribution queue, one or more of the swap proposals received via the first chain core, wherein the first swap proposal distribution queue is associated with the first chain core and is associated with the first chain core. 2 Swap proposal distributed queue is associated with the second chain core, the method of implementing a distributed Markov chain Monte Carlo procedure. The method of claim 1,
Storing one or more of the plurality of random numbers via a first random bit queue, wherein the first random bit queue is associated with the first chain core and is a second random bit queue. Is associated with the second chain core, a method for implementing a distributed Markov chain Monte Carlo procedure. The method of claim 1,
After waiting for the second chain core through the first chain core to reach the corresponding iteration of the distributed Markov chain Monte Carlo procedure, the method further comprises:
Distributing, through the swap proposal core, additional swap proposals to the first chain core and the second chain core;
A second chain, through the first chain core and / or the second chain core, a state associated with the first chain portion based at least in part on one or more of the swap proposals stored through a swap proposal distribution queue. Determining whether to swap with a state associated with the wealth; And
Processing subsequent iterations of the first chain portion based at least in part on the plurality of random numbers stored via the first chain core and via the random bit queue and the state swapped from the second chain portion. A method for implementing a distributed Markov chain Monte Carlo procedure comprising. The method of claim 1,
And said distributed Markov chain Monte Carlo procedure comprises a Metropolis-coupled-type Markov chain Monte Carlo procedure. The method of claim 1,
And a particular swap proposal includes information related to the first chain portion, the second chain portion, and a particular repetition. The method of claim 1,
Wherein said method is for preserving the statistical performance of said distributed Markov chain Monte Carlo procedure. A multi-core processor comprising a plurality of processor cores,
A swap proposal core configured to generate a plurality of swap proposals associated with the distributed Markov chain Monte Carlo procedure;
Receive one or more of the swap proposals from the swap proposal core, generate a plurality of random numbers, and perform a current iteration of the first chain portion of the distributed Markov chain Monte Carlo procedure based at least in part on the plurality of random numbers. A first chain configured to wait for a current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure associated with a second chain core based at least in part on one or more of the swap proposals to reach a corresponding iteration. core; And
The second chain core configured to handle a current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure,
Wherein the first chain core is further configured to continue generating a random number without interruption while waiting for the second chain core to reach a corresponding iteration of the distributed Markov chain Monte Carlo procedure. 11. The method of claim 10,
The swap proposal core is further configured to continue generating the swap proposal without interruption while waiting for the second chain core to reach the corresponding iteration of the distributed Markov chain Monte Carlo procedure. 11. The method of claim 10,
A swap proposal generation queue configured to store one or more of the swap proposals,
The swap proposal core is further configured to distribute one or more of the swap proposals from the swap proposal generation queue to the first chain core. 11. The method of claim 10,
A first swap proposal distribution queue, configured to store one or more of the swap proposals received via the first chain core, wherein the first swap proposal distribution queue is associated with the first chain core; And
A second swap proposal distribution queue configured to store one or more of the swap proposals received via the second chain core, wherein the second swap proposal distribution queue is associated with the second chain core
Multi-core processor further comprising. 11. The method of claim 10,
A first random bit queue configured to store one or more of the plurality of random numbers, the first random bit queue associated with the first chain core; And
A second random bit queue configured to store one or more of the plurality of random numbers, the second random bit queue associated with the second chain core
Multi-core processor further comprising. A computing device comprising a plurality of processor cores,
Multi-core processor;
Memory bus; And
A system memory configured to communicate with the multi-core processor via the memory bus,
The multi-
A swap proposal core configured to generate a plurality of swap proposals associated with a distributed Markov chain Monte Carlo procedure,
A first chain core, receiving one or more of the swap proposals from the swap proposal core, generating a plurality of random numbers, and based on the distributed Markov chain Monte Carlo procedure based at least in part on the plurality of random numbers. Process the current iteration of the first chain portion and allow the current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure associated with the second chain core to reach a corresponding iteration based at least in part on one or more of the swap proposals. A first chain core configured to wait, and
The second chain core configured to handle the current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure,
And the first chain core is further configured to continue generating a random number without interruption while waiting for the second chain core to reach a corresponding iteration of the distributed Markov chain Monte Carlo procedure. 16. The method of claim 15,
And the swap proposal core is further configured to continue generating the swap proposal without interruption while waiting for the second chain core to reach the corresponding iteration of the distributed Markov chain Monte Carlo procedure. 16. The method of claim 15,
The swap proposal core further includes a swap proposal generation queue configured to store one or more of the swap proposals,
And the swap proposal core is further configured to distribute one or more of the swap proposals from the swap proposal generation queue to the first chain core. 16. The method of claim 15,
The first chain core includes a first swap proposal distribution queue configured to store one or more of the swap proposals received via the first chain core;
The second chain core includes a second swap proposal distribution queue configured to store one or more of the swap proposals received via the second chain core;
The first chain core further comprises a first random bit queue configured to store one or more of the plurality of random numbers, the first random bit queue associated with the first chain core; And
And the second chain core further comprises a second random bit queue configured to store one or more of the plurality of random numbers. A computer readable storage medium comprising stored machine-readable instructions, wherein the instructions, when executed by one or more processors, cause the computing device to:
Generating, through the swap proposal core, a plurality of swap proposals associated with the distributed Markov chain Monte Carlo procedure;
Generating a plurality of random numbers through the first chain core;
Processing, through the first chain core, a current iteration of the first chain portion of the distributed Markov chain Monte Carlo procedure based at least in part on the plurality of random numbers; And
The current iteration of the second chain portion of the distributed Markov chain Monte Carlo procedure associated with the second chain core based at least in part on one or more of the swap proposals received from the swap proposal core through the first chain core corresponds to Enabling the waiting to be reached, through the first chain core, to reach an iteration,
The generation of the random number through the first chain core proceeds without interruption while waiting for the second chain core through the first chain core to reach a corresponding iteration of the distributed Markov chain Monte Carlo procedure. ,
The generation of the swap proposal through the swap proposal core proceeds without interruption while waiting for the second chain core through the first chain core to reach a corresponding iteration of the distributed Markov chain Monte Carlo procedure. Computer-readable storage media. 20. The method of claim 19,
The instructions, when executed by the one or more processors, cause the computing device to:
Storing, via a swap proposal creation queue, one or more of the swap proposals;
Distributing, via the swap proposal core, one or more of the swap proposals from the swap proposal generation queue to the first chain core;
Storing, via a first swap proposal distribution queue, one or more of the swap proposals received through the first chain core, wherein the first swap proposal distribution queue is associated with the first chain core and distributes a second swap proposal distribution. A cue is associated with the second chain core;
Storing, via a random bit queue, one or more of the plurality of random numbers, the random bit queue associated with the first chain core and a second random bit queue associated with the second chain core. Computer readable storage medium.

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