KR101373699B1 - Multi core multi thread system and multi core process management method under mobile circumstance - Google Patents

Abstract

The present invention relates to a process management method of a multi-core multi-threaded system that executes a plurality of cores including a first core and a second core and a plurality of threads within each core. The first step is terminated, and the third step in which a SYNC instruction is issued to a plurality of threads in the first core and the second core after the second and second steps in which all threads in the second core are finished. Provided is a process management method of a multi-core multi-threaded system comprising a.

Description

MULTI CORE MULTI THREAD SYSTEM AND MULTI CORE PROCESS MANAGEMENT METHOD UNDER MOBILE CIRCUMSTANCE

The present invention relates to a branching method for single-process parallelism of a multi-core multi-threaded system in a mobile environment. More specifically, multi-threaded multi-threaded processing is performed by using a branch instruction only in a single process execution without a separate thread management host processor. The present invention relates to a branching method for single process parallelization of a multi-core multi-threaded system of a mobile environment suitable for a mobile environment.

Recently, in the computer field, multi-core processors having a plurality of cores in one processor have been developed due to the importance of multimedia performance requiring multitasking and a plurality of high-speed operations. Multi-core processors can improve processing performance because a plurality of cores share a task. In addition, compared to the use of multiple processors can be shared other than the core has the advantage of low manufacturing cost and small size.

IBM's Cell Processor and nVidia's CUDA manage multiple cores and threads through a Power Processing Element (PPE) and a Thread Manager, respectively. This design requires another host processor to manage them in addition to the processors that perform the actual work. This architecture requires the creation of programs for separate host processors in addition to the programs to be run on the processor, which wastes space and power from a hardware perspective and software for a separate host processor from a software perspective. Therefore, additional cost is required. This design is a good way to maximize performance among multi-core and multi-threaded management in personal computer (PC) environments with low power consumption and chip area limitations, but it is a burdensome method for use in mobile environments with limited resources. to be. Therefore, in order to eliminate the separate host processor, each core must play the role of the host processor at the same time.

IBM's Cell Processor is largely divided into PPE units and SPE units, which can be thought of as PowerPC CPUs. SPE is the core core that drives multiple threads with the Stream Processor Element. The SPE has a local memory inside to accumulate a certain amount of data to be computed and communicate with the PPE through an interrupt line. When the SPE is finished, it takes a flexible structure, making it clear that the PPE is interrupted and instructs the next task. However, the SPE is not active and acts as a slave processor under the control of the PPE.

nVidia's CUDA processor is a General Purpose Computing on Graphics Processing Unit (GP-GPU) designed for graphics cards but used in a variety of applications. CUDA has a separate thread manager that manages a large number of thread processors. Also, since CUDA is a structure in which several threads are executed by one instruction at the same time, a thread that does not execute when there is a programming structure such as a conditional branch is inefficient. This structure reduces performance of individual cores, but can greatly improve performance when running simple, fixed functions by greatly increasing the number of threads that can be processed at one time.

In order to execute the program, CUDA Processor also needs to write a binary program separately in both thread and thread manager like IBM Cell. Although the CUDA SDK has been abstracted to make programming easier, the actual operation of CUDA is unknown, and there are limitations that must be designed by the method provided by the CUDA SDK, and have a proprietary structure that can not be participated by third-party vendors. You can limit performance.

Although IBM's Cell and nVidia's CUDA architectures have advantages and disadvantages, they all have a structure in which each core is executed by an external core manager. This structure is easy to expand to multicore because a separate manager allocates workload per thread in terms of workload allocation, and shows high performance in a PC environment where power consumption and chip area are limited. The use of such a structure has a burden on power consumption, heat generation, and chip area.

In order to apply the same method to the GP-GPU in a mobile environment, a separate host processor and a processing program are required, which is not suitable for a GP-GPU in a mobile environment. Therefore, GP-GPU in mobile environment needs processing method to replace task management with new core and thread management instructions that eliminated host processor.

An object of the present invention is to provide a multithreaded management method through various branch instruction structures of a single process program without a separate thread management module in a multicore multithreaded structure.

The above object of the present invention is a multi-threaded system that performs a plurality of cores and a plurality of threads in each core, the thread flag register indicating whether or not to perform each thread performed in each core and is performed for each core And a core flag register indicating whether there is at least one thread, and having a multi-threaded system structure by a separate branch instruction structure.

According to the present invention, when thread synchronization between cores is required, all threads except the last thread of each core are terminated through a SYNC instruction, and the hardware complexity is simplified and the implementation is simplified by comparing only one unterminated thread of each core. It is also possible to manage cores with instructions in a single program without a separate core management program. Using this instruction set, you can write multi-core and multi-threaded programs as if you were writing a single threaded program. You can efficiently self-manage threads on each core without external multi-core or multi-thread managers. This eliminates the need for multi-core or multi-thread managers and separate programs for them, reducing power, chip size, and the cost of developing a dual-threaded thread management program during software development. In addition, the multi-core of this design is a scalable multi-core that can be expanded and reduced up to 16, so that programming can be made independent of the number of cores. Therefore, no additional code modification is required even if the number of cores changes.

In addition, a global scratch counter has been set up for fast workload allocation, and each thread returns a different value to each core even if a request comes from each core at the same time without setting a critical section. References can be made to allocate workload at high speed.

1 is a command flow diagram illustrating an all branch instruction used in the present invention.
2 is a command flow diagram illustrating a seq branch instruction used in the present invention.
3 is a flow chart of a multicore multiprocess instruction processing in one embodiment in accordance with the present invention.
4 is an explanatory diagram showing a state of a flag register of an embodiment according to the present invention that enables execution of the thread task of FIG. 1 over time; FIG.

The present invention extends a single-core based multi-thread management scheme to replace the host processor role with instructions in GP-GPU in a multi-core environment so that each core thread is a scratch counter without an external multi-core manager. It is an efficient structure that can actively allocate work through

However, this structure, in which each thread allocates work through scratch counters without a separate external thread manager, has some problems when it is extended to multicore. The problem is that different cores need to watch for threads inside each other, and when using a scratch counter, multiple cores have to access the scratch counter at the same time. You can solve this problem by setting up a critical section, but setting up a critical section can put all other threads on standby except the one that is being accessed, resulting in performance degradation.

Best Mode for Carrying Out the Invention Hereinafter, a preferred embodiment of a glass surface foreign matter inspection apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, in addition to the general branch instruction in the core, there are instructions called all, seq, and sync. The all branch instruction is a multithreaded instruction that is activated by the same program specified at the same time as another empty thread in one core. 1 is a flowchart illustrating an all branch instruction. Referring to FIG. 1, in one core, a 0 thread, a 1 thread, a 2 thread, a 3 thread, and a 4 thread (# 4 Thread) is running, and when the all branch instruction is executed, an empty first thread (# 0 thread), first thread (# 1 thread), second thread (# 2 thread), and third thread Thread (# 3 Thread) shows that Process B runs in a multi-threaded fashion.

The seq branch instruction terminates when there is a running thread other than itself in a core, indicating that the thread is empty, and branching to the specified program when all threads other than itself are empty. 2 is a flowchart illustrating a seq branch instruction. Referring to FIG. 2, there is a 0 thread, a 1 thread, a 2 thread, and a 3 thread in a core. , The 0th thread, the 3rd thread, the 2nd thread, and the 1st thread are terminated in the waiting state, and when the first thread that has finished execution is terminated, only one first thread in the same core remains. In this case, it indicates a state ready to branch to the designated program.

The sync branch command is the same branch as the seq command and is executed after waiting for a single thread to be executed within all other cores.

3 is a flow chart of a multicore multiprocess instruction processing in one embodiment in accordance with the present invention. The clarification process flow shown in FIG. 3 does not require a separate control unit, does not require a critical section setting, and has a structure capable of quickly transacting work with a simple structure. A SYNC instruction has been added to manage multiple threads of multiple cores. The SYNC instruction performs synchronization and thread termination of all cores.

In the present invention, since the synchronization is completed while leaving only one thread in each core through the SYNC instruction, the complexity does not increase significantly compared to only one thread for each core. When synchronization is required or when a program is run with a single thread, it is a structure that can guarantee synchronization and when the thread is terminated.

In FIG. 3, two cores (core # 0) and a first core (core # 1) are configured, and three threads (Thread # 0, Thread # 1, and Thread # 2) are performed on each core. Shows the multi-core multi-threaded instruction execution flow. All threads of the 0th core and the 1st core are performing process 'A', and in the 1st core, the 0th thread (Thread # 0), the 2nd thread (Thread # 2), and the 1st thread (Thread # 1) It is assumed that the threads are terminated in order, and then the threads are terminated in order of the 0th thread (Thread # 0), the second thread (Thread # 2), and the first thread (Thread # 1) of the 0th core. In the present invention, the SYNC instruction is used to wait for the last thread of another core to terminate and then synchronize. All threads in the first core are terminated at the time between t0 and t1 shown in the left side of FIG. 3, but since the thread of the 0th core is still performing work, the first thread of the first core notifies that the thread is terminated. If all threads of the 0th core are terminated after waiting without performing the first thread, the first thread is notified of the thread termination by the SYNC command. After that, by executing the ALL command at time t4, the process for process 'C' is divided.

The operation of the SYNC instruction terminates the threads of each core when the SYNC instruction is accessed while the threads of all the cores are working as shown in FIG. 3, and the last thread marked is not terminated. The commands will wait until the SYNC command is entered. After all the threads of the core meet the SYNC instruction, it will come out of standby and continue the program afterwards. At this point, the next task is performed, and the next thread is executed by all threads at the same time. The end point is different during each operation. Since the SYNC instruction ensures that all other threads that do the same operation are terminated, this enables synchronization of each core and subsequently transacts or terminates with a new operation through the whole branch instruction. Can be performed.

In addition, in this structure, core and thread management is performed through instructions in one program, so it is possible to maintain the advantages of not requiring a separate program for managing each core and each thread in a multi-core environment. Efficient multicore and multithreaded management is achieved.

4 is an explanatory diagram illustrating a state of a flag register of an embodiment according to the present invention enabling execution of the thread task of FIG. 3 over time. Each core is provided with a thread flag register that indicates whether a thread is running in the core, and whether or not there is a thread running in each core in a multicore multithreaded system. A core flag register is provided. The core flag register is provided in a multi-core multithreaded system in a separate circuit configuration rather than the core.

Specifically, FIG. 4 will be described. The zeroth core is provided with a thread flag register 10, and the second to fourth bits are flags 11, 13, and 15 indicating the states of the zeroth thread, the first thread, and the second thread, respectively, performed in the zeroth core. ) Is provided. Similarly, the first core is provided with a thread flag register 20, and the second to fourth bits, respectively, flags 21 and 23 indicating the states of the 0th thread, the first thread, and the second thread performed in the first core. , 25). The core flag register 30 indicates whether there are threads running in the 0th core and the 1st core, respectively using the second and third bits.

At the time t0, since all threads of the 0th core are performing work, the second to fourth bits of the thread flag register 10 of the 0th core are marked as "111", and the 0th thread and the 2nd thread of the first core are marked as "111". Is terminated and the first thread is running, so the second to fourth bits of the thread flag register 20 of the first core are marked with " 010. " At this time, the second bit and the third bit of the core flag register 30 are stored as "11" to indicate that a thread is running in the 0th core and the 1st core.

At the time t1, the 0th thread of the 0th core is terminated, and since the first thread and the second thread are running, the second to fourth bits of the thread flag register 10 of the 0th core are marked as "011", and the first thread is the first thread. Since all threads of the core are terminated, the second to fourth bits of the thread flag register 20 of the first core are represented by "000". At this time, the second bit and the third bit of the core flag register 30 are stored as "10", and it can be seen that no thread is running in the 0th core but no thread is running in the first core.

At the time t2, the 0th thread and the 2nd thread of the 0th core are terminated, and since the 1st thread is running, the 2nd to 4th bits of the thread flag register 10 of the 0th core are represented by "010", Since all threads of the core are terminated, the second to fourth bits of the thread flag register 20 of the first core are represented by "000". At this time, the second bit and the third bit of the core flag register 30 are stored as "10", and it can be seen that no thread is running in the 0th core but no thread is running in the first core.

At the time t3, all the threads of the 0th core are terminated, so the second to fourth bits of the thread flag register 10 of the 0th core are marked as "010", and all the threads of the first core are terminated, so that the threads of the first core are terminated. The second to fourth bits of the flag register 20 are represented by "000". At this time, the second bit and the third bit of the core flag register 30 are stored as "00", and it can be seen that there are no threads running in the zeroth core and the first core.

In addition, in this multi-core multi-threaded system, the workload allocation using the previous scratch counter has a problem in that the conventional scratch counter is applied to the multi-core because several cores need to access the scratch counter at the same time. Global Scratch Counter) method was used.

The global scratch counter is designed to allow four operations: Get (read), Inc (+1 increase after read), Set (component write), and Limit (write limit). The Global Scratch Counter computes this from cores when an Inc request, where multiple cores request the value of a concurrent global scratch counter and increments it simultaneously, calculates the value of the current global scratch counter for each core and the value to add to each core. You can compute dogs and pass different values to each core in one cycle. This allows each core to efficiently allocate workload by using different values obtained through global scratch counters.

Using this global scratch counter, each core can have a different value in one cycle without a critical section, thus enabling a structure that can allocate workload at high speed without waiting.

In the present invention, the multi-core multi-threaded system refers to a semiconductor chip (for example, a processor) or an electronic device including the same, in which a plurality of cores are provided and a plurality of threads are performed in each core.

While the preferred embodiments of the present invention have been described and illustrated above using specific terms, such terms are used only for the purpose of clarifying the invention, and the embodiments of the present invention may be embodied in various forms without departing from the spirit or scope of the following claims It is evident that various changes and changes may be made.

10, 20: thread flag register
11, 13, 15, 21, 23, 25: Flag indicating whether or not each thread is running
30: core flag register
31, 33: flags indicating the presence of threads running within each core

Claims (4)

delete delete A process management method of a multi-core multi-threaded system for performing a plurality of cores including a first core and a second core and a plurality of threads in each core,
A first step in which execution of all threads in the first core ends;
A second step in which execution of all threads in the second core ends; and
A third step of giving a SYNC command to a plurality of threads in the first core and the second core after the second step,
During the period between the first step and the third step, the thread of the first core remains in a waiting state without performing a process,
And after the third step, the first core and the second core further comprise a fourth step of exiting the standby state and simultaneously processing a new process.
The method of claim 3, wherein
As the step performed between the first step and the third step,
In case of requesting 1 increment command that requests multiple cores at the same time and increments at the same time, calculates the current counter value for each core and two values to be added for each core, so that the different counter values for each core in one cycle And a fifth step of returning the multi-core multithreaded system.

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