KR101370809B1 - Apparatus for sensing a capacitance for a multi-touch panel and multi-touch sensing device having the same - Google Patents

Abstract

The capacitive sensing circuit for a multi-touch panel integrates a charge corresponding to a rising cycle and a falling cycle of a transmission circuit unit for applying a square wave transmission signal to a transmission line and a square wave transmission signal applied from the transmission circuit unit, respectively. And a receiving circuit unit which detects a difference in capacitance generated between the transmission line and the reception line to determine whether the touch is performed. The receiving circuit unit includes an upper switch, a lower switch, an upper current mirror part, and a lower current mirror part. The upper switch is connected to the receiving line and turned on or off according to the first integration control signal. The lower switch is connected to the receiving line and the upper switch, and is turned on or off according to the second integration control signal. The upper current mirror unit is connected to the upper switch connected to the receiving line, and sets the current path with the multi-touch panel according to the on of the upper switch to mirror the current flowing along the set current path and output it through the output terminal. The lower current mirror part is connected to a node connected to the upper current mirror part, the upper switch, and a lower switch connected to the receiving line, respectively, and discharges by mirroring the current of the upper current mirror part according to the on of the lower switch.

Description

CAPACITIVE SENSING CIRCUIT FOR MULTI-TOUCH PANEL AND MULTI-TOUCH SENSOR WITH THE SAME

The present invention relates to a capacitive sensing circuit for a multi-touch panel and a multi-touch sensing device having the same, and more particularly, to a capacitive sensing circuit for sensing capacitance in a multi-touch panel capable of multi-touch. And a multi-touch sensing device having the same.

As electronic technology and information technology continue to evolve, the proportion of electronic devices in everyday life, including work environments, is steadily increasing. In recent years, the types of electronic devices have become very diverse. Portable electronic devices such as laptops, mobile phones, portable multimedia players (PMPs), and tablet PCs are pouring new design devices with new functions every day.

As the types of electronic devices encountered in everyday life are gradually diversified and the functions of each electronic device are advanced and complicated, the necessity of a user interface that can be easily learned by the user and capable of intuitive operation has been raised. A touch panel device has attracted attention as an input device capable of satisfying such a requirement, and has already been widely applied to various electronic devices.

In particular, the touch screen device, which is the most common application product of the touch panel device, detects the touch position of the user on the display screen and uses the information on the detected touch position as input information to perform overall control of the electronic device including the display screen control. Refers to a device. In the manufacture of touch screens with the popularity of such touch screen devices, the importance of the capacitance measuring circuits for touch screens and the capacitance controller semiconductors in charge thereof is increasing day by day.

Therefore, the technical problem of the present invention has been made in view of the above, the object of the present invention is a multi-design designed to detect a multi-touch operation with a simple circuit configuration, fast capacitance detection speed, good sensitivity to noise To provide a capacitive sensing circuit for the touch panel.

Another object of the present invention is to provide a multi-touch sensing device having the capacitive sensing circuit for the multi-touch panel described above.

In order to achieve the above object of the present invention, a multi-touch panel capacitance sensing circuit according to an embodiment is connected to a transmission line of a multi-touch panel, and transmits a square wave transmission signal to the transmission line. Circuit section; And connected to the receiving line of the multi-touch panel, when the user's human body contact occurs integrating the charge corresponding to the rising period and the falling period of the square wave transmission signal applied from the transmission circuit unit, respectively, the transmission line and the reception And a receiving circuit unit which detects a difference in capacitance generated between lines to determine whether a touch occurs. The receiving circuit unit includes an upper switch, a lower switch, an upper current mirror part, and a lower current mirror part. The upper switch has a first end connected to the receiving line and turned on or off according to a first integration control signal applied to a control end. The lower switch has a first end connected to the receiving line and a second end of the upper switch and turned on or off according to a second integration control signal applied to a control end. The upper current mirror unit is connected to the second end of the upper switch, sets the current path with the multi-touch panel according to the on of the upper switch, mirrors the current flowing along the set current path, and outputs it through the output terminal. . The lower current mirror part is connected to a node connected to the upper current mirror part, the upper switch, and a second end of the lower switch, respectively, and flows along a set current path with the multi-touch panel according to the on of the lower switch. The upper current mirror part is mirrored to discharge the electric current in correspondence with the current.

In one embodiment of the present invention, the upper current mirror portion and the lower current mirror portion, the voltage induced by the touch when the received signal is provided through the receiving line, the rising edge time and falling edge time of the received signal The corresponding charge of the received signal may be integrated and output through the output terminal.

In an embodiment of the present disclosure, the upper current mirror unit may include a plurality of transistors disposed in two stages in a current mirror relationship.

In one embodiment of the present invention, the upper current mirror unit may include an upper master and an upper slave mirroring a current flowing through the upper master. Here, the upper master, the source is connected to the power supply voltage terminal is supplied with a power supply voltage, the gate is connected to the first slave PMOS, the source is connected to the drain of the first PMOS, the gate is the upper slave A second PMOS connected to the gate, a gate connected to the upper switch, a source connected to a third PMOS connected to the drain of the second PMOS, and a gate and a drain connected to the upper switch and the gate of the third PMOS; The source may include a fourth PMOS connected to the drain of the third PMOS.

In addition, the upper slave may include an upper PMOS unit including a plurality of PMOSs having common gates connected thereto, and a lower PMOS unit consisting of a plurality of PMOS gates commonly connected to each other.

In an embodiment of the present disclosure, the lower current mirror unit may include a plurality of transistors disposed in two stages in a current mirror relationship.

In an embodiment of the present disclosure, the lower current mirror unit may include a lower master and a lower slave mirroring a current flowing through the lower master. Here, the lower master may include a first NMOS having a gate and a drain connected in common, a drain connected to a source of the first NMOS, and a gate connected to a gate and a drain of the first NMOS, and the lower switch. A second NMOS connected to the drain; a drain connected to a source of the second NMOS; a gate connected to a drain of the second NMOS; a drain connected to a source of the third NMOS; and a gate connected to the third NMOS; It is connected to the drain of the 3 NMOS, the source may include a fourth NMOS connected to the ground voltage.

In one embodiment of the present invention, the lower slave has a drain connected to the upper current mirror portion and the upper switch, a gate of a fifth NMOS connected to the gate of the third NMOS, and a drain of the fifth NMOS. Is coupled to the gate of the fourth NMOS, and the source may include a sixth NMOS coupled to the ground voltage.

In one embodiment of the present invention, the upper current mirror unit may include an upper master and an upper slave mirroring a current flowing through the upper master. Here, the upper master, the source is connected to the power supply voltage terminal is supplied with a power supply voltage, the gate is connected to the first slave PMOS, the source is connected to the drain of the first PMOS, the drain is the upper switch A second PMOS connected to the source, a source connected to a power supply voltage terminal, a gate connected to a drain of the first PMOS, a source of the second PMOS, and a drain connected to a gate of the second PMOS; A source may be connected to a drain of the third PMOS and a gate of the second PMOS, a gate may be connected to a gate of the third PMOS, and the drain may include a first NMOS connected to a ground voltage.

In one embodiment of the present invention, the upper slave, the source is connected to the fourth PMOS connected to the power supply voltage, the drain is connected to the drain of the fourth PMOS, the gate is connected to the gate of the fourth PMOS, May include a second NMOS connected to a ground voltage, an upper PMOS portion including a plurality of PMOSs commonly connected to gates, and a lower PMOS portion including a plurality of PMOSs commonly connected to gates. In the upper PMOS unit, a source of each of the PMOSs may be connected to a power supply voltage terminal, and a common gate may be connected to the upper master, the upper switch, and the lower current mirror unit. In the lower PMOS portion, the source of each of the PMOS portions is connected to the drains of the upper PMOS portion, the gate of the fourth PMOS and the gate of the second NMOS, respectively, and the common gate is connected to the drain and the fourth PMOS. It may be connected to the drain of the second NMOS.

In an embodiment of the present disclosure, the lower current mirror unit may include a lower master and a lower slave mirroring a current flowing through the lower master. The lower master may include a third NMOS connected to a drain of the lower switch, a drain connected to a source of the third NMOS, a gate connected to a source of the third NMOS, and a drain of the third NMOS. A fifth NMOS connected to a source of the third NMOS and a drain of the fourth NMOS, a source connected to a ground voltage, a source connected to a power supply voltage terminal, and a gate connected to a fifth NMOS; The gate may be connected to a gate, a source of the third NMOS, and a drain of the fourth NMOS, and the drain may include a sixth PMOS connected to the drain of the fifth NMOS.

In one embodiment of the present invention, the lower slave has a drain connected to a seventh NMOS connected to the upper switch and the upper current mirror, a drain connected to a source of the seventh NMOS, and a gate of the lower master. An eighth NMOS connected to a gate of the fourth NMOS and the lower switch, a source connected to a drain of the eighth NMOS, a source connected to a drain of the eighth NMOS, and a source connected to a ground voltage terminal; The gate may be connected to a voltage terminal, the gate may be connected to the source of the seventh NMOS, the gate of the sixth NMOS, and the drain may include a drain of the PMOS and a seventh PMOS connected to the gate of the seventh NMOS.

In an embodiment of the present disclosure, the receiving circuit unit may further include an enable switch disposed at an end of the lower current mirror unit and turned on according to the first integration control signal to enable an operation of the lower current mirror unit. have.

In one embodiment of the present invention, the first integration control signal and the second integration control signal may be out of phase with each other.

In one embodiment of the present invention, in the rising edge period of the transmission signal of the square wave, the first integration control signal may be turned on the upper switch, the second integration control signal may be turned off the lower switch.

In one embodiment of the present invention, in the falling edge section of the transmission signal of the square wave, the first integral control signal may be turned off the upper switch, the second integral control signal may be turned on the lower switch.

In one embodiment of the present invention, in the rising edge period of the transmission signal of the square wave, the first integral control signal may be turned off the upper switch, the second integral control signal may be turned on the lower switch.

In one embodiment of the present invention, in the falling edge section of the transmission signal of the square wave, the first integral control signal may be turned on the upper switch, the second integral control signal may be turned off the lower switch.

In one embodiment of the present invention, the transmitting circuit portion and the receiving circuit portion may be implemented on one chip.

According to another aspect of the present invention, there is provided a multi-touch sensing apparatus including: a multi-touch panel including a plurality of transmission lines and a plurality of reception lines; A transmission circuit unit connected to the transmission line and applying a square wave transmission signal to the transmission line; And connected to the receiving line, and when a human body contact occurs, the charges are integrated between the transmitting line and the receiving line by integrating charges corresponding to the rising period and the falling period of the square wave transmission signal applied from the transmitting circuit unit. It includes a receiving circuit unit for detecting the difference in capacitance to determine whether the touch. The receiving circuit unit includes an upper switch, a lower switch, an upper current mirror part, and a lower current mirror part. The upper switch has a first end connected to the receiving line and turned on or off according to a first integration control signal applied to a control end. The lower switch has a first end connected to the receiving line and a second end of the upper switch and turned on or off according to a second integration control signal applied to a control end. The upper current mirror unit is connected to the second end of the upper switch, sets the current path with the multi-touch panel according to the on of the upper switch, mirrors the current flowing along the set current path, and outputs it through the output terminal. . The lower current mirror part is connected to a node connected to the upper current mirror part, the upper switch, and a second end of the lower switch, respectively, and flows along a set current path with the multi-touch panel according to the on of the lower switch. The upper current mirror part is mirrored to discharge the electric current in correspondence with the current.

According to the capacitive sensing circuit for the multi-touch panel and the multi-touch sensing device having the same, the current mirror instead of the operational amplifier (OP-AMP) is used to configure the charge integrating circuit that integrates both the rising and falling periods of the transmission signal. The circuit configuration can be simplified by constructing a circuit. In addition, by integrating in both the rising and falling periods of the transmission signal, it is possible to precisely maintain the voltage value in the change component of the output voltage after integration.

In addition, by configuring a discharge path in the reception signal in response to the charging signal of the transmission signal or by charging the charging signal of the transmission signal together in the reception signal, the amount of charge delivered to both ends of the capacitor provided in the multi-touch panel in a short period of time is reduced. Fast sensing speed can be achieved by increasing or decreasing.

In addition, semiconductors can be easily manufactured, have low power consumption, and can support multi-touch with high detection speed while being particularly resistant to noise from outside.

1 is a schematic diagram illustrating a multi-touch sensing device according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram schematically illustrating an example of the capacitive sensing circuit for the multi-touch panel of the mutual cap method shown in FIG. 1.
FIG. 3 is a waveform diagram illustrating an operation of the capacitive sensing circuit for the multi-touch panel of FIG. 2.
FIG. 4 is an equivalent circuit diagram schematically illustrating another example of the capacitive sensing circuit for the multi-touch panel of the mutual cap method shown in FIG. 1.
FIG. 5 is a waveform diagram illustrating an operation of the capacitive sensing circuit for the multi-touch panel of FIG. 4.
FIG. 6 is a circuit diagram for describing the reception circuit unit shown in FIGS. 2 and 4 as a whole.
FIG. 7 is a circuit diagram for describing a part of the reception circuit unit illustrated in FIG. 6.
FIG. 8 is a circuit diagram illustrating the upper PMOS unit, the lower PMOS unit, and the output switching unit in FIG. 7.
FIG. 9 is a circuit diagram illustrating the microdischarge current source shown in FIG. 7.
10 is a circuit diagram illustrating a switch provided in the receiving circuit unit according to the present invention.
FIG. 11 is an equivalent circuit diagram schematically illustrating another example of the capacitive sensing circuit for the multi-touch panel of the mutual cap method shown in FIG. 1.
FIG. 12 is a waveform diagram illustrating an operation of the capacitive sensing circuit for the multi-touch panel of FIG. 11.
FIG. 13 is an equivalent circuit diagram schematically illustrating another example of the capacitive sensing circuit for the multi-touch panel of the mutual cap method shown in FIG. 1.
FIG. 14 is a waveform diagram illustrating an operation of the capacitive sensing circuit for the multi-touch panel of FIG. 13.
FIG. 15 is a circuit diagram for describing the reception circuit unit shown in FIGS. 11 and 13 as a whole.
FIG. 16 is a circuit diagram for describing a part of the reception circuit unit illustrated in FIG. 15.
FIG. 17 is a circuit diagram illustrating the microdischarge current source shown in FIG. 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to the accompanying drawings. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a schematic diagram illustrating a multi-touch sensing device according to an embodiment of the present invention.

Referring to FIG. 1, the multi-touch sensing device includes a multi-touch panel 100 and a capacitive sensing circuit 200.

The multi-touch panel 100 includes a plurality of transmission lines T0, T1, T2, T3, T4, T5, T6, and T7 extending in the X-axis direction and extending in the Y-axis direction, and extending in the Y-axis direction. And a plurality of receiving lines R0, R1, R2, R3, R4, R5, R6, and R7 arranged in the X-axis direction. The transmission lines and the reception lines may be formed on different layers or may be formed on the same layer. In this embodiment, the number of transmission lines and receiving lines is eight. In this embodiment, the transmission line serves to transmit a specific signal, for example, a square wave transmission signal, and the reception line serves to sense capacitance caused by a signal induced from the transmission line. .

The capacitive sensing circuit 200 includes a transmitting circuit unit 210 and a receiving circuit unit 220. The transmitting circuit unit 210 and the receiving circuit unit 220 may be formed on one chip or may be formed on different chips. Meanwhile, the transmitting circuit unit 210 and the receiving circuit unit 220 may be integrated on the multi-touch panel 100.

The transmission circuit unit 210 includes a transmitter 212 and a transmission switch 214, and transmits the transmission signal to the transmission line (T0, T1, T2, T3, T4) of the multi-touch panel 100. , T5, T6, T7) sequentially. In the present embodiment, the transmitter 212 outputs a square wave transmission signal to the transmission lines T0, T1, T2, T3, T4, T5, T6, and T7 of the multi-touch panel 100. The strength of the transmission signal output from the transmitter 212 may be weak. If the strength of the transmission signal is weak, difficulty in processing the signal in the reception circuit unit 220 may occur. Accordingly, the amount of energy induced in the reception line may be further increased by increasing the output voltage of the transmitter 212 to increase the transmission energy. In order to increase the voltage of the transmission signal, the transmission circuit unit 210 may further include a power booster (not shown) such as a charge pump.

The reception circuit unit 220 may determine a difference in capacitance generated between the transmission line and the reception line when a human body contact occurs, and receive lines R0, R1, R2, R3, and R4 of the multi-touch panel 100. , R5, R6, R7). In the present embodiment, the receiving circuit 220 includes a current mirror-based charge integrating circuit 224, the rising period and the falling period of the square wave transmission signal applied from the transmission circuit unit 210 Correspondingly, the charges are respectively integrated to detect a difference in capacitance generated between the transmission line and the reception line of the multi-touch panel 100 to detect whether or not the touch is performed. In the present exemplary embodiment, the receiving circuit unit 220 is provided with a receiving switch 222 to receive the receiving signal from the receiving lines R0, R1, R2, R3, R4, R5, R6, and R7. The receiving switch 222 may be omitted. In this case, a plurality of receiving circuit units are provided and connected to each of the receiving lines.

Since the change in the received signal (charge amount) detected by the human body is very small, such as several tens fF to several Pf, the charge integrator accumulates the charge amount by the received signal and amplifies and converts the accumulated charge into voltage. 224, a circuit is used for the receiving circuit unit 220. An analog-to-digital converter (ADC) 226 or the like is used to digitize the value of the detected voltage to enable data processing.

As described above, according to the multi-touch sensing device, the transmission lines 110 and the receiving lines 120 that are perpendicular to each other are formed with each other's capacitance by an insulating material overlapping each other in an insulated state. At the same time, energy of a certain level of the transmission line is induced to the reception line by the electric field generated from the transmission signal of the transmission line. At this time, when a touch is generated by the user, the transmission signal applied to the electrode lines corresponding to the points where the touch is generated and the reception signal induced in the reception lines are capacitances formed on the respective electrodes by the touch. A change in the capacitance and a change in the static / electrical energy field occur, resulting in a change in the amount of energy induced into the receiving line.

The capacitive sensing circuit according to the present invention converts the electrical energy detected from the receiving line, that is, the amount of charge (or the amount of change in capacitance) into a unit of voltage to take advantage of the difference between the voltage when a touch is generated and when it is not. The presence or absence of a user's touch is determined. The difference in the amount of charge due to the change in capacitance is measured by measuring the change amount of all the horizontal axes with respect to the independent vertical axis, and the measured values are processed in a two-dimensional arrangement of the vertical axis and the horizontal axis, so that multi-touch can be easily distinguished.

FIG. 2 is an equivalent circuit diagram schematically illustrating an example of the capacitive sensing circuit for the multi-touch panel of the mutual cap method shown in FIG. 1. FIG. 3 is a waveform diagram illustrating an operation of the capacitive sensing circuit for the multi-touch panel of FIG. 2.

2 and 3, the transmitting circuit unit 210 connected to the multi-touch panel 100 (shown in FIG. 1) may include a first switch SW0, a second switch SW1, and a first inverter IN1. And a second inverter IN2, and provides a square wave transmission signal TX to the multi-touch panel 100. For convenience of description, the transmitter 212 (shown in FIG. 1) provided in the transmitting circuit unit 210 and outputting a square wave transmission signal is referred to as a first switch SW0 and a second switch SW1. That is, when the first switch SW0 is turned on, a high level power supply voltage VDD is output. When the second switch SW1 is turned on, a ground voltage GND which is low level is output. Therefore, a square wave transmission signal having a high level and a low level can be output.

The receiving circuit unit 220 includes an upper switch SW11, a lower switch SW12, an upper current mirror unit UCM, a lower current mirror unit LCM, an output switching unit SW13, an output capacitor C1, and an enable circuit. And a switch SW14.

In every period of the transmission signal TX having a square wave shape, the transmission signal in response to the first and second transmission switch control signals S0 and S1 and the first and second integration control signals CP and CN. The operation of the capacitance sensing circuit at the rising edge of TX and the operation of the capacitance sensing circuit at the falling edge are different. In the present embodiment, the first transmission switch control signal SO and the first integration control signal CP are in phase with each other.

That is, at the rising edge of the transmission signal TX, a first current path along the first switch SW0, the multi-touch panel 100, the lower switch SW12, and the lower current mirror part LCM. Is formed, and the current flowing along the first current path is mirrored to the NMOSs disposed on the right side of the lower current mirror part LCM, so that the upper current mirror part UCM and the lower current mirror part LCM are disposed. As a result, a second current path is formed. The current flowing along the second current path is mirrored to the PMOSs disposed on the right side of the upper current mirror unit UCM, and thus a third current path along the upper current mirror unit UCM and the output switching unit SW13. Is formed. Charge corresponding to the current according to the third current path is charged in the output capacitor C1 and then output through the output terminal. Here, the reception signal RX is discharged through the lower current mirror part LCM and thus has a voltage level that decreases with time.

On the other hand, at the falling edge of the transmission signal TX, a first current path along the upper current mirror unit UCM, the upper switch SW11, the multi-touch panel 100, and the second switch SW1. Is formed. The current flowing through the left PMOSs of the upper current mirror unit UCM is mirrored to the right PMOSs of the upper current mirror UCM to form a second current path. Charge corresponding to the current according to the second current path is charged to the output capacitor C1 and then output through the output terminal. Here, the reception signal RX has a voltage level that increases with time because charge is continuously supplied from the upper current mirror unit UCM.

Therefore, since the charges received at each of the rising and falling edges of the transmission signal TX can be integrated, twice as much charge energy can be integrated as compared to a technique of integrating only the charges received at the rising edge.

On the other hand, if a touch occurs during the rising edge or falling edge of the transmission signal TX, the capacitance C0 formed in the multi-touch panel 100 is reduced. That is, since the waveform of the transmission signal TX and the waveform of the reception signal RX are inversed to each other, the capacitance of the capacitor generated by the human contact reduces the capacitance formed in the multi-touch panel 100. .

On the other hand, according to the present embodiment, by configuring the discharge path from the reception signal (RX) in response to the charging of the transmission signal (TX) or by charging together in the reception signal (RX) in response to the charging of the transmission signal (TX), The sensing speed of the capacitance can be increased by increasing or decreasing the amount of charges transferred to both ends of the capacitor C0 formed in the multi-touch panel 100 in a short time. That is, when one end charges through the other end of the capacitor connected to the ground electrode, the charge is charged quickly at the beginning of charging, but after a certain time elapses, the charging speed becomes slow. However, if one end and the other end of the capacitor are used as the charging terminal and the discharge terminal, respectively, and then one end and the other end of the capacitor are used as the charging terminal and the charging terminal, respectively, the speed at which the charge flows during the charging and discharging operations is increased. Therefore, according to this embodiment, it is possible to speed up the detection speed of the capacitance.

Further, according to the present invention, the circuit configuration can be simplified by configuring the charge integrating circuit integrating both the rising and falling periods of the transmission signal with the current mirror instead of the operational amplifier OP-AMP. In addition, by integrating in both the rising and falling periods of the transmission signal, it is possible to precisely maintain the voltage value in the change component of the output voltage after integration.

FIG. 4 is an equivalent circuit diagram schematically illustrating another example of the capacitive sensing circuit for the multi-touch panel of the mutual cap method shown in FIG. 1. FIG. 5 is a waveform diagram illustrating an operation of the capacitive sensing circuit for the multi-touch panel of FIG. 4.

4 and 5, the transmission circuit unit 210 connected to the multi-touch panel 100 includes a first switch SW0 and a second switch SW1, and transmits a square wave transmission signal TX. The multi-touch panel 100 is provided. For convenience of description, the transmitter 212 (shown in FIG. 1) provided in the transmitting circuit unit 210 and outputting a square wave transmission signal is referred to as a first switch SW0 and a second switch SW1. That is, when the first switch SW0 is turned on, a high level power supply voltage VDD is output. When the second switch SW1 is turned on, a ground voltage GND which is low level is output. Therefore, a square wave transmission signal having a high level and a low level can be output.

The receiving circuit unit 220 includes an upper switch SW11, a lower switch SW12, an upper current mirror unit UCM, a lower current mirror unit LCM, an output switching unit SW13, a discharge current source DIC, and an output capacitor. (C1) and enable switch SW14.

In every period of the transmission signal TX having a square wave shape, the transmission signal in response to the first and second transmission switch control signals S0 and S1 and the first and second integration control signals CP and CN. The operation of the capacitance sensing circuit at the rising edge of TX and the operation of the capacitance sensing circuit at the falling edge are different.

That is, at the rising edge of the transmission signal TX, a first current path is formed along the first switch SW0 and the multi-touch panel 100, and the upper current mirror unit UCM and the upper switch are formed. A second current path is formed along SW11. In this case, the first integration control signal CP for turning on the upper switch SW11 is also supplied to the enable switch SW14 to turn on the enable switch SW14 to mirror the lower current mirror part LCM. The operation is blocked. A current flowing through the plurality of PMOSs disposed on the left side of the upper current mirror unit UCM is mirrored to the PMOSs disposed on the right side of the upper current mirror UCM to form a third current path. Charge corresponding to the current according to the third current path is charged in the output capacitor C1 and then output through the output terminal. In this case, since the charge is supplied to the multi-touch panel 100 through the first switch SW0, the reception signal RX has a voltage level that increases with time.

On the other hand, at the falling edge of the transmission signal TX, a first current path is formed through the second switch SW1, and a current flowing along the multi-touch panel 100 and the lower switch SW12 is A third current path is formed along the upper current mirror unit UCM and the lower current mirror unit LCM by mirroring the NMOSs disposed on the right side of the lower current mirror unit LCM. Current flowing through the left PMOSs of the upper current mirror unit UCM is mirrored to the right PMOSs of the upper current mirror UCM to form a fourth current path. Charge corresponding to the current according to the fourth current path is charged in the output capacitor C1 and then output through the output terminal via the output switching unit SW13. Here, the reception signal RX is discharged through the lower current mirror part LCM and thus has a voltage level that decreases with time.

FIG. 6 is a circuit diagram for describing the reception circuit unit shown in FIGS. 2 and 4 as a whole.

4 and 6, the receiving circuit unit according to an embodiment of the present invention, the upper switch (SW11), the lower switch (SW12), the upper current mirror unit (UCM), the lower current mirror unit (LCM), output switching A unit SW13, an enable switch SW14, an output capacitor C1, a discharge current source DIC, and a switching signal output unit SCP.

The upper switch SW11 is turned on or off in response to a first integration control signal CP to receive the received signal RX received through an input terminal connected to a receiving line, the upper current mirror unit UCM and the lower current. It is provided to the mirror part LCM.

The lower switch SW12 is turned on or off in response to a second integration control signal CN to provide the received current signal RX received through an input terminal connected to the receiving line to the lower current mirror unit LCM. . The configuration of the upper switch SW11 and the lower switch SW12 will be described in detail later with reference to FIG. 10.

The upper current mirror unit UCM includes a plurality of transistors arranged in two stages in a current mirror relationship. The lower current mirror portion LCM includes a plurality of transistors arranged in two stages in a current mirror relationship. When the voltage induced by the touch is provided with the reception signal RX through the reception line, the upper current mirror unit UCM and the lower current mirror unit LCM may receive the rising edge time of the reception signal RX. The corresponding charge of the received signal RX is integrated at the falling edge time and output through the output terminal. The configuration of the upper current mirror unit UCM and the lower current mirror unit LCM will be described in detail later with reference to FIG. 7.

The output switching unit SW13 is composed of a plurality of switches and is disposed at each end of the upper current mirror unit UCM to output a signal integrated through an output terminal. The configuration of the output switching unit SW13 will be described in detail later with reference to FIGS. 7 and 8.

The enable switch SW14 is disposed at the end of the lower current mirror part LCM, and the upper current mirror part UCM and the multi-touch panel 100 are turned on according to the on of the upper switch SW11. 2) and when the current path is set through the second switch SW1 (shown in FIG. 2) of the transmitting circuit unit, it serves to block the operation of the lower current mirror unit LCM. In the present exemplary embodiment, the enable switch SW14 is illustrated at the end of the lower current mirror part LCM, but is not limited thereto. For example, the enable switch SW14 may be disposed between the upper current mirror unit UCM and the lower current mirror unit LCM, and the lower switch SW12 and the lower current mirror unit LCM. It may be placed in the liver.

The output capacitor C1 has one end connected to the output terminal and the other end connected to the ground voltage terminal supplied with the ground voltage GND, thereby charging a charge corresponding to the current mirrored by the upper current mirror unit UCM. do.

The discharge current source DIC is disposed at the end of the output switching unit SW13 to discharge the charge charged in the output capacitor C1. The configuration of the discharge current source DIC will be described in detail later with reference to FIG. 9.

The switching signal output unit SCP is composed of two inverters connected in series to provide a signal for controlling on or off of the output switching unit SW13 to the output switching unit SW13.

FIG. 7 is a circuit diagram for describing a part of the reception circuit unit illustrated in FIG. 6.

Referring to FIG. 7, the receiving circuit unit according to the exemplary embodiment of the present invention includes an upper switch SW11, a lower switch SW12, an upper current mirror unit UCM, a lower current mirror unit LCM, and an output switching unit SW13. ), The enable switch (SW14) and the micro-discharge current source (DIC).

The upper switch SW11 has a first end connected to a receiving line of the multi-touch panel 100 (shown in FIG. 1), a second end connected to the upper current mirror unit UCM, and a control end. It is turned on in response to the first integration control signal CP.

The lower switch SW12 has a first end connected to a receiving line of the multi-touch panel 100 (shown in FIG. 1), a second end connected to the lower current mirror part LCM, and a control end. It is turned on in response to the second integration control signal CN inputted through the second integration control signal CN. The second integration control signal CN and the first integration control signal CP are opposite to each other. That is, when the second integration control signal CN is at a high level, the first integration control signal CP is at a low level, and when the second integration control signal CN is at a low level, the first integration is performed. The control signal CP is at a high level.

The upper current mirror unit UCM includes an upper master UM and an upper slave US, and a current flowing through the upper master UM is mirrored to the upper slave US to the output switching unit SW13. Is provided.

The upper master includes a first PMOS QP11, a second PMOS QP12, a third PMOS QP13, and a fourth PMOS QP14. In detail, the source of the first PMOS QP11 is connected to the power supply voltage terminal to which the power supply voltage VDD is supplied, and the gate is connected to the drain of the second PMOS QP12. The source of the second PMOS QP12 is connected to the drain of the first PMOS QP11, and the gate is connected to the drain of the third PMOS QP13. A gate of the third PMOS QP13 is connected to the upper switch SW11, a source is connected to the drain of the second PMOS QP12, and a drain is connected to the source of the fourth PMOS QP14. The gate and the drain of the fourth PMOS QP14 are commonly connected and connected to the upper switch SW11, and the source is connected to the drain of the third PMOS QP13.

The upper slave US includes an upper PMOS unit MQP1 including a plurality of PMOSs having common gates connected thereto, and a lower PMOS unit MQP2 including a plurality of PMOSs common gates connected to each other.

The lower current mirror part LCM includes a lower master LM and a lower slave LS, and a current flowing through the lower master LM is mirrored to the lower slave LS.

The lower master LM includes a first NMOS QN11, a second NMOS QN12, a third NMOS QN13, and a fourth NMOS QN14. In detail, the gate and the drain of the first NMOS QN11 are commonly connected to the lower switch SW12. A drain of the second NMOS QN12 is connected to the source of the first NMOS QN11, and a gate is connected to the gate and drain of the first NMOS QN11 and the lower switch. The drain of the third NMOS QN13 is connected to the source of the second NMOS QN12, and the gate is connected to the drain of the second NMOS QN12. The drain of the fourth NMOS QN14 is connected to the source of the third NMOS QN13, the gate is connected to the drain of the third NMOS QN13, and the source is connected to the ground voltage GND.

The lower slave LS includes a fifth NMOS QN15 and a sixth NMOS QN16. Specifically, the drain of the fifth NMOS QN15 is connected to the drain and gate of the fourth PMOS QP14 provided in the upper master, the gate of the third PMOS QP13, and the upper switch SW11, and the gate is formed of the fifth NMOS QN15. 3 is connected to the gate of NMOS QN13. The drain of the sixth NMOS QN16 is connected to the source of the fifth NMOS QN15, the gate is connected to the gate of the fourth NMOS QN14, and the source is connected to the ground voltage GND.

The first stage of the output switching unit SW13 is connected to the drain of the lower PMOS unit MQP2, and the second stage of the output switching unit SW13 is connected to an analog-to-digital converter (ADC) (not shown). The charge integral value is output to the ADC in response to the signal SC.

One end of the enable switch SW14 is commonly connected to the gate of the fourth NMOS QN14 and the gate of the sixth NMOS QN16 that are commonly connected to each other, thereby switching the first switch SW11. On). That is, when the first integration control signal CP is provided to the upper switch SW11 and the upper switch SW11 is turned on, the enable switch SW14 is also turned on. Accordingly, while the voltage of the receiving line is applied to the upper current mirror unit UCM through the upper switch SW11, the lower current mirror unit LCM stops the operation.

The microdischarge current source DIC is connected to the output terminal to perform a function of finely discharging the integrated voltage Vint of the output terminal. Accordingly, the range in which the integrated voltage can be detected can be widened.

FIG. 8 is a circuit diagram for describing the upper PMOS unit MQP1, the lower PMOS unit MQP2, and the output switching unit SW13 in FIG. 7.

Referring to FIGS. 7 and 8, the upper PMOS unit MQP1 includes a plurality of PMOSs Q11, Q12, Q13, Q14, Q15, Q16, Q17, and Q18 having a common gate connected thereto, and the PMOSs Q11, The source of each of Q12, Q13, Q14, Q15, Q16, Q17, and Q18) is connected to a power supply voltage terminal to which a power supply voltage VDD is applied, and a common connected gate is connected to the first PMOS QP11 of the upper master UM. Connected to the gate.

The lower PMOS unit MQP2 includes a plurality of PMOSs Q21, Q22, Q23, Q24, Q25, Q26, Q27, and Q28 having a common gate connected thereto, and PMOSs Q21, Q22, Q23, Q24, Q25, and Q26. , Q27, Q28 each source is connected to each of the drains of the PMOS (Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18) provided in the upper PMOS unit (MQP1), the common gate is It is connected to the gate of the second PMOS QP12.

The output switching unit SW13 includes a first charge output switch US1, a second charge output switch US2, a third charge output switch US3, a fourth charge output switch US4, and a fifth charge output switch US5. ), A sixth charge output switch US6, a seventh charge output switch US7, and an eighth charge output switch US8. Each of the first to eighth charge output switches US1, US2, US3, US4, US5, US6, US7, US8 is selectively turned on in response to the switching control signal SC to be output from the lower PMOS unit MQP2. Output the charge to the output terminal.

The switching control signal SC includes a first switching signal s <0>, a second switching signal s <1>, a third switching signal s <2>, and a fourth switching signal s <3>. ), A fifth switching signal s <4>, a sixth switching signal s <5>, a seventh switching signal s <6>, and an eighth switching signal s <7>. The first to eighth switching signals s <0>, s <1>, s <2>, s <3>, s <4>, s <5>, s <6>, and s <7> ) May be provided to each of the first to eighth charge output switches US1, US2, US3, US4, US5, US6, US7, US8 having a high level. Accordingly, at least one of the first to eighth charge output switches US1, US2, US3, US4, US5, US6, US7, US8 may be turned on.

For example, the second to eighth switching signals s <1>, s <2>, s <3>, s <4>, s <5>, s <6>, and s <7> are low. Level and the first switching signal s <0> has a high level, only the first charge output switch US1 is turned on to mirror the mirrored current flowing through the PMOS Q11 and the PMOS Q21. Output to the output terminal. At this time, if the PMOS Q11 and the PMOS Q21 are designed to mirror 0.125 times the reference current, the current output through the output stage is 0.125 times the reference current.

Meanwhile, the first to sixth switching signals s <0>, s <1>, s <2>, s <3>, s <4>, and s <5> have low levels, and the seventh and sixth switching signals. If the eight switching signals s <6> and s <7> have a high level, the seventh and eighth charge output switches US7 and US8 are turned on and flow through the PMOS Q17 and the PMOS Q27. The mirrored current and the mirrored current flowing through the PMOS Q18 and PMOS Q28 are output to the output terminal. At this time, if the PMOS Q17 and the PMOS Q27 are designed to be 8 times mirrored with respect to the reference current, and the PMOS Q18 and PMOS Q28 are designed to be 16 times mirrored with respect to the reference current, the current output through the output stage is 24 times the reference current.

FIG. 9 is a circuit diagram illustrating the microdischarge current source DIC shown in FIG. 7.

Referring to FIG. 9, the microdischarge current source DIC includes a main discharge current mirror unit MDC, a main discharge switching unit MDS, and a sub-discharge current mirror unit SDC.

The main discharge current mirror unit (MDC) includes a PMOS (DQ11) performing a master mirror function, a PMOS (DQ12), a PMOS (DQ13), a PMOS (DQ14), and a PMOS (DQ15) performing a slave function of the current mirror. , PMOS DQ16, PMOS DQ17 and PMOS DQ18.

The source of the PMOS DQ11 is connected to the power supply voltage terminal to which the power supply voltage VDD is supplied, and the common gate and drain are connected to the gate and the main discharge switching unit MDS of the PMOS DQ12.

The sources of PMOS (DQ12), PMOS (DQ13), PMOS (DQ14), PMOS (DQ15), PMOS (DQ16), PMOS (DQ17), and PMOS (DQ18), respectively, are connected to the supply voltage terminal to which the supply voltage (VDD) is supplied. Each gate is connected to a common gate and a drain of the PMOS DQ11, and each drain is connected to the main discharge switching unit MDS.

The main discharge switching unit MDS includes a first discharge switch DS1, a second discharge switch DS2, a third discharge switch DS3, a fourth discharge switch DS4, a fifth discharge switch DS5, and a fifth discharge switch DS1. And a sixth discharge switch DS6, a seventh discharge switch DS7, and an eighth discharge switch DS8.

The first terminal of the first discharge switch DS1 is connected to the drain of the PMOS DQ11 to be turned on in response to the switch enable signal SSEN provided through the control terminal to bias the PMOS DQ11. Accordingly, the second stage of the first discharge switch DS1 outputs the biasing current to the outside.

A first end of the second discharge switch DS2 is connected to the drain of the PMOS DQ12, and a second end of the second discharge switch DS2 is connected to the sub-discharge current mirror unit SDC. When the first switching signal SS <0> is provided through the control terminal of the second discharge switch DS2, the second discharge switch DS2 is turned on and the mirrored current output through the drain of the PMOS DQ12. Is provided to the sub-discharge current mirror unit (SDC) through a second stage.

A first end of the third discharge switch DS3 is connected to the drain of the PMOS DQ13, and a second end of the third discharge switch DS3 is connected to the sub-discharge current mirror unit SDC. When the second switching signal SS <1> is provided through the control terminal of the third discharge switch DS3, the third discharge switch DS3 is turned on and the mirrored current output through the drain of the PMOS DQ13. Is provided to the sub-discharge current mirror unit (SDC) through a second stage.

A first end of the fourth discharge switch DS4 is connected to the drain of the PMOS DQ14, and a second end of the fourth discharge switch DS4 is connected to the sub-discharge current mirror unit SDC. When the third switching signal SS <2> is provided through the control terminal of the fourth discharge switch DS4, the fourth discharge switch DS5 is turned on and the mirrored current output through the drain of the PMOS DQ14. Is provided to the sub-discharge current mirror unit (SDC) through a second stage.

A first end of the fifth discharge switch DS5 is connected to the drain of the PMOS DQ15, and a second end of the fifth discharge switch DS5 is connected to the sub-discharge current mirror unit SDC. When the fourth switching signal SS <3> is provided through the control terminal of the fifth discharge switch DS5, the fifth discharge switch DS5 is turned on and the mirrored current output through the drain of the PMOS DQ15. Is provided to the sub-discharge current mirror unit (SDC) through a second stage.

A first end of the sixth discharge switch DS6 is connected to the drain of the PMOS DQ16, and a second end of the sixth discharge switch DS6 is connected to the sub-discharge current mirror unit SDC. When the fifth switching signal SS <4> is provided through the control terminal of the sixth discharge switch DS6, the sixth discharge switch DS6 is turned on and the mirrored current output through the drain of the PMOS DQ16. Is provided to the sub-discharge current mirror unit (SDC) through a second stage.

A first end of the seventh discharge switch DS7 is connected to the drain of the PMOS DQ17, and a second end of the seventh discharge switch DS7 is connected to the sub-discharge current mirror unit SDC. When the sixth switching signal SS <5> is provided through the control terminal of the seventh discharge switch DS7, the seventh discharge switch DS7 is turned on and the mirrored current output through the drain of the PMOS DQ17. Is provided to the sub-discharge current mirror unit (SDC) through a second stage.

A first end of the eighth discharge switch DS8 is connected to the drain of the PMOS DQ18, and a second end of the eighth discharge switch DS8 is connected to the sub-discharge current mirror unit SDC. When the seventh switching signal SS <6> is provided through the control terminal of the eighth discharge switch DS8, the eighth discharge switch DS8 is turned on and the mirrored current output through the drain of the PMOS DQ18. Is provided to the sub-discharge current mirror unit (SDC) through a second stage.

The sub-discharge current mirror unit SDC includes an NMOS DC1 performing a master function and an NMOS DC2 performing a slave function.

The NMOS DC1 has a drain and a gate commonly connected to each other, and is connected to a second terminal of each of the second to eighth discharge switches DS2, DS3, DS4, DS5, DS6, DS7, and DS8. GND) is connected to the supplied ground voltage terminal. The gate of the NMOS DC2 is connected to the drain and gate of the NMOS DC1, the source is connected to the ground voltage terminal, and the drain is connected to the output switching unit SW13 and the output terminal.

As the current is output through the second to eighth discharge switches DS2, DS3, DS4, DS5, DS6, DS7, and DS8, the NMOS DC1 is biased so that a bias current flows. Accordingly, the NMOS DC2 outputs a mirrored current corresponding to the bias current.

In operation, when the first discharge switch DS1 is turned on and the PMOS DQ12 is biased, a reference current flows through the PMOS DQ12.

As the reference current is generated, the mirroring current flows through the PMOS (DQ12), PMOS (DQ13), PMOS (DQ14), PMOS (DQ15), PMOS (DQ16), PMOS (DQ17) and PMOS (DQ18) gates connected in parallel. Each mirroring current generated is provided to the second to eighth discharge switches DS2, DS3, DS4, DS5, DS6, DS7, and DS8.

Each of the second to eighth discharge switches DS2, DS3, DS4, DS5, DS6, DS7, and DS8 is turned on in response to a switching signal to provide mirroring currents to the sub-discharge current mirror unit SDC. As the sub-discharge current mirror unit SDC provides the current mirrored by the main discharge current mirror unit MDC through the NMOS DC1 performing a master function, the NMOS DC2 is applied to the integral voltage Vint. Correspondingly, the micro-discharge operation is performed by mirroring the current output through the output terminal. As a result, the integral voltage Vint is finely down.

In general, the gain of the transistor may be determined by the channel width versus the channel length (W / L). In view of this, in this embodiment, it is assumed that the channel width W of the PMOS DQ11 is 1, and the PMOS DQ12, PMOS DQ13, and PMOS DQ14 which are in a current mirror relationship with the PMOS DQ11 are assumed. ), The channel widths of the PMOS DQ15, the PMOS DQ16, the PMOS DQ17, and the PMOS DQ18 may be set to 0.125, 0.25, 0.5, 1.0, 2.0, 4.0, 8.0, and 16.0. Accordingly, when the first to eighth discharge switches DS1, DS2, DS3, DS4, DS5, DS6, DS7, and DS8 are connected to the drains of the respective PMOSs, 0.125 to a reference current flowing through the PMOS DQ11 is controlled. Integral currents amplified up to 31.875 times from integrated currents reduced from the reference current, such as 0.25, 0.5, 1.0, 2.0, 4.0, 8.0, 16.0, can be output through the output terminals in 0.125x units.

10 is a circuit diagram illustrating a switch provided in the receiving circuit unit according to the present invention.

Referring to FIG. 10, the switch includes a first switching inverter SI1, a second switching inverter SI2, a PMOS SP1, and an NMOS SN1. The switch may be used as the upper switch SW11 or may be used as the lower switch SW12. In addition, the switch may be provided in the output switching unit SW13 or may be provided in the enable switch SW14.

The first switching inverter SI1 inverts the switching control signal provided from the outside and supplies the inverted control signal to the gate of the PMOS SP1 and the second switching inverter SI2. The second switching inverter SI2 inverts the inverted switching control signal provided from the first switching inverter SI1 and provides the inverted switching control signal to the gate of the NMOS SN1.

The PMOS SP1 has a source connected to an input terminal, a drain connected to an output terminal, and turned on or off in response to an inverted switching control signal provided through a gate. For example, if the switch is used as the upper switch SW11, the source of the PMOS SP1 is connected to the terminal IN to which the reception signal RX is applied, and the drain is connected to the upper current mirror unit UCM. The gate receives a first integration control signal CP.

The NMOS SN1 has a drain connected to the input terminal, a source connected to the output terminal, and turned on or off in response to a switching control signal provided through a gate. For example, if the switch is used as the upper switch SW11, the drain of the NMOS SN1 is connected to the terminal IN to which the reception signal RX is applied, and the source is connected to the upper current mirror unit UCM. The gate receives a first integration control signal CP.

FIG. 11 is an equivalent circuit diagram schematically illustrating another example of the capacitive sensing circuit for the multi-touch panel of the mutual cap method shown in FIG. 1. FIG. 12 is a waveform diagram illustrating an operation of the capacitive sensing circuit for the multi-touch panel of FIG. 11.

11 and 12, the transmitting circuit unit 210 connected to the multi-touch panel 100 (shown in FIG. 1) may include a first switch SW0, a second switch SW1, and a first inverter IN1. And a second inverter IN2, and provides a square wave transmission signal TX to the multi-touch panel 100 (shown in FIG. 1). For convenience of description, a transmitter 212 (shown in FIG. 1) provided in the transmitting circuit unit 210 and outputting a square wave transmission signal is denoted by a first switch SW0 and a second switch SW1. That is, when the first switch SW0 is turned on, a high level power supply voltage VDD is output. When the second switch SW1 is turned on, a ground voltage GND which is low level is output. Therefore, a square wave transmission signal having a high level and a low level can be output.

The receiving circuit unit 220 includes an upper switch SW11, a lower switch SW12, an upper current mirror unit UCM, a lower current mirror unit LCM, an output switching unit SW13, an output capacitor C1, and an enable switch. (SW14) is included.

In every period of the transmission signal TX having a square wave shape, the transmission signal in response to the first and second transmission switch control signals S0 and S1 and the first and second integration control signals CP and CN. The operation of the capacitance sensing circuit at the rising edge of TX and the operation of the capacitance sensing circuit at the falling edge are different. In the present embodiment, the first transmission switch control signal S0 and the first integration control signal CP are opposite to each other.

That is, at the rising edge of the transmission signal TX, the first switch SW0, the multi-touch panel 100 (shown in FIG. 1), the lower switch SW12 and the lower current mirror part LCM are arranged along the first edge. A current path is formed, and the current flowing along the first current path is mirrored to the NMOSs disposed on the right side of the lower current mirror part LCM, and thus, along the upper current mirror part UCM and the lower current mirror part LCM. A second current path is formed. The current flowing along the second current path is mirrored to the PMOSs disposed on the right side of the upper current mirror unit UCM to form a third current path along the upper current mirror unit UCM and the output switching unit SW13. The current according to the third current path is output through the output terminal. Here, since the reception signal RX is discharged through the lower current mirror part LCM, the reception signal RX has a voltage level that decreases with time.

Meanwhile, at the falling edge of the transmission signal TX, the first current mirror unit UCM, the upper switch SW11, the multi-touch panel 100 (shown in FIG. 1), and the first switch along the second switch SW1 may be used. A current path is formed. The current flowing through the left PMOSs of the upper current mirror unit UCM is mirrored to the right PMOSs of the upper current mirror UCM to form a second current path. The current according to the second current path is output through the output terminal. Here, the reception signal RX has a voltage level that increases with time because charge is continuously supplied from the upper current mirror unit UCM.

Therefore, since the charges received at the rising and falling edges of the transmission signal TX can be integrated, the charge energy can be integrated twice as much as the technology for integrating only the charges received at the rising edge.

On the other hand, when a touch is generated during the rising edge section or the falling edge section of the transmission signal TX, the capacitance C0 formed in the multi-touch panel 100 (shown in FIG. 1) decreases. Because the TX waveform and the RX waveform are inverse to each other, the capacitance of the capacitor generated by the contact of the human body reduces the capacitance formed in the multi-touch panel 100 (shown in FIG. 1).

FIG. 13 is an equivalent circuit diagram schematically illustrating another example of the capacitive sensing circuit for the multi-touch panel of the mutual cap method shown in FIG. 1. FIG. 14 is a waveform diagram illustrating an operation of the capacitive sensing circuit for the multi-touch panel of FIG. 13.

Referring to FIGS. 13 and 14, the transmitting circuit unit 210 connected to the multi-touch panel 100 (shown in FIG. 1) includes a first switch SW0 and a second switch SW1, and includes a square wave. The transmission signal TX is provided to the multi-touch panel 100 (shown in FIG. 1). For convenience of description, a transmitter 212 (shown in FIG. 1) provided in the transmitting circuit unit 210 and outputting a square wave transmission signal is denoted by a first switch SW0 and a second switch SW1. That is, when the first switch SW0 is turned on, a high level power supply voltage VDD is output. When the second switch SW1 is turned on, a ground voltage GND which is low level is output. Therefore, a square wave transmission signal having a high level and a low level can be output.

The receiving circuit unit 220 includes an upper switch SW11, a lower switch SW12, an upper current mirror unit UCM, a lower current mirror unit LCM, an output switching unit SW13, an output capacitor C1, and an enable switch. (SW14) is included.

In every period of the transmission signal TX having a square wave shape, the transmission signal in response to the first and second transmission switch control signals S0 and S1 and the first and second integration control signals CP and CN. The operation of the capacitance sensing circuit at the rising edge of TX and the operation of the capacitance sensing circuit at the falling edge are different. In the present embodiment, the first transmission switch control signal SO and the first integration control signal CP are in phase with each other.

That is, at the rising edge of the transmission signal TX, a first current path is formed along the first switch SW0 and the multi-touch panel 100 (shown in FIG. 1), and the upper current mirror unit UCM, A second current path is formed along the top switch SW11 and the multi-touch panel 100 (shown in FIG. 1). It is mirrored to the PMOSs disposed on the right side of the upper current mirror unit UCM flowing along the second current path. The current mirrored in the PMOSs disposed on the right side of the upper current mirror unit UCM is output through the output terminal via the output switching unit SW13. Here, the reception signal RX has a voltage level that increases with time because charge is continuously supplied through the upper current mirror unit UCM.

On the other hand, at the falling edge of the transmission signal TX, a first current path is formed along the second switch SW1, and the multi-touch panel 100 (shown in FIG. 1), the lower switch SW12, and the lower current. A second current path is formed along the mirror portion LCM. Since the current flowing along the second current path is mirrored to the PMOSs disposed on the right side of the lower current mirror part LCM, the current flowing along the upper current mirror part UCM, the upper switch SW11, and the lower current mirror part LCM is generated. 3 Current paths are formed. The current flowing along the third current path is mirrored to the PMOSs disposed on the right side of the upper current mirror unit UCM to form a fourth current path. The current according to the fourth current path is output through the output terminal. Here, since the charge is discharged by the lower current mirror portion LCM, the reception signal RX has a voltage level that increases with time.

Therefore, since the charges received at the rising and falling edges of the transmission signal TX can be integrated, the charge energy can be integrated twice as much as the technology for integrating only the charges received at the rising edge.

On the other hand, when a touch occurs during the rising edge section or the falling edge section of the transmission signal TX, the capacitance C0 formed in the multi-touch panel 100 (shown in FIG. 1) increases. Because the TX waveform and the RX waveform are the same, the capacitance of the capacitor generated by the contact of the human body is substantially added to the capacitance formed in the multi-touch panel 100 (shown in FIG. Increase the capacitance formed in FIG.

FIG. 15 is a circuit diagram for describing the reception circuit unit shown in FIGS. 11 and 13 as a whole.

Referring to FIG. 15, the receiving circuit unit according to another embodiment of the present invention includes an upper switch SW11, a lower switch SW12, an upper current mirror unit UCM, a lower current mirror unit LCM, and an output switching unit SW13. ), An output capacitor C1, an enable switch SW14, a discharge current source DIC, and a switching signal output unit SCP.

The upper switch SW11 is turned on or off in response to a first integration control signal CP to receive the received signal RX received through an input terminal connected to a receiving line, the upper current mirror unit UCM and the lower current. It is provided to the mirror part LCM.

The lower switch SW12 is turned on or off in response to a second integration control signal CN to provide the received current signal RX received through an input terminal connected to the receiving line to the lower current mirror unit LCM. . The configuration of the upper switch SW11 and the lower switch SW12 has been described with reference to FIG. 6, and thus description thereof will be omitted.

The upper current mirror unit UCM includes a plurality of transistors arranged in two stages in a current mirror relationship. The lower current mirror portion LCM includes a plurality of transistors arranged in two stages in a current mirror relationship. When the voltage induced by the touch is provided with the reception signal RX through the reception line, the upper current mirror unit UCM and the lower current mirror unit LCM may receive the rising edge time of the reception signal RX. The corresponding charge of the received signal RX is integrated at the falling edge time and output through the output terminal. The configuration of the upper current mirror unit UCM and the lower current mirror unit LCM will be described in detail later with reference to FIG. 16.

The output switching unit SW13 is composed of a plurality of switches and is disposed at each end of the upper current mirror unit UCM to output a signal integrated through an output terminal. Since the configuration of the output switching unit SW13 has been described with reference to FIG. 6, the description thereof will be omitted.

The enable switch SW14 is disposed at the end of the upper current mirror unit UCM, and the upper current mirror unit UCM and the multi-touch panel 100 are turned on when the upper switch SW11 is turned on. 2) and when the current path is set through the second switch SW1 (shown in FIG. 2) of the transmitting circuit unit, it serves to block the operation of the lower current mirror unit LCM. In the present exemplary embodiment, the enable switch SW14 is illustrated at the end of the lower current mirror part LCM, but is not limited thereto. For example, the enable switch SW14 may be disposed between the upper current mirror unit UCM and the lower current mirror unit LCM, and the lower switch SW12 and the lower current mirror unit LCM. It may be placed in the liver.

The output capacitor C1 has one end connected to the output terminal and the other end connected to the ground voltage terminal supplied with the ground voltage GND, thereby charging a charge corresponding to the current mirrored by the upper current mirror unit UCM. do.

The discharge current source DIC is disposed at the end of the output switching unit SW13 to discharge the charge charged in the output capacitor C1. The configuration of the discharge current source (DIC) will be described in detail later with reference to FIG. 17.

Although not shown, a switching signal output unit SCP as shown in FIG. 4 is provided to provide a signal for controlling the on or off of the output switching unit SW13 to the output switching unit SW13.

FIG. 16 is a circuit diagram for describing a part of the reception circuit unit illustrated in FIG. 15.

Referring to FIG. 16, the receiving circuit unit according to the exemplary embodiment of the present invention includes an upper switch SW11, a lower switch SW12, an upper current mirror unit UCM, a lower current mirror unit LCM, and an output switching unit SW13. ), An output capacitor C1, and an enable switch SW14.

The upper switch SW11 has a first end connected to a receiving line of the multi-touch panel 100 (shown in FIG. 1), a second end connected to the upper current mirror unit UCM, and a control end. It is turned on in response to the first integration control signal CP.

The lower switch SW12 has a first end connected to a receiving line of the multi-touch panel 100 (shown in FIG. 1), a second end connected to the lower current mirror part LCM, and a control end. It is turned on in response to the second integration control signal CN that is input through the controller.

The upper current mirror unit UCM includes an upper master UM and an upper slave US, and current flowing through the upper master UM is mirrored to the upper slave US and provided to the output switching unit SW13. do.

The upper master includes a first PMOS QP21, a second PMOS QP22, a third PMOS QP23, and a first NMOS QN21. In detail, the source of the first PMOS QP21 is connected to the power supply voltage terminal to which the power supply voltage VDD is supplied, and the gate is connected to the drain of the second PMOS QP22. The source of the second PMOS QP22 is connected to the drain of the first PMOS QP21, the gate is connected to the drain of the third PMOS QP23, and the drain is connected to the upper switch SW11. The source of the third PMOS QP23 is connected to the power supply voltage terminal, the gate is connected to the drain of the first PMOS QP21 and the source of the second PMOS QP22, and the drain is connected to the gate of the second PMOS QP12. Connected. The source of the first NMOS QN21 is connected to the drain of the third PMOS QP23 and the gate of the second PMOS QP22, the gate is connected to the gate of the third PMOS QP23, and the drain is connected to the ground voltage. Connected.

The upper slave US includes an upper PMOS unit MQP1, a lower PMOS unit MQP2, a fourth PMOS QP24, and a second NMOS QN22. In detail, the upper PMOS unit MQP1 includes a plurality of PMOSs in which gates are commonly connected to each other, a source of each of the PMOSs is connected to a power supply voltage terminal, and a gate connected in common to the first PMOS (UM) of the upper master UM. It is connected to the gate of the QP21 and the top switch SW11. The lower PMOS unit MQP2 includes a plurality of PMOSs in which gates are commonly connected. The source of each of the PMOSs is connected to each of the drains of the upper PMOS part MQP1 and the gate of the fourth PMOS QP24, and the common connected gate is the drain of the fourth PMOS QP24 and the second NMOS QN22. Is connected to the drain. The source of the fourth PMOS QP24 is connected to the power supply voltage terminal, and the gate is connected to the drains of the PMOSs provided in the upper PMOS unit MQP1. The drain of the second NMOS QN22 is connected to the drain of the fourth PMOS QP24, the gate is connected to the gate of the fourth PMOS QP24, and the source is connected to the ground voltage.

The lower current mirror part LCM includes a lower master LM and a lower slave LS, and a current flowing through the lower master LM is mirrored to the lower slave LS.

The lower master LM includes a third NMOS QN23, a fourth NMOS QN24, a fifth NMOS QN25, and a sixth PMOS QP26. Specifically, the drain of the third NMOS QN23 is connected to the lower switch SW12, the gate is connected to the drain of the sixth PMOS QP26, and the source is the drain of the fourth NMOS QN24, and the sixth PMOS ( A drain of QP26 and a drain of fifth NMOS QN25. The drain of the fourth NMOS QN24 is connected to the source of the third NMOS QN23 and the gate of the fifth NMOS QN25, and the gate is connected to the lower switch SW12. The drain of the fifth NMOS QN25 is connected to the gate of the third NMOS QN23 and the drain of the sixth PMOS QP26, and the gate is connected to the source of the third NMOS QN23 and the gate of the sixth PMOS QP26. The source is connected to ground voltage. The drain of the sixth PMOS QP26 is connected to a power supply voltage terminal, and the gate is connected to the gate of the fifth NMOS QN25, the source of the third NMOS QN23, and the drain of the fourth NMOS QN24. It is connected to the drain of the fifth NMOS QN25. The drain of the third NMOS QN23 is connected to the gate of the third NMOS QN23 and the drain of the sixth PMOS QP26, and the gate is connected to the source of the third NMOS QN23 and the drain of the fourth NMOS QN24. The source is connected to ground voltage.

The lower slave LS includes a seventh NMOS QN27, an eighth NMOS QN28, a sixth NMOS QN26, and a seventh PMOS QP27.

The drain of the seventh NMOS QN27 is connected to the upper switch SW11, the drain of the second PMOS QP22 and the gate of the first PMOS QP21, and the gate is connected to the drain of the sixth NMOS QN26. The source is connected to the gate of the sixth NMOS QN26, the gate of the seventh PMOS QP27, and the drain of the eighth NMOS QN28.

The drain of the eighth NMOS QN28 is connected to the source of the seventh NMOS QN27, the gate of the sixth NMOS QN26, and the gate of the seventh PMOS QP27, and the gate is connected to the gate of the fourth NMOS QN24. It is connected to the lower switch SW12, and the source is connected to the ground voltage.

The source of the seventh PMOS QP27 is connected to the power supply voltage terminal, the gate is connected to the source of the seventh NMOS QN27, the gate of the sixth NMOS QN26, and the drain is the drain of the sixth PMOS QN26 and Is connected to the gate of the seventh NMOS QN27.

The drain of the sixth NMOS QN26 is connected to the drain of the seventh PMOS QP27 and the gate of the seventh NMOS QN27, and the gate is the gate of the seventh PMOS QP27, the source of the seventh NMOS QN27, and It is connected to the drain of the eighth NMOS QN28, the source is connected to the ground voltage terminal.

The first stage of the output switching unit SW13 is connected to the drain of the lower PMOS unit MQP2, and the second stage of the output switching unit SW13 is connected to an analog-to-digital converter (ADC) (not shown). The charge integration value is output to the analog-to-digital converter ADC in response to the signal SC.

One end of the enable switch SW14 is commonly connected to the gate of the fourth NMOS QN24 and the gate of the eighth NMOS QN28 that are commonly connected to each other to switch the first switch SW11 to the first integration control signal CP. On). That is, when the first integration control signal CP is provided to the upper switch SW11 and the upper switch SW11 is turned on, the enable switch SW14 is also turned on. Accordingly, the lower current mirror part LCM is discharged while the voltage of the receiving line is applied to the upper current mirror part UCM through the upper switch SW11.

FIG. 17 is a circuit diagram illustrating the microdischarge current source DIC shown in FIG. 15.

Referring to FIG. 17, the microdischarge current source includes a main discharge current mirror unit MDC, a main discharge switching unit MDS, and a sub-discharge current mirror unit SDC. Since the main discharge current mirror unit MDC and the main discharge switching unit MDS are the same as the main discharge current mirror unit MDC and the main discharge switching unit MDS shown in FIG. 9, the same reference numerals are used. The detailed description thereof will be omitted.

The sub-discharge current mirror unit SDC includes a sub-master current unit SMC performing a discharge master function and a sub-slave current unit SSC performing a discharge slave function. The current flowing through the sub-master current portion SMC is mirrored to the sub-slave current portion SSC.

Since the number and connection of the transistors provided in the sub-master current unit SMC are the same as the number of transistors provided in the lower master LM shown in FIG. 16, the description thereof is omitted.

In addition, since the number and connection of transistors included in the sub-slave current unit SSC are the same as the number of transistors included in the lower slave LS shown in FIG. 16, the description thereof is omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. You will understand.

As described above, according to the present invention, as the charge amount is integrated in both the rising and falling periods of the transmission signal, the voltage value can be precisely maintained in the change component of the output voltage after integration, and the received signal is higher than the transmission signal. Can be received.

In addition, the circuit configuration can be simplified by using a charge integrating circuit composed of a current mirror rather than using a charge integrating circuit composed of an OP-AMP to sense a change in capacitance.

In addition, by forming a discharge path in the receiving line corresponding to the charging signal of the transmission line or by charging together the charging signal of the transmission line in the receiving line, the sensing by increasing or decreasing the amount of charge delivered to both ends of the capacitor in a short period of time You can speed it up.

In addition, semiconductors can be easily manufactured, have low power consumption, and can support multi-touch with high detection speed while being particularly resistant to noise from outside.

100: multi-touch panel 200: capacitive sensing circuit
210: transmitting circuit unit 212: transmitter
214: transmitting switch 220: receiving circuit
SW0: first switch SW1: second switch
IN1: first inverter IN2: second inverter
SW11: top switch SW12: bottom switch
UCM: Upper current mirror part LCM: Lower current mirror part
SW13: Output Switch SW14: Enable Switch
DIC: discharge current source SCP: switching signal output
UM: Top Master US: Top Slave
MQP1: Upper PMOS section MQP2: Lower PMOS section
MDC: Main discharge current mirror MDS: Main discharge switching unit
SDC: sub-discharge current mirror unit

Claims (20)

A transmission circuit unit connected to a transmission line of a multi-touch panel and applying a square wave transmission signal to the transmission line; And
Connected to a receiving line of the multi-touch panel, and when a user's human body contact occurs, charges are integrated in accordance with the rising period and the falling period of the square wave transmission signal applied from the transmitting circuit unit, respectively. It includes a receiving circuit unit for detecting the difference between the capacitance generated between the touch or not,
The receiving circuit unit,
An upper switch connected to the receiving line and having a first end turned on or off according to a first integration control signal applied to a control end;
A lower switch connected to a first end of the first line and a second end of the upper switch, the lower end being turned on or off according to a second integration control signal applied to a control end;
An upper current mirror unit connected to a second end of the upper switch and configured to mirror a current flowing along a set current path by setting a current path with the multi-touch panel according to the on of the upper switch;
The upper current mirror part, the upper switch connected to the node connected to the second end of the lower switch, respectively, and corresponding to the current flowing along the set current path with the multi-touch panel according to the on of the lower switch; A lower current mirror unit for discharging by mirroring a current of the upper current mirror unit; And
And an enable switch disposed at an end of the lower current mirror unit and turned on according to the first integration control signal to enable operation of the lower current mirror unit. According to claim 1, wherein the upper current mirror portion and the lower current mirror portion, when the voltage induced by the touch is provided through the receiving line through the receiving line, the receiving edge at the rising edge time and falling edge time of the received signal Capacitive sensing circuit for a multi-touch panel, characterized in that for outputting through the output stage by integrating the corresponding charge of the signal. The capacitive sensing circuit of claim 1, wherein the upper current mirror unit comprises a plurality of transistors arranged in two stages in a current mirror relationship. The method of claim 1, wherein the upper current mirror portion,
Upper master; And
An upper slave mirroring a current flowing through the upper master,
The upper master,
A source connected to a power supply voltage terminal to which a power supply voltage is supplied, and a gate connected to the upper slave;
A second PMOS having a source coupled to the drain of the first PMOS and a gate coupled to the upper slave;
A third PMOS having a gate connected to the upper switch and a source connected to the drain of the second PMOS; And
A gate and a drain are connected in common and connected to the upper switch and the gate of the third PMOS, and the source includes a fourth PMOS connected to the drain of the third PMOS. . The method of claim 4, wherein the upper slave,
An upper PMOS part including a plurality of PMOSs having common gates connected thereto; And
A capacitive sensing circuit for a multi-touch panel, characterized in that the gate comprises a lower PMOS portion consisting of a plurality of PMOSs commonly connected. The capacitive sensing circuit of claim 1, wherein the lower current mirror unit comprises a plurality of transistors arranged in two stages in a current mirror relationship. The method of claim 1, wherein the lower current mirror portion,
Bottom master; And
A lower slave mirroring a current flowing through the lower master,
The lower master,
A first NMOS having a gate and a drain connected in common and connected to the lower switch;
A drain connected to the source of the first NMOS, and a gate connected to the gate and drain of the first NMOS and to the lower switch;
A third NMOS having a drain connected to the source of the second NMOS and a gate connected to the drain of the second NMOS; And
And a drain is connected to the source of the third NMOS, a gate is connected to the drain of the third NMOS, and the source comprises a fourth NMOS connected to the ground voltage. The method of claim 7, wherein the lower slave,
A fifth NMOS having a drain connected to the upper current mirror part and the upper switch, and a gate connected to the gate of the third NMOS; And
The drain is connected to the source of the fifth NMOS, the gate is connected to the gate of the fourth NMOS, the source comprises a sixth NMOS connected to the ground voltage. The method of claim 1, wherein the upper current mirror portion,
Upper master; And
An upper slave mirroring a current flowing through the upper master,
The upper master,
A source connected to a power supply voltage terminal to which a power supply voltage is supplied, and a gate connected to the upper slave;
A second PMOS having a source coupled to the drain of the first PMOS and a drain coupled to the upper switch;
A third PMOS having a source connected to a power supply voltage terminal, a gate connected to a drain of the first PMOS and a source of the second PMOS, and a drain connected to a gate of the second PMOS; And
A source is connected to the drain of the third PMOS and the gate of the second PMOS, the gate is connected to the gate of the third PMOS, and the drain comprises a first NMOS connected to a ground voltage. Capacitive sensing circuit for panel. The method of claim 4, wherein the upper slave,
The source includes a fourth PMOS connected to a power supply voltage terminal;
A second NMOS having a drain connected to the drain of the fourth PMOS, a gate connected to a gate of the fourth PMOS, and a source connected to a ground voltage;
An upper PMOS part including a plurality of PMOSs having common gates connected thereto; And
A gate having a lower PMOS portion including a plurality of PMOSs commonly connected;
In the upper PMOS unit, a source of each of the PMOSs is connected to a power supply voltage terminal, and a common gate is connected to the upper master, the upper switch, and the lower current mirror unit.
In the lower PMOS portion, the source of each of the PMOS portions is connected to the drains of the upper PMOS portion, the gate of the fourth PMOS and the gate of the second NMOS, respectively, and the common gate is connected to the drain and the fourth PMOS. A capacitance sensing circuit for a multi-touch panel, characterized in that connected to the drain of the second NMOS. The method of claim 1, wherein the lower current mirror portion,
Bottom master; And
A lower slave mirroring a current flowing through the lower master,
The lower master,
A drain comprises a third NMOS connected to the lower switch;
A fourth NMOS having a drain connected to the source of the third NMOS and a gate connected to the lower switch;
A fifth NMOS having a drain connected to a gate of the third NMOS, a gate connected to a source of the third NMOS and a drain of the fourth NMOS, and a source connected to a ground voltage; And
A source is connected to a power supply voltage terminal, a gate is connected to a gate of the fifth NMOS, a source of the third NMOS, and a drain of the fourth NMOS, and the drain includes a sixth PMOS connected to the drain of the fifth NMOS. Capacitive sensing circuit for a multi-touch panel, characterized in that. The method of claim 10, wherein the lower slave,
A drain includes a seventh NMOS connected to the upper switch and the upper current mirror unit;
An eighth NMOS having a drain connected to the source of the seventh NMOS, a gate connected to the gate and the bottom switch of the fourth NMOS of the bottom master, and a source connected to a ground voltage;
A sixth NMOS gate connected to a drain of the eighth NMOS and a source connected to a ground voltage terminal; And
A source connected to a power supply voltage terminal, a gate connected to a source of the seventh NMOS, a gate of the sixth NMOS, and a drain including a drain of the PMOS and a seventh PMOS connected to a gate of the seventh NMOS Capacitive sensing circuit for multi-touch panel characterized in that. delete The capacitive sensing circuit of claim 1, wherein the first integral control signal and the second integral control signal are out of phase with each other. The multi-integral control method of claim 1, wherein the first integration control signal turns on the upper switch and the second integration control signal turns off the lower switch in the rising edge section of the square wave transmission signal. -Capacitive sensing circuit for touch panel. The method of claim 15, wherein in the falling edge of the transmission signal of the square wave, the first integral control signal is turned off the upper switch, the second integral control signal is characterized in that the lower switch on -Capacitive sensing circuit for touch panel. The multi-integral control method of claim 1, wherein the first integration control signal turns off the upper switch and the second integration control signal turns on the lower switch in the rising edge section of the square wave transmission signal. -Capacitive sensing circuit for touch panel. 18. The method of claim 17, wherein the first integral control signal turns on the upper switch and the second integral control signal turns off the lower switch in the falling edge section of the square wave transmission signal. -Capacitive sensing circuit for touch panel. The capacitive sensing circuit of claim 1, wherein the transmitting circuit unit and the receiving circuit unit are implemented on one chip. A multi-touch panel in which a plurality of transmission lines and a plurality of receiving lines are disposed;
A transmission circuit unit connected to the transmission line and applying a square wave transmission signal to the transmission line; And
Connected to the receiving line, when a user's human body contact occurs, the blackout generated between the transmission line and the receiving line by integrating charges respectively corresponding to the rising period and the falling period of the square wave transmission signal applied from the transmitting circuit unit It includes a receiving circuit unit for detecting a difference in capacitance to determine whether the touch,
The receiving circuit unit,
An upper switch connected to the receiving line and having a first end turned on or off according to a first integration control signal applied to a control end;
A lower switch connected to a first end of the first line and a second end of the upper switch, the lower end being turned on or off according to a second integration control signal applied to a control end;
An upper current mirror unit connected to a second end of the upper switch and configured to mirror a current flowing along a set current path by setting a current path with the multi-touch panel according to the on of the upper switch;
The upper current mirror part, the upper switch connected to the node connected to the second end of the lower switch, respectively, and corresponding to the current flowing along the set current path with the multi-touch panel according to the on of the lower switch; A lower current mirror unit for discharging by mirroring a current of the upper current mirror unit; And
And an enable switch disposed at an end of the lower current mirror unit and turned on according to the first integration control signal to enable operation of the lower current mirror unit.

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