KR101366515B1 - Uplink signal processing method for lte measuring equipment - Google Patents

Abstract

The present invention relates to an uplink signal processing method of LTE measuring equipment capable of reducing costs of measuring equipment by processing signals in real time and of enabling a FPGA to use the small capacity of a memory by improving an uplink signal processing method in the LTE measuring equipment including the FPGA and DSP. The uplink signal processing method of the LTE measuring equipment capable of processing the LTE uplink signal transmitted from a mobile terminal by including the FPGA and the DSP comprises (a) a step of sequentially storing symbol data, obtained by executing FFT calculation in an uplink signal received from the mobile terminal by the FPGA in real time, in two embedded memories; (b) a step of enabling the FPGA to transmit symbol data stored in one of the embedded memories to DSP; (c) a step of enabling the DSP to successively store seven symbol data received from the FPGA until the symbol data is completely received; and (d) a step of enabling the DSP to execute coherent demodulation and to estimate a channel by processing the symbol data of one slot stored in other memory. According to the aforementioned construction, The embedded memory includes the capacity of one symbol data size. [Reference numerals] (S10) Execute FFT calcualtion in an uplink signal; (S20) Store calculated one size symbol data in two embedded memory sucessively; (S30) Transmit stored one symbol data; (S40) Transmit CP kind information of symbol data; (S50) Store symbol data in a memory with one slot using CP kind information; (S60) Demodulate symbol data stored in other memory with one slot

Description

Uplink signal processing method for LTE measuring equipment

The present invention relates to a method for processing uplink signals in LTE measurement equipment. In particular, the LTE measurement equipment consisting of an FPGA and a DSP improves the method for processing uplink signals, thereby enabling real-time signal processing while using a small amount of memory. It relates to an uplink signal processing method of equipment.

Various radio access technologies have been proposed that enable a mobile terminal to communicate with other mobile terminals or with wired terminals connected to a wired network. Examples of radio access technologies include the Global System for Mobile communications (GSM) and Universal Mobile Telecommunications System (UMTS) technology as defined by the Third Generation Partnership Project (3GPP) and the Code Division Multiple Access 2000 (CDMA 2000) technology as defined by 3GPP2. It includes.

In addition, new standards have been proposed as part of the ongoing evolution of radio access technologies for improved spectrum efficiency, service enhancements, and cost savings, one of which is the long-term evolution from 3GPP, which seeks to strengthen the UMTS radio network. Term Evolution (LTE) standard, and the other is Worldwide Interoperability for Microwave Access (WiMax) technology. In addition, WiBro as a subset of WiMax has been proposed as a national standard and is currently commercialized, and WiBro Evolution, which has been further developed, has been proposed. LTE and WiBro Evolution are commonly referred to as fourth generation (4G) technologies.

Meanwhile, in order to develop a mobile terminal or base station equipment according to the aforementioned standard, various test equipment or measurement equipment for testing its performance is required. A base station emulator is a type of such test / measurement equipment. have. The base station emulator functions as a base station between the mobile station and transmits a downlink signal to the mobile station and receives an uplink signal from the mobile station to perform various analysis.

The uplink signal measurement portion of the base station emulator includes two analog-to-digital (In-phase) signals and quadrature-phase (ADC) signals that are received from the mobile station, respectively. One FPGA (Field Programmable Gaty Array) or FPGA that performs a Converter, Low Pass Filtering (LPF) or Fast Fourier Transform (FFT) operation, and delivers the result to the DSP in one slot, that is, seven symbols. And a plurality of digital signal processors (DSPs) for performing coherent demodulation on the physical channels after estimating the channel by the processed signal.

However, according to the LTE downlink and uplink time domain structures, one radio frame having a length of 10 ms is composed of ten subframes having a length of 10 ms, and each subframe has two 0.5 ms length subframes. It consists of a slot. One slot is composed of seven symbols for normal CP (Normal Cyclic Prefix) and six symbols for extended CP (Extended Cyclic Prefix). The length of time is equal to 0.5 ms. In case of the LTE uplink, a reference signal (RS) is also transmitted for channel estimation. The uplink RS is located in the fourth symbol of each slot in case of normal CP, whereas in case of extended CP. It is located in the third symbol of each slot.

Thus, the FPGA alternately stores the FFT calculation results in even / odd slot order in two memories of built-in seven symbol sizes (based on normal CP), and then in the order of seven symbols in the DSP in even / odd slot order every 0.5 ms. The DSP operates to enable real-time signal processing by performing channel estimation and demodulation on a slot basis.

However, according to the uplink signal processing method of the conventional LTE measurement equipment as described above, the cost of the measurement equipment is increased because two large-capacity memory of the size of seven symbols that can store the FFT operation result in the FPGA is required. There was this.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and improves the uplink signal processing method in LTE measurement equipment composed of FPGA and DSP so that FPGA can use real time signal processing while using a small amount of memory. An object of the present invention is to provide a method for processing uplink signals of LTE measurement equipment to reduce the unit cost.

In the uplink signal processing method of the LTE measurement equipment of the present invention for achieving the above object, in the uplink signal processing method of the LTE measurement equipment for processing the LTE uplink signal transmitted from the mobile terminal having an FPGA and DSP, (a) alternately storing symbol data obtained by FFT operation on an uplink signal received from a mobile terminal in two internal memories, one symbol at a time; (b) the FPGA transmitting one immediately preceding symbol data stored in the remaining internal memory of the two internal memories to the DSP; (c) sequentially storing the symbol data received from the FPGA in one of seven symbol data sizes until the DSP receives all of the slot data of the symbol; and (d) the DSP is already stored in another memory. Estimating a channel and performing coherent demodulation by processing symbol data of one immediately preceding slot.

In the above configuration, the built-in memory is characterized in that the capacity of one symbol data size.

In addition, the FPGA transmits CP (Cyclic Prefix) type information, which is used for the slot including the symbol data being transmitted, to the DSP, and the DSP determines whether all the symbols of one slot amount are received based on the CP type information and RS ( Reference signal) is characterized in identifying the symbol position assigned.

According to the uplink signal processing method of the LTE measurement equipment of the present invention, while fully considering the characteristics of the DSP to perform the signal processing in a unit of up to seven symbols to enable the real-time signal processing, while storing the symbols processed in the FPGA By drastically reducing capacity, the cost of LTE instrumentation can be significantly lowered.

1 is a block diagram of hardware of the LTE measurement equipment to implement the uplink signal processing method of the present invention.
Figure 1 is a functional block diagram for explaining the function of the FPGA and DSP.
3 is a flowchart illustrating a method for processing uplink signal in LTE measurement equipment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the uplink signal processing method of the LTE measurement equipment of the present invention.

FIG. 1 is a block diagram illustrating the hardware configuration of an LTE metrology equipment in which an uplink signal processing method of the present invention is implemented. In FIG. As shown in Figures 1 and 2, LTE measurement equipment, for example, the base station emulator in which the uplink signal processing method of the present invention is implemented, the analog type I-phase signal and Q-phase signal received from the mobile terminal, respectively, Channel estimation and signal coherent demodulation of physical channels are performed by signals processed by two ADCs 10 converting data into a form of data, one FPGA 20 performing LPF or FFT operation, and one FPGA 20 A plurality of DSP 40, for example, are performed.

In the above-described configuration, the FPGA 10 has two memory 40 of one symbol size for storing the FFT calculation result in one symbol unit and transmitting the result to the DSP 40. The FPGA 20 and DSP 40 are interconnected by Serial RapidIO (SRIO) with a transmission rate of 3.125 Gbps. SRIO's actual data rate, excluding the header bits, is 2.5 Gbps.

On the other hand, as described above, the time domain structure of the LTE uplink signal includes a total of 14 symbols (in the case of normal CP) or 12 symbols (in the case of extended CP) in a subframe of 1 ms, and the 4th and 11th. RS is allocated to the third or third and ninth, that is, the fourth symbol of each slot in the case of the normal CP and the third symbol of each slot in the case of the extended CP. Since DSP 40 estimates a channel using RS existing in each slot and performs coherent demodulation based on this, all seven (or six) symbols corresponding to one slot from FPGA 20 are all present. Signal processing is performed after reception. Considering the signal processing characteristics of the DSP 40, the basic symbol unit of data that can be transmitted from the FPGA 20 to the DSP 40 will be 7 or 1, otherwise it corresponds to an even slot or an odd slot. The order of the data is reversed, making coherent demodulation impossible.

In the present invention, the result of the FFT operation performed by the FPGA 20 is alternately stored in order of even / odd memory 30 in one symbol unit for every 71.42 ms, which is 1/14 ms (normal CP reference), and then even / odd Are transmitted to the DSP 40 in one symbol unit. Then, the DSP 40 waits until all seven symbols are received in the FPGA 20, and when all seven symbols have been received, the DSP 40 checks the channel, and the channel is assigned by the RS assigned to the fourth symbol of the received slot. Estimate and perform coherent demodulation.

In detail, the data structure of the LTE uplink signal is based on 32 bits in which 16 bits are allocated to the I-phase signal and the Q-phase signal (hereinafter referred to as 'I / Q signal'). Assuming that the maximum bandwidth of 20MHz bandwidth is supported, the FFT calculation result for one symbol has 1200 samples of 32-bit I / Q signal. Therefore, the time required for the FPGA 20 to transmit one symbol to the DSP 40 and the time required to transmit all seven symbols of one slot, that is, the data processing unit of the DSP 40, are respectively represented by the following equations. It can be determined as 1 and 2.

As can be seen in Equations 1 and 2 above, the time required for transmitting all seven symbols to the DSP 40 in the FPGA 20 is 0.1 which is much smaller than 0.5 ms, which is one slot length of the LTE uplink signal. Because only, DSP 40 receives channel estimation and coherent demodulation for 0.4 ㎳ (0.5 ㎳-0.1 ㎳), the remaining time from receiving all symbols in one slot to receiving all seven symbols in the next slot. By doing this, no problem occurs in real time signal processing.

3 is a flowchart illustrating an uplink signal processing method of the LTE measurement equipment of the present invention. As shown in FIG. 3, the FPGA 20 performs an FFT operation (step S10) on an uplink signal received from a mobile terminal in real time, and alternates one symbol data thus calculated to two built-in memories 30. In the meantime, the data is stored (step S20), and at the same time, one symbol data immediately stored in the other remaining memory 30 is transmitted to the DSP 40 (step S30). In this process, the type information of the CP used in the slot including the currently transmitted symbol data, that is, whether the normal CP or the extended CP is transmitted to the DSP 40 (step S40), the step S40 may be performed before or after step S30. It may be performed at the same time as step S30.

On the other hand, the DSP 40 sequentially stores the symbol data received from the FPGA 20 in one of the seven symbol data sizes until all the symbol data of one slot is received (step S50). At the same time, the DSP 40 processes the immediately preceding slot amount of symbol data already stored in another memory, estimates a channel, and performs coherent demodulation based on the estimated channel (step S60). According to the received CP type information, the total number of symbols and the position of a symbol to which an RS is allocated may be checked. As a result, the DSP 40 can also determine whether all of the slot data of symbol data has been received according to the CP type information transmitted from the FPGA 20.

The uplink signal processing method of the LTE measurement equipment of the present invention is not limited to the above-described embodiment, and may be variously modified and implemented within the range allowed by the technical idea of the present invention.

10: Analog to Digital Converter (ADC),
20: field programmable gate array (FPGA),
30: FPGA internal memory,
40: Digital Signal Processor (DSP)

Claims (3)

In the uplink signal processing method of LTE measurement equipment having an FPGA and a DSP to process the LTE uplink signal transmitted from a mobile terminal,
(a) alternately storing symbol data obtained by FFT operation on an uplink signal received from a mobile terminal in two internal memories, one symbol at a time;
(b) the FPGA transmitting one immediately preceding symbol data stored in the remaining internal memory of the two internal memories to the DSP;
(c) sequentially storing the symbol data received from the FPGA in one of seven symbol data sizes until the DSP receives all of the slot data of symbol data; and
and (d) processing a symbol data of one slot immediately before DSP is already stored in another memory to estimate a channel and perform coherent demodulation. The method of claim 1,
The internal memory uplink signal processing method of the LTE measurement equipment, characterized in that the capacity of one symbol data size. 3. The method according to claim 1 or 2,
The FPGA transmits CP (Cyclic Prefix) type information used in the slot including the symbol data being transmitted to the DSP.
The DSP checks whether all symbols of one slot amount are received based on the CP type information, and determines the symbol position to which a reference signal (RS) is allocated.

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