KR101365811B1 - In-plane switching mode liquid crystal display, and method for manufacturing the same - Google Patents

Abstract

By arranging the data lines horizontally, an opening ratio can be increased, and a horizontal electric field type liquid crystal display device capable of securing a bonding margin in the horizontal direction and a manufacturing method thereof are provided. The liquid crystal display device includes a liquid crystal display panel in which a thin film transistor, a pixel electrode, and a common electrode are formed; A gate line formed in one direction of the liquid crystal display panel; A data line formed in the same direction as the gate line; A gate driver applying a scan signal to the gate line; A data driver for applying a data signal to a data line in synchronization with a scan signal; And a timing controller providing a gate control signal to the gate driver and providing a data control signal and data to the data driver.

Liquid Crystal Display, Data Line, Horizontal, Transverse Field

Description

Transverse electric field type liquid crystal display device and its manufacturing method {In-plane switching mode liquid crystal display, and method for manufacturing the same}

1 is a perspective view of a general liquid crystal display.

2 is a block diagram of a liquid crystal display according to the related art.

3 is a diagram illustrating a unit pixel structure of a liquid crystal display device having a transverse electric field according to the related art.

4 is a vertical cross-sectional view of the thin film transistor array substrate taken along the line AA ′ of FIG. 3.

5 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a diagram illustrating a unit pixel structure of a transverse electric field type liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 7 is a vertical cross-sectional view of the thin film transistor array substrate taken along line B-B ′ and C-C ′ of FIG. 6.

FIG. 8 is a detail view of a vertical cross section taken along line BB ′ of FIG. 7.

FIG. 9 is a detailed view of the vertical cross section taken along the line C-C 'of FIG.

<Brief Description of Drawings>

200: display panel 300: gate driver

400: data driver 500: timing controller

120a: gate line 160c: data line

The present invention relates to a transverse electric field type liquid crystal display device and a manufacturing method thereof.

In general, a liquid crystal display is an apparatus that expresses an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. In the liquid crystal display, two substrates on which the field generating electrodes are formed are disposed so that the surfaces on which the two electrodes are formed face each other, a liquid crystal material is injected between the two substrates, and then a voltage is applied to the two electrodes. By changing the arrangement of the liquid crystal molecules by the electric field, and by controlling the amount of light transmitted through the transparent insulating substrate, the desired image is expressed.

As the liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used. The TFT LCD transmits the red (R), green (G), and blue (B) color filter layers disposed 1: 1 on each liquid crystal pixel after the backlight having white light passes through the liquid crystal pixel and the light transmittance is adjusted. The color mixture of the TFT-LCD is produced by adding mixed color of the emitted light.

1 is a perspective view of a general liquid crystal display.

Referring to FIG. 1, a liquid crystal panel provided in a liquid crystal display device includes a first substrate 10, a second substrate 20, and the first substrate 10 and the second substrate 20 bonded to each other with a predetermined space. It consists of a liquid crystal layer 30 injected between. In this case, the first substrate 10 is defined as a TFT region TFT, a pixel region Pixel, and a storage region C _ST which are switching regions.

The first substrate 10 has a plurality of gate lines 12 arranged in one direction at regular intervals on the transparent glass substrate 11, and a plurality of gate lines 12 in a direction perpendicular to the gate line 12. By arranging the data lines 16, the pixel area Pixel is defined.

In addition, a pixel electrode 18 is formed in each pixel region Pixel, and a thin film transistor TFT is formed at a portion where each gate line 12 and the data line 16 cross each other. The data signal of the data line 16 is applied to each pixel electrode 18 in accordance with the scan signal applied through (12).

In the second substrate 20, a black matrix layer 22 is formed on the transparent glass substrate 21 to block light except for the pixel region Pixel, and the color corresponding to each pixel region is formed in the second substrate 20. R, G, and B color filter layers 23 are formed to represent the common electrode 24 on the color filter layer 23.

A charging capacitor C _ST connected in parallel with the pixel electrode 18 is configured on the gate line 12, and a portion of the gate line 12 is used as the first electrode of the charging capacitor C _ST . As the second electrode, an island-shaped metal pattern formed of the same material as the source and drain electrodes is used.

In the liquid crystal display, the liquid crystal layer 30 formed between the first substrate 10 and the second substrate 20 is aligned by an electric field between the pixel electrode 18 and the common electrode 24, and the liquid crystal layer is aligned. The desired image can be expressed by adjusting the amount of light passing through the liquid crystal layer 30 according to the degree of alignment of the 30.

2 is a block diagram of a liquid crystal display according to the related art.

Referring to FIG. 2, a liquid crystal display according to the related art includes a liquid crystal display panel 80 in which liquid crystal cells are formed in a region defined by data lines D1 to Dm and gate lines S1 to Sn. Include. In addition, the data driver 70 for supplying data to the data lines D1 to Dm of the liquid crystal display panel 80 and the gate lines S1 to Sn of the liquid crystal display panel 80 are driven. It includes a gate driver 60 for the. In addition, the timing controller 50 receives data supplied in units of frames from the system and aligns and outputs each frame data to the data driver 70.

In the liquid crystal display panel 80, liquid crystal is injected between two substrates, and regions defined by data lines D1 to Dm and gate lines S1 to Sn are formed to cross each other on a lower substrate. TFT is formed on the substrate. The TFT supplies the data Data on the data lines D1 to Dm to the liquid crystal cell in response to the gate signals supplied to the gate lines S1 to Sn. For this purpose, the gate electrode of the TFT is connected to the gate line, and the source electrode is connected to the data line, respectively. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell. In addition, a storage capacitor is formed in the liquid crystal cell of the liquid crystal display panel 80. The storage capacitor is formed between the pixel electrode and the front gate line of the liquid crystal cell, or is formed between the pixel electrode and the common electrode of the liquid crystal cell to maintain a constant voltage of the liquid crystal cell.

The timing controller 50 generates the data control signal DCS and the gate control signal GCS using the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the main clock MCLK input from the outside.

3 is a unit pixel structure of a liquid crystal display panel to which an IPS mode according to the related art is applied. 4 is a vertical cross-section taken along line A-A 'in a liquid crystal display panel to which an IPS mode according to the related art is applied. In FIG. 4, for clarity, the vertical cross-section of the thin film transistor, taken along the line II ′ of FIG. 1, is also shown.

3 and 4, the liquid crystal display panel to which the IPS mode according to the related art is applied is a transparent substrate 11, a gate electrode 12a, a common line 12b, a gate insulating layer 13, and an active layer. The semiconductor film 14, the ohmic contact layer 15, the source electrode 16a, the drain electrode 16b, the data line 16c, the passivation film 17, the pixel electrode 18, and the third data line 19. In this case, as illustrated, the data line 16c is disposed to overlap the common line 12b in the vertical direction.

The conventional vertical data line structure requires a sufficient space to secure the line width and the bonding margin of the data line, so that the opening area is narrowed.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a transverse electric field type liquid crystal display device and a method of manufacturing the same which can increase the aperture ratio by arranging data lines horizontally.

Another object of the present invention for solving the above-mentioned problems is to provide a transverse electric field type liquid crystal display device and a method of manufacturing the same that can secure a bonding margin in the horizontal direction.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a liquid crystal display device according to the present invention, a liquid crystal display panel formed with a thin film transistor, a pixel electrode and a common electrode; A gate line formed in one direction of the liquid crystal display panel; A data line formed in the same direction as the gate line; A gate driver applying a scan signal to the gate line; A data driver for applying a data signal to the data line in synchronization with the scan signal; And a timing controller providing a gate control signal to the gate driver and providing a data control signal and data to the data driver.

The data driver may be disposed opposite to the gate driver.

The gate line and the data line may be electrically separated from each other by an acryl layer.

Here, the black matrix of the color filter substrate is formed corresponding to the region where the gate line and the data line are formed, and the black matrix of the color filter substrate is not formed in the vertical direction of the region where the gate line and the data line are formed. It is characterized by.

In order to achieve the above technical problem, a thin film transistor array substrate according to the present invention, a thin film transistor formed on a transparent substrate, including a gate electrode, a source electrode and a drain electrode; A gate line extending from the gate electrode; A data line extending from the source electrode and formed in the same direction as the gate line; A gate insulating layer formed between the gate line and the data line to electrically isolate each other; And a pixel electrode and a common electrode formed in the pixel region.

The gate insulating layer may be an acryl layer.

The data line may be disposed on the gate line or in a lateral direction.

The pixel electrode and the common electrode may be disposed horizontally with each other to form a horizontal electric field.

In order to achieve the above technical problem, a method of manufacturing a thin film transistor array substrate according to the present invention, forming a gate electrode and a gate line extending from the gate electrode; Forming a gate insulating layer on the gate electrode and the gate line; Forming a source electrode and a drain electrode on the gate insulating layer on which the gate electrode is formed, and forming a data line extending from the source electrode in the same direction as the gate line; And forming a pixel electrode and a common electrode in the pixel region.

The details of other embodiments are included in the detailed description and drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

Hereinafter, a transverse electric field type liquid crystal display device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In a multi-domain IPS (In-Plane Switching) mode liquid crystal display in which pixels are divided into a plurality of domains, a common electrode and a pixel electrode are formed in a zigzag shape to form electric fields in different directions. The lines overlap with the common lines to reduce the aperture ratio.

Embodiments of the present invention disclose that the aperture ratio of an IPS model can be improved by arranging data lines horizontally.

5 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 200 in which a thin film transistor, a pixel electrode, and a common electrode are formed; A gate line formed in one direction of the liquid crystal display panel 200; A data line formed in the same direction as the gate line; A gate driver 300 applying a scan signal to the gate line; A data driver 400 for applying a data signal to the data line in synchronization with the scan signal; And a timing controller 500 for providing a gate control signal to the gate driver 300 and providing a data control signal and data to the data driver 400.

Specifically, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 200 in which liquid crystal cells are formed in regions defined by data lines D1 to Dm and gate lines S1 to Sn. do. In addition, the data driver 400 for supplying data to the data lines D1 to Dm of the liquid crystal display panel 200 and the gate lines S1 to Sn of the liquid crystal display panel 200 are driven. The gate driver 300 is included. In addition, the timing controller 500 receives data supplied in units of frames from the system and aligns and outputs each frame data to the data driver 400. In this case, the data driver 400 is disposed opposite the gate driver 300.

Liquid crystal is injected between the two substrates of the liquid crystal display panel 200 and defined by data lines D1 to Dm and gate lines S1 to Sn formed on the lower substrate in the same direction. TFTs are formed in the area. In an embodiment of the present invention, the gate lines S1 to Sn are electrically separated from the data lines D1 to Dm, but are disposed in the same direction, and the data lines D1 to Dm are source electrodes. Connected with

  The TFT supplies the data Data on the data lines D1 to Dm to the liquid crystal cell in response to the gate signals supplied to the gate lines S1 to Sn. For this purpose, the gate electrode of the TFT is connected to the gate line, and the source electrode is connected to the data line, respectively. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell. In addition, a storage capacitor is formed in the liquid crystal cell of the liquid crystal display panel 200. The storage capacitor is formed between the pixel electrode and the front gate line of the liquid crystal cell, or is formed between the pixel electrode and the common electrode of the liquid crystal cell to maintain a constant voltage of the liquid crystal cell.

The timing controller 500 generates the data control signal DCS and the gate control signal GCS by using the horizontal sync signal Hsync, the vertical sync signal Vsync, and the main clock MCLK input from the outside. The data control signal DCS includes a dot clock, a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, a polarity control signal POL, and the like. The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like.

In other words, the gate line and the data line are electrically separated from each other by an acryl layer.

In addition, a black matrix of the color filter substrate is formed corresponding to the region where the gate line and the data line are formed, and a black matrix of the color filter substrate is not formed in the vertical direction of the region where the gate line and the data line are formed. . Accordingly, the aperture ratio can be increased.

6 is a diagram illustrating a unit pixel structure of a transverse electric field type liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 6, a unit pixel of a transverse electric field type liquid crystal display according to an exemplary embodiment may include a gate electrode, a gate line 120a, a source electrode 160a, a drain electrode 160b, and a data line 160c. , A common line 120b, a pixel electrode 180, and a common electrode 190.

As illustrated, the data line 160c may be disposed in the same direction as the gate line 120a, and in this case, the data line 160c may be disposed above or on the side of the gate line 120a.

FIG. 7 is a vertical cross-sectional view of the thin film transistor array substrate taken along line B-B 'and C-C' of FIG. 6.

Referring to FIG. 7, a thin film transistor array substrate according to an embodiment of the present invention may include a thin film transistor formed on a transparent substrate and including a gate electrode 120, a source electrode 160a, and a drain electrode 160b; A gate line 120a extending from the gate electrode 120; A data line 160c extending from the source electrode 160a and formed in the same direction as the gate line 120a; A gate insulating layer 130 formed between the gate line 120a and the data 160c line and electrically separating each other; And a pixel electrode 180 and a common electrode 190 formed in the pixel area.

In detail, the plurality of common electrodes 190 and the pixel electrodes 180 are arranged in the pixel to be substantially parallel to the data line 160c. In addition, a common line 120b connected to the common electrode 190 is disposed in the middle of the pixel, and a pixel electrode line connected to the pixel electrode 180 is disposed on the common line 120b to form the common line ( Overlap with 120b). Storage capacitance is formed in the transverse electric field mode liquid crystal display due to the overlap of the common line 120b and the pixel electrode line.

In the liquid crystal display of the IPS mode configured as described above, the liquid crystal molecules are aligned substantially in parallel with the common electrode 190 and the pixel electrode 180. When the thin film transistor is operated to apply a signal to the pixel electrode 180, a transverse electric field substantially parallel to the liquid crystal panel is generated between the common electrode 190 and the pixel electrode 180. Since the liquid crystal molecules rotate on the same plane along the transverse electric field, gray level inversion due to the refractive anisotropy of the liquid crystal molecules can be prevented.

A gate electrode 120 is formed on the thin film transistor array substrate, and a gate insulating layer 130 is stacked on the entire thin film transistor array substrate. The semiconductor layer 140 is formed on the gate insulating layer 130, and a source electrode 160a and a drain electrode 160b are formed thereon. In addition, a passivation layer 170 is formed on the entire thin film transistor array substrate.

In addition, a plurality of common electrodes 190 are formed on the thin film transistor array substrate, and a pixel electrode 180 and a data line 160c are formed on the gate insulating layer 130, so that the common electrode 190 and the pixel electrode ( The transverse electric field E is generated between 180).

Meanwhile, a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention is as follows. Here, since specific manufacturing processes and conditions are apparent to those skilled in the art, the description thereof is omitted, and reference numerals of FIG. 7 are used for reference.

 First, a gate electrode 120 and a gate line 120a extending from the gate electrode are formed on the transparent substrate 110.

Thereafter, a gate insulating layer 130 is formed on the gate electrode 120 and the gate line 120a.

Next, a source electrode 160a and a drain electrode 160b are formed on the gate insulating layer 130 on which the gate electrode 120 is formed, and the data line 160c extending from the source electrode 160a is gated. It is formed in the same direction as the line 120a.

Thereafter, the pixel electrode 180 and the common electrode 190 are formed in the pixel area, thereby completing the thin film transistor array substrate.

FIG. 8 is a detailed view of a vertical cross section taken along the line BB ′ of FIG. 7, and FIG. 9 is a detailed view of a vertical cross section taken along the line CC ′ of FIG. 7.

Referring to FIG. 8, since the data line does not pass in the portion indicated by C-C ', the width of the pattern becomes narrower, and thus, a block made of the common electrode and the pixel electrode by the width of the narrowed pattern (Block). ) Can be additionally arranged to increase the aperture ratio. That is, it can be seen that the width is formed narrower than the portion shown by the conventional A-A '.

Referring to FIG. 9, as shown by reference numeral E, a photo acrylic layer is formed as the gate insulating layer 130 on the gate line 120a to be formed between the data line 160c and the gate line 120a. Capacitance can be prevented.

According to an exemplary embodiment of the present invention, a pair of the common electrode and the pixel electrode is called a block, and as the number of blocks increases in the pixel, the aperture ratio increases. By arranging the data lines horizontally, the pixel area is increased by that much, and the number of blocks can be increased, so that the aperture ratio can be increased. That is, since the black matrix of the color filter substrate is formed corresponding to the region where the gate line and the data line are formed, the black matrix of the color filter substrate does not have to be formed in the vertical direction of the region where the gate line and the data line are formed. In response, the aperture ratio can be increased.

In addition, when the thin film transistor substrate and the color filter substrate are bonded together, the bonding margin in the horizontal direction can be easily secured. That is, since the width in the horizontal direction is secured in proportion to the missing data line, the bonding margin is also easily secured.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

According to the present invention, by arranging the data lines horizontally, the aperture ratio can be increased, and the bonding margin in the horizontal direction can be secured.

Claims (12)

A liquid crystal display panel on which a thin film transistor, a pixel electrode, and a common electrode are formed; A gate line formed in one direction of the liquid crystal display panel; A data line extending from the source electrode of the thin film transistor and formed in the same direction as the gate line; A gate driver applying a scan signal to the gate line; A data driver for applying a data signal to the data line in synchronization with the scan signal; And A timing controller providing a gate control signal to the gate driver and providing a data control signal and data to the data driver Liquid crystal display comprising a. The method of claim 1, And the data driver is disposed opposite to the gate driver. The method of claim 1, And the gate line and the data line are electrically separated from each other by an acryl layer. The method of claim 1, The black matrix of the color filter substrate is formed corresponding to the region where the gate line and the data line are formed, and the black matrix of the color filter substrate is not formed in the vertical direction of the region where the gate line and the data line are formed. Liquid crystal display. A thin film transistor formed on the transparent substrate and including a gate electrode, a source electrode, and a drain electrode; A gate line extending from the gate electrode; A data line extending from the source electrode and formed in the same direction as the gate line; A gate insulating layer formed between the gate line and the data line to electrically isolate each other; And Pixel electrodes and common electrodes formed in the pixel region Thin film transistor array substrate comprising a. The method of claim 5, The gate insulating film is a thin film transistor array substrate, characterized in that the acrylic (acryl) layer. The method of claim 5, And the data line is disposed above the gate line or in a lateral direction. The method of claim 5, The pixel electrode and the common electrode are arranged horizontally with each other to form a horizontal electric field. Forming a gate electrode and a gate line extending from the gate electrode on the transparent substrate; Forming a gate insulating layer on the gate electrode and the gate line; Forming a source electrode and a drain electrode on the gate insulating layer on which the gate electrode is formed, and forming a data line extending from the source electrode in the same direction as the gate line; And Forming a pixel electrode and a common electrode in the pixel region Method of manufacturing a thin film transistor array substrate comprising a. 10. The method of claim 9, The gate insulating film is a method of manufacturing a thin film transistor array substrate, characterized in that the acrylic (acryl) layer. 10. The method of claim 9, And the data line is disposed above the gate line or in a lateral direction. 10. The method of claim 9, And the pixel electrode and the common electrode are disposed horizontally to each other to form a horizontal electric field.

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