KR101355463B1 - Transmitter for data communication - Google Patents

Abstract

The present invention can determine the optimal pre-emphasis degree according to the channel situation by modeling the channel to perform pre-emphasis of the output driver, and adjust the delay value of the delay data by the digital delay signal. The present invention relates to a transmitter for data communication that can operate stably with noise on a phase.
For example, a serializer having an input terminal and an output terminal connected to a channel and converting data input to the input terminal into serial data; A pre-output driver primarily pre-emphasizing the serial data to generate pre-emphasis data; An output driver which receives the pre-emphasis data and generates output data; A pre-output controller configured to simulate a state of the channel to adjust a delay value of delay data applied to pre-emphasis of the output driver; And a variable capacitor disposed between the output driver, the pre-output controller, and the pre-output controller, the capacitance being adjusted according to the delay value, wherein the output driver stores the pre-emphasis data at the delay value. Disclosed is a transmitter for data communication, characterized in that it is regulated by a second pre-emphasis.

Description

 [0001] TRANSMITTER FOR DATA COMMUNICATION [0002]

The present invention relates to a transmitter for data communication, and in particular, by modeling the channel to determine the optimal degree of pre-emphasis according to the situation of the channel to perform the pre-emphasis of the output driver and delayed by the digital delay signal The present invention relates to a transmitter for data communication that can stably operate to noise in a system by adjusting a delay value of data.

With the development of the semiconductor process, the throughput and transmission amount of data for realizing high resolution has been rapidly increased, whereas the rate of channel development cannot keep up. Attenuation of the data signal occurs in the channel because the rate of evolution of the channel does not keep up with the throughput of the data.

To this end, the transmitter applies pre-emphasis to the output driver to restore the data attenuation due to the limitation of the bandwidth of the channel, and the equalizer is applied to the receiver.

The pre-emphasis is implemented through a main tap driven with original data and an auxiliary tap driven through delay data, and the degree of the pre-emphasis is controlled by adjusting the amount of current flowing through the auxiliary tap. Properly adjusting the amount of current depends on information about the data attenuation of the channel. If the amount of current does not match the data attenuation of the channel, the jitter component of the data output by the jitter due to the data pattern may be large. Therefore, it is important to determine the amplification degree of the high frequency component through the pre-emphasis through the optimal amount of current for performing the pre-emphasis.

However, the method of controlling the degree of pre-emphasis through the amount of current flowing through the auxiliary tap as described above cannot determine the appropriate amplification degree of the high frequency component. Accordingly, after the cable is modeled separately, a method of determining the compensation degree by adjusting the amount of current of the auxiliary tap to amplify a high frequency component sufficient to compensate for data corruption in a channel is generally used. In such a case, it is difficult to control the amount of current to be changed according to the operating environment of the chip, and it is not easy to maintain the constant because the amount of current is controlled using a general analog voltage.

An object of the present invention is to determine the optimal degree of pre-emphasis according to the channel situation by modeling the channel, and to perform the pre-emphasis of the output driver. The present invention provides a transmitter for data communication that can be controlled to provide stable operation to noise in a system.

A data communication transmitter according to an embodiment of the present invention for achieving the above object has an input terminal, an output terminal connected to the channel, and a serializer for converting the data input to the input terminal into serial data; A pre-output driver primarily pre-emphasizing the serial data to generate pre-emphasis data; An output driver which receives the pre-emphasis data and generates output data; A pre-output controller configured to simulate a state of the channel to adjust a delay value of delay data applied to pre-emphasis of the output driver; And a variable capacitor installed between the pre-output driver and the output driver and the pre-output controller, the capacitance of which is adjusted according to the delay value, wherein the output driver includes the pre-emphasis data at the delay value. By means of pre-emphasis secondarily.

The pre-output driver and the output driver may be formed in the same structure.

The pre-output controller includes a pattern generator for generating a first data pattern and a second data pattern; A duplicated output driver formed in the same structure as the output driver and generating simulated data patterns by passing the first data pattern and the second data pattern; A channel modeling filter configured to simulate the situation of the channel to pass the simulated data patterns; A digital signal converter for converting the simulated data patterns passed through the channel modeling filter into digital signal patterns; Digital control logic for generating a digital delay control signal for adjusting the delay value.

The channel modeling filter is implemented as a low pass filter including a resistor and a capacitor, and may be configured to adjust attenuation of data through a control signal.

The digital control logic may include a sense-embedded flip flop to which the digital signal pattern is input; And a counter at which the output is increased until the output of the sense-implied flip flop is kept constant.

The digital control logic may fix the output of the counter to determine the delay value when the output of the sense-implied flip flop becomes “0”.

The capacitance of the variable capacitor may be adjusted by the digital delay control signal.

The digital delay control signal may be input to the copy output driver.

The first data pattern may be a data pattern having the lowest high frequency component, and the second data pattern may be a data pattern having the highest high frequency component.

The first data pattern may be a data pattern of 1100, ..., 1100, and the second data pattern may be a data pattern of 1000, ..., 1000.

The transmitter for data communication according to the embodiment of the present invention includes a pre-emphasis controller including a channel modeling filter, so that the information of the channel cannot be known in the conventional data transmitter, so that the output driver performs pre-emphasis only as predetermined. Compared to the case in which the channel state cannot be reflected, the optimal pre-emphasis can be determined by adjusting the delay value of the delay data while reflecting the channel state. Accordingly, the data transmitter according to the embodiment of the present invention allows the output driver to pre-emphasize the delay data in the state where the jitter component is minimized while reflecting the channel condition, thereby operating the semiconductor process and operating temperature of the chip operating in the channel. And the pre-emphasis irrespective of the voltage can be pre-amplified high-frequency components of the data loss occurs in the channel to compensate for the data loss in the channel.

In addition, the data transmitter according to the embodiment of the present invention includes a pre-emphasis controller including digital control logic, thereby adjusting the pre-emphasis degree by adjusting the analog voltage, but digitally delaying the delay value of the delay data. It can be controlled by a signal to ensure stable operation of noise on the system.

1 is a block diagram showing the structure of a transmitter for data communication according to an embodiment of the present invention.
2 is a circuit diagram showing the structure of a pre-output driver and an output driver.
3 is a circuit diagram of the channel modeling filter of FIG. 1.
4 is a circuit diagram illustrating a structure of the digital control logic of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram showing a structure of a transmitter for data communication according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a structure of a pre-output driver and an output driver, and FIG. 3 is a circuit diagram of the channel modeling filter of FIG. 4 is a circuit diagram illustrating a structure of the digital control logic of FIG. 1.

1 to 4, a transmitter 100 for data communication according to an embodiment of the present invention includes a serializer 110, a pre-output driver (POD) 120, and an output. The driver includes an output driver 130, a pre-emphasis controller 140, a capacitor unit 150, and a phase locked loop (PLL) 160. The data communication transmitter 100 transmits data to a receiver through a channel of a cable.

The serializer 110 converts n (n is a natural number of two or more) bits of data (Data) input to the input terminal of the transmitter 100 for data communication into n: 1 serial data. The serializer 110 generates serial data of PreD _n , PreD _{n −1} , and PreD _{n −2} based on the clock generated by the phase locked loop circuit 160. Here, the PreD _n Serial data is main data, PreD _{n -1} serial data is data delayed by 1 UI from PreD _n serial data, and PreD _{n -2} serial data is data delayed by 2 UI from PreD _n serial data.

The pre-output driver 120 performs pre-emphasis on the serial data of PreD _n , PreD _{n −1} , and PreD _{n −2} , and then pre-emphasis data of D _n , D _{n −1} . Create them. Here, the D _{n -1} pre-emphasis data is D _n Data delayed by 1 UI from the pre-emphasis data, and pre-emphasis is to compensate for the loss of data in the channel by amplifying the high frequency component of the data in which the loss occurs in the channel in advance. The pre-output driver 120 is composed of a circuit as shown in FIG. As shown in Figure 2, the pre-output driver 120 is configured to include a resistor for matching the impedance of the cable. As shown in FIG. 2, the pre-output driver 120 includes a tab for pre-emphasis implemented by moving a tab installed for pre-emphasis at a final stage of an existing output driver. It is composed. Accordingly, the pre-output driver 120 can reduce the power consumption by reducing the number of taps of the existing output driver, so that the pre-emphasis is performed in the output driver 130 in a state where the taps are reduced. . On the other hand, due to the output driver 130 of the tab is reduced, the number of pre-output driver 120 for driving the output driver 130 may be reduced.

The output driver 130 receives pre-emphasis data of D _n and D _{n -1} generated by the pre-output driver 120, and uses the pre-emphasis data of D _n and D _{n -1} . By performing pre-emphasis secondly, output data of TxDatan and TxDatap are generated and transmitted to the output terminal of the data communication transmitter 100, that is, the input terminal of the channel. The output driver 130 is formed in the same structure as the pre-output driver 120.

The pre-emphasis controller 140 is configured to adjust a delay value of delay data necessary for pre-emphasis of the output driver 130. In detail, the pre-emphasis controller 140 may include a pattern generator 141, a replica output driver 142, a channel modeling filter 143, and a digital signal converter. CML-to-Logic Converter (CLC) 144 and Digital Control Logic (DCL) 145.

The pattern generator 141 generates a first data pattern having the least jitter caused by the data pattern and a second data pattern having the largest jitter caused by the data pattern. Here, the first data pattern may be a data pattern of 1100,... 1100 having the lowest high frequency component, and the second data pattern may be a data pattern of 1000, ..., 1000 having the highest high frequency component. . Since the jitter component between the data pattern with the highest high frequency component and the data pattern with the least high frequency component is the largest, the delay value of the delay data is adjusted to reduce the jitter component to the minimum, thereby pre-emphasis of the output driver 130. Because it is efficient to do.

The duplicated output driver 142 receives the first data pattern and the second data pattern from the pattern generator 141 and passes them through to generate simulated data patterns of Rout ₀₀₁₁ and Rout ₀₀₀₁ . The duplicated output driver 142 is configured by duplicating the output driver 130. This relates to causing the output driver 130 to measure and predict the jitter component of the delay data passing through the channel from simulated data patterns of Rout ₀₀₁₁ , Rout ₀₀₀₁ generated from the duplicate output driver 142 in advance. This is to simulate the delay data passing through the output driver 130 before passing through. Here, the duplicated output driver 142 has the same structure as the output driver 130 but has a small current consumption since it is not directly connected to the channel.

The channel modeling filter 143 is a filter modeling a channel of the cable. The channel model filter 143 is composed of a circuit as shown in FIG. 3 to prevent an increase in complexity and area when an inductor among a resistor, a capacitor, and an inductor for implementing a cable is implemented on a chip. That is, the channel modeling filter 143 is implemented as a low pass filter including a resistor and a capacitor to implement the degree of attenuation of data on the channel in a simple circuit as shown in FIG. 3, and a control signal. It is configured to control the attenuation of the data through. The channel modeling filter 143 adjusts the data attenuation of the channel that the cable may have when the actual cable is connected to the transmitter for data communication through a digital signal from the outside, and generates the Rout ₀₀₁₁ and Rout generated from the duplicate output driver 142. _It can be applied to simulated data patterns of ₀₀₀₁ . Here, the data patterns passing through the duplicated output driver 142 and the channel modeling filter 143 have different frequency components and thus have different degrees of attenuation. For this reason, when the data pattern passed through the duplicate output driver 142 and the channel modeling filter 143 is converted into a digital signal, a delay difference between the data patterns occurs. This delay difference can be tailored using the digital control logic 145 to minimize jitter in accordance with the data pattern, thereby determining the degree of optimized pre-emphasis.

The digital signal converter 144 receives the simulated data patterns of Rout ₀₀₁₁ and Rout ₀₀₀₁ from the copy output driver 142 and the channel modeling filter 143 and converts them into digital signal patterns of Cout ₀₀₁₁ and Cout ₀₀₀₁ . Such digital signal patterns of Cout ₀₀₁₁ and Cout ₀₀₀₁ are easier than analog signal patterns to adjust delay values of delay data.

The digital control logic 145 includes a sense-amplitude flip flop (SAFF) 145a and a counter 145b as shown in FIG. 4, and includes Cout ₀₀₁₁ and Cout _0001. A digital delay control signal (Digital Delay Contorl Signal) is generated to detect the difference between the delays of the digital signal patterns and to adjust the difference. The digital delay control signal is used to adjust the delay value of the delay data for pre-emphasis by adjusting the capacitance of the output terminal of the pre-output driver 120. The digital delay control signal is input to the copy output driver 142 to be applied to the first data pattern and the second data pattern generated by the pattern generator 141. Although not shown, the replica output driver 142 includes a variable capacitor capable of adjusting capacitance by a digital delay control signal.

The sense-implied flip-flop 145a can detect very small delay differences of data patterns unlike other master-slave flip-flops or D-flip-flops. The sense-embedded flip-flop 144 is initialized by resetting the output to " 0 " every cycle. Here, the sense by the property that the initialization until the moment the digital signal patterns are sampled in the Cout ₀₀₀₁ digital signal pattern of Cout ₀₀₀₁ is changed from "1" to "0" output of the flo Li sulfide flip-flop (145a) is " The output value of the counter 145b is incremented until 1 " As the output value of the counter 145b increases, the capacitance adjusted by the digital delay control signal increases, and through this operation, the delay value of delay data for pre-emphasis is increased.

After the capacitance is adjusted to reduce the difference in the delay of the data patterns reflecting the attenuation of the data in the real channel through the digital delay control signal generated by the digital control logic 145, the pre- Emphasis is performed.

The pre-emphasis controller 140 having the above configuration measures the jitter component of the data patterns passing through the replica output driver 142 and the channel modeling filter 143 and reflects the measured value to determine the delay value of the delay data. Change the digital value to adjust it. This operation consists of a feedback circuit that continuously changes the digital value by comparing the jitter components to change the delay value. That is, by using a repetitive feedback system to find a delay value that can minimize the delay difference of the delay data by adjusting the capacitance, it is possible to find the optimized delay value. As a result, delay data having a delay value optimized according to the semiconductor process of the chip operating in the channel, the change in the operating voltage and the temperature of the chip is input to the output driver 130, and pre-emphasis is performed. Accordingly, delay data in a state in which the jitter component is reduced as much as possible by reflecting the attenuation of data in the channel may be pre-emphasized in the output driver 130.

The capacitor unit 150 is installed between the pre-output driver 120, the output driver 130, and the pre-output controller 140, and includes a variable capacitor 151 and a dummy capacitor 152. The variable capacitor 151 is adjusted to have a capacitance in which the difference in delay of data patterns is reduced through the digital delay control signal generated by the digital control logic 145. The dummy capacitor 152 is configured to have a capacity equal to the minimum capacity of the variable capacitor 151.

The phase locked loop circuit 160 generates a clock used in the serializer 110 using a reference clock and provides the clock to the serializer 110 and the pattern generator 141.

As described above, the data transmitter 100 according to the exemplary embodiment of the present invention includes the pre-emphasis controller 140 including the channel modeling filter 143, so that the information of the channel cannot be known in the conventional data transmitter. The optimum degree of pre-emphasis can be determined by adjusting the delay value of the delay data while reflecting the channel condition as compared with the case where the output driver performs the pre-emphasis only as predetermined and does not reflect the channel condition.

Accordingly, the data transmitter 100 according to an embodiment of the present invention operates by operating the channel by causing the output driver 130 to pre-emphasize the delay data in a state where the jitter component is reduced as much as possible while reflecting the situation of the channel. Regardless of the chip's semiconductor process, operating temperature, and voltage, optimal pre-emphasis allows high-frequency components of the data that are lost in the channel to be pre-amplified to compensate for data loss in the channel.

In addition, as described above, the data transmitter 100 according to the embodiment of the present invention includes the pre-emphasis controller 140 including the digital control logic 145, thereby adjusting the pre-emphasis degree to the analog voltage. The delay value of the delayed data can be adjusted with the digital delay signal, so that it can operate stably to the noise on the system.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation and that those skilled in the art will understand that various modifications and equivalent arrangements may be made therein It will be possible.

100: transmitter for data communication 110: serializer
120: pre-output driver 130: output driver
140: pre-output controller 141: pattern generator
142: Duplicate Output Driver 143: Channel Modeling Filters
144: digital signal converter 145: digital control logic
145a: sense-implied flip flop 145b: counter
150: capacitor portion 151: variable capacitor
152: dummy capacitor 160: phase locked loop circuit

Claims (10)

In the transmitter for data communication having an input terminal and an output terminal connected to the channel,
A serializer for converting data input to the input terminal into serial data;
A pre-output driver primarily pre-emphasizing the serial data to generate pre-emphasis data;
An output driver which receives the pre-emphasis data and generates output data;
A pre-output controller configured to simulate a state of the channel to adjust a delay value of delay data applied to pre-emphasis of the output driver; And
A variable capacitor installed between the pre-output driver and the output driver and the pre-output controller to adjust capacitance according to the delay value,
And the output driver second pre-emphasizes the pre-emphasis data by adjusting the delay value. The method of claim 1,
And said pre-output driver and said output driver have the same structure. The method of claim 1,
The pre-output controller is
A pattern generator for generating a first data pattern and a second data pattern;
A duplicated output driver formed in the same structure as the output driver and generating simulated data patterns by passing the first data pattern and the second data pattern;
A channel modeling filter configured to simulate the situation of the channel to pass the simulated data patterns;
A digital signal converter for converting the simulated data patterns passed through the channel modeling filter into digital signal patterns; And
And digital control logic for generating a digital delay control signal for adjusting the delay value. The method of claim 3, wherein
The channel modeling filter is implemented as a low pass filter including a resistor and a capacitor, and the data communication transmitter, characterized in that configured to adjust the attenuation of the data through a control signal. The method of claim 3, wherein
The digital control logic
A sense-implied flip flop to which the digital signal pattern is input; And
And a counter for increasing the output until the output of the sense-implied flip flop remains constant. The method of claim 5, wherein
And the digital control logic determines the delay value by fixing the output of the counter when the output of the sense-implied flip flop becomes “0”. The method of claim 3, wherein
And the capacitance of the variable capacitor is controlled by the digital delay control signal. The method of claim 3, wherein
And the digital delay control signal is input to the copy output driver. The method of claim 3, wherein
When comparing the widths of the smallest signal widths included in each data pattern that the pattern generator can generate,
The width of the smallest signal width in the first data pattern is largest,
And the smallest width of the smallest signal width in the second data pattern. The method of claim 9,
The first data pattern is a data pattern in which 1100 is repeated.
The second data pattern is a data communication transmitter, characterized in that 1000 is repeated data pattern.

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