KR101354006B1 - Bottom electrode using by vertical silcon nanowires and fabrication method of the same - Google Patents

Bottom electrode using by vertical silcon nanowires and fabrication method of the same Download PDF

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KR101354006B1
KR101354006B1 KR1020120088457A KR20120088457A KR101354006B1 KR 101354006 B1 KR101354006 B1 KR 101354006B1 KR 1020120088457 A KR1020120088457 A KR 1020120088457A KR 20120088457 A KR20120088457 A KR 20120088457A KR 101354006 B1 KR101354006 B1 KR 101354006B1
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thin film
metal thin
silicide
forming
catalyst
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KR1020120088457A
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Korean (ko)
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이석희
정현호
최지훈
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한국과학기술원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention discloses a bottom electrode using vertical silicon nanowires and a method for fabricating the same. A catalyst etching process is simplified by using a property where a catalyst metal used for a catalyst etching method remains under the nanowires, without a separate post lower electrode process. The contact resistance of silicon and silicide are greatly improved by using a silicide formation metal thin film. The method includes a step for forming a lamination pattern structure where the silicide formation metal thin film and a catalyst metal thin film of a mesh shape are layered on the upper part of the silicon substrate; a step for manufacturing the vertical silicon nanowires in the silicon substrate by a metal catalyst etching process; and a step for forming a silicide by silicon reaction by performing a thermal process on the silicide formation metal thin film.

Description

Bottom Electrode Using by Vertical Silcon Nanowires and Fabrication Method of the Same}

The present invention relates to a lower electrode using vertical silicon nanowires and a method for forming the lower electrode, wherein a lower electrode of vertical silicon nanowires is formed by stacking a catalyst metal thin film and a silicide forming metal thin film.

In the current high oil price era, various technologies for solving energy problems are emerging, and thermoelectric device technology that generates energy using waste heat and geothermal heat is also emerging. Since general thermoelectric materials are very toxic and rare metals, they are highly advantageous in terms of material cost and industrialization. Although the thermoelectric performance of bulk silicon is not good, nanometer sized silicon has a very low thermal conductivity due to the scattering of phonons on the surface and thus shows good thermoelectric performance. This representative structure is a vertical silicon nanowire structure.

Since the vertical silicon nanowire structure has a large surface area compared to the volume, the contact area with other gas molecules has a large area, which makes it suitable for a sensitive sensor structure. In addition, it has many applications in optoelectronics and transistors.

Catalytic metal etching method is to pattern metals such as gold, silver and platinum on the silicon substrate and immerse them in HF and H 2 O 2 aqueous solution. It is oxidized and etched. These phenomena leave uncovered portions of the catalytic metal, resulting in a structure of vertical silicon nanowires.

Silicide refers to a compound formed by reacting a positively charged material with silicon. Typical silicon and metal form Schottky junctions, resulting in degradation of device performance by the resulting Schottky barrier. To solve this problem, silicide materials are used to form ohmic contacts of silicon and metal contacts in the source, drain, and poly gate structures of the CMOS process. Generally, materials used in CMOS processes include Ti, Co, Ni, and W. When the material is heat-treated in contact with silicon, it reacts with silicon to form a phase change to form a compound. This reduces the contact resistance between the silicon and the metal and forms an ohmic junction.

There is a need to use semiconductor nanowires as building blocks for large area electronic and optoelectronic devices. A wide range of Group 4, Group 3-5, and Group 2-6 semiconductor nanowires can be reasonably synthesized to have adjustable chemical composition, physical dimensions and electronic properties (Duan, X. et al., Nanowire Nanoelectronics Assembled from the Bottom-). up, in Molecular Nanoelectronis, Reed, M. ed., American Scientific Publisher, New York (2002); Duan, X. and Lieber, CM, Adv. Mater. 12: 298-302 (2000) and Gudiksen, MS, etc. See J. Phys. Chem. B 104: 4062-4062 (2001), wherein each of these documents is incorporated in its entirety for all purposes). The extended longitudinal and shortened transverse dimensions also make the nanowires the minimum dimension material for efficient transport of the electrical carrier. Several nanodevices have been described using nanowires including field effect transistors (FETs), logic circuits, memory arrays, light-emitting diodes (LEDs) and sensors (Huang, Y. et al., Nano Letters 2: 101). -105 (2002); Huang, Y. et al., Science 294: 1313-1317 (2001); Duan, X. et al., Nano Letters 2: 487-490 (2002); Wang, J. et al., Science 293 : 1455-1457 (2001); see Cui, Y. et al., Science 293: 1289-1292 (2001); US Patent Application No. 60 / 414,359 and US Patent Application No. 60 / 414,323, each of which is for all purposes. For the whole is merged). Nanowires have the potential as high mobility electrical carriers, but at present, the use of nanowires in devices is limited by the difficulties encountered when obtaining nanowires from a nanowire synthesized substrate. If no nanowires are obtained, the range of nanodevices employing nanowires is limited because the device can only use substrates suitable for nanowire synthesis. Currently, nanowires are obtained by separating nanowires from a substrate using mechanical devices such as laser blades or other knife edges. The method has the problem of including a defect that can cause physical damage to the nanowires while obtaining the nanowires. Therefore, there is a need to develop an efficient method for obtaining nanowires from a substrate on which nanowires are synthesized.

In the process of fabricating vertical silicon nanowires using a metal catalyst etching method, forming a lower electrode is a very difficult problem. If the distance between the nanowires is wide and the length is short, a method of depositing a metal to be used as the lower electrode may be used. However, in order to effectively use the nanowires, nanowires having a long distance and a long distance are used. In this case, it is very difficult to separately form the lower electrode after the nanowire formation.

To solve this problem, we devised a method of using this metal directly as an electrode because the metal used when using the metal-catalyzed etching method is continuously remaining under the vertical silicon nanowire etching process, but the metal is used as the silicon and the Schottky. Since a bond is formed, a silicide forming material is stacked on top to improve contact resistance. Therefore, the lower part of the nanowire is formed by forming a metal and silicide under the nanowire and thereby forming an ohmic junction between the metal and silicon.

The present invention for achieving the above object includes the following configuration.

That is, the method of forming the lower electrode of the vertical silicon nanowire according to the embodiment of the present invention includes the steps of: (a) forming a pattern structure in which a catalyst metal thin film and a silicide forming metal thin film are stacked on a silicon substrate; (b) fabricating vertical silicon nanowires on the silicon substrate by a metal catalyst etching process; And (c) forming the silicide by causing the silicide forming metal thin film to react with the silicon by a heat treatment process.

In addition, the lower electrode of the vertical silicon nanowire according to an embodiment of the present invention, a pattern structure having a pattern in which a catalyst metal thin film and a silicide forming metal thin film having a mesh form on the silicon substrate is stacked; Vertical silicon nanowires fabricated on the silicon substrate through a metal catalyst etching process; And silicide formed by causing a silicon reaction of the silicide-forming metal thin film through a heat treatment process.

According to the present invention, in the process of fabricating the vertical silicon nanowire array using the catalytic metal etching method, the lower electrode can be easily formed as part of the catalytic metal etching process without a complicated process for forming the lower electrode.

In addition, when the lower electrode is formed using the above method, the performance may also be lower than the silicide material used in the conventional CMOS process, and thus may have a low resistance value. You can expect

1 is a schematic diagram illustrating a process of fabricating a laminated mesh structure of a catalyst metal and a silicide forming metal and patterning the silicon substrate using a nano hole array structure template.
2 is a schematic diagram of a process of fabricating a laminated mesh structure of a catalyst metal and a silicide forming metal and patterning the silicon substrate using a lithography process
3 is a schematic diagram illustrating a process of fabricating vertical silicon nanowires using a metal catalyst etching method using a deposited laminated mesh structure.
4 is a schematic diagram of a silicide formation process in a laminated mesh structure remaining under the vertical silicon nanowire array through heat treatment.
5 is a schematic diagram of a simple nanowire array structure example in which a fabricated vertical silicon nanowire underlying metal may be used.

[Example]

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention relates to a lower electrode of a vertical silicon nanowire and a method of forming the same, and forms a lower electrode of the vertical silicon nanowire 400 by laminating a catalyst metal thin film 200 and a silicide forming metal thin film 300. More specifically, the catalyst metal thin film 200 and the vertical silicon nanowires are formed by forming the lower region of the vertical silicon nanowires 400 and the silicides 500 using Ni and Ti, which are well known silicide 500 materials. It not only lowers the contact resistance of 400) but also improves the performance of vertical silicon nanowire devices.

That is, the lower electrode 2000 of the vertical silicon nanowire of the present invention has a pattern structure 1000 having a pattern in which a catalyst metal thin film 200 having a mesh form and a silicide forming metal thin film 300 are stacked on a silicon substrate. The vertical silicon nanowire 400 and the silicide forming metal thin film 300 fabricated on the silicon substrate through the metal catalyst etching process may include the silicide 500 formed by causing a silicon reaction through the heat treatment process.

In addition, in the method of forming a lower electrode of the vertical silicon nanowire of the present invention, a pattern structure 1000 in which a catalyst metal thin film 200 having a mesh form and a silicide forming metal thin film 300 is stacked is formed on a silicon substrate, and a metal catalyst After the vertical silicon nanowires 400 are manufactured on the silicon substrate by the etching process, the silicide forming metal thin film 300 generates a silicon reaction by the heat treatment process to form the silicide 500.

More specifically, FIG. 1 according to an embodiment of the present invention is a method of forming a mesh laminated structure of a catalyst metal thin film 200 and a silicide-forming metal thin film 300 by using a template 100 having a hole structure. Is a schematic for.

Gold (Au), silver (Ag), or platinum (Pt) belonging to the catalyst metal is used as the catalyst metal thin film 200 or the silicide forming metal thin film 300 having a mesh form.

The template (Template: 100) that can be used typically has an Aanodic Aluminum Oxide (AOA) structure.

For example, the metal is deposited on the pattern structure 1000 by chemical vapor deposition as well as physical vapor deposition such as sputtering and thermal vapor deposition on the AAO structure. The metal to be deposited first deposits 10 nanometers of gold (Au) to be used as the catalytic metal thin film 200.

A metal (ex: NiPt) forming silicide on the top is deposited by 10 nanometers. In general, titanium (Ti), cobalt (Co), nickel (Ni) or tungsten (W) may also be used as the catalytic metal thin film 200 or silicide-forming metal thin film 300 having a mesh shape, but in this case, There is a fear of etching by the HF solution used in the metal catalyst etching process.

In order to solve this problem, a method of depositing titanium, cobalt, and nickel metals and then redepositing and re-depositing gold, which is rarely reactive with HF, or using an alloy containing platinum in a metal such as nickel have. Nickel mixed with platinum (NiPt) is not etched in the HF solution, which can solve the problem of subsequent processes.

In another embodiment, when titanium, cobalt, nickel or tungsten is mixed with platinum (Pt) to form titanium alloy (TiPt), cobalt alloy (CoPt), nickel alloy (NiPt) or tungsten alloy (WPt), titanium Alloys, cobalt alloys, nickel alloys or tungsten alloys will not be bad to take advantage of, as they prevent them from being etched by the HF solution during the metal catalyst etching process.

In other words, as the titanium, cobalt, nickel or tungsten is redeposited or capped by a catalytic metal including gold (Au), silver (Ag) and platinum (Pt), the silicide forming metal thin film 300 is a metal catalyst etching process. It can only be prevented by etching with heavy HF solution.

In the example shown in the scheme, after deposition of gold (Au: 200) 10 nanometer, nickel (NiPt: 300) containing 5% platinum is deposited to a thickness of 10 nanometers. After removing the template 100 in a solution for removing the template 100 from the pattern structure 1000 in which the gold 200 and the nickel alloy 300 deposited on the AAO template 100 are stacked, a silicon substrate is used. Transfer the laminated structure.

Note that a substrate having a structure of a silicon on insulator (SOI) may be applied instead as a substitute for the silicon substrate.

FIG. 2 is a schematic diagram of a method of directly hole-patterning a silicon substrate using a lithography process without transferring the laminated mesh structure as shown in FIG. 1.

The photoresist (PR) is arranged as shown in FIG. 2 to pattern holes on the silicon substrate using a (photo) lithography process.

That is, the pattern structure 1000 includes a pattern including at least one hole by patterning through photohot-lithography, Aanodic Aluminum Oxide, or Block Copolmyer template processes.

The pattern structure 1000 may be transformed into a vertical nanotube and a vertical nanowall structure as the pattern structure 1000 includes other patterns patterned in a ring shape or a line shape in addition to a pattern including a hole.

In addition, instead of the lithography process, a patterning method using a polymer or a block copolymer having a characteristic of being arranged at regular intervals may be patterned as shown in FIG. 2.

For example, the nickel alloy 300 containing gold 200 and platinum is deposited on the patterned substrate by 10 nanometers. The photoresist (PR) material 110 that acts as a masking is removed from the substrate on which the stacked structure is deposited, leaving only the stacked mesh structure.

The remaining laminated mesh structure can naturally form on top of the silicon substrate without the transfer process.

3 is a schematic diagram illustrating a process of fabricating a vertical silicon nanowire 400 using a metal catalyst etching method on a silicon substrate having a stacked mesh structure thereon.

Etching is performed using an aqueous solution of HF and H 2 O 2 , and the catalytic metal does not directly participate in the reaction and remains in the lower portion of the vertical silicon nanowire 400 during the etching process. It is easy to form an electrode.

In addition, by adjusting the ratio (concentration) of the etching aqueous solution and the time or temperature of etching, the etching rate and crystallographic orientation including the length of the silicon vertical silicon nanowire 400 may be adjusted.

Note that the vertical silicon nanowire 400 is made of a group III-V compound (GaAs, InP, etc.) or a group IV combination thereof (SiGe).

4 is a diagram illustrating a process of forming a silicide 500 between a silicon substrate and a metal material (NiPt) forming silicide through heat treatment in a stacked structure disposed under the fabricated vertical silicon nanowire 400.

The heat treatment temperature is a heat treatment in an inert gas argon atmosphere for 1 minute using the RTA equipment at a temperature of about 500 ° C. in which the deposited nickel is known to form silicide.

During the heat treatment, nickel contained in the nickel alloy (or silicide forming metal thin film: 300), which was located on the upper part of the laminated structure, was diffused between the larger particles, Au, and contacted the silicon substrate surface. As a result, a phase change between nickel and silicon occurs while in contact with the silicon substrate, and at the same time, silicide is formed. At this time, the resistance value between the silicon substrate and the catalyst metal thin film is lowered.

In other words, in the process in which the silicide (containing the nickel component: 500) is formed by the heat treatment process, the resistance value between the silicide forming metal thin film 200 and the silicon substrate is changed as well as the silicide according to the heat treatment temperature and the heat treatment time. The phase change of 500 will also be different.

FIG. 5 is a simple diagram of a usable example of the vertical silicon nanowire 400 array structure and the lower electrode fabricated through the process of FIGS. 1-4.

As a representative example, in the case of thermoelectric devices, vertical silicon nanowires 400 of different types (n-type, p-type) are used for each region, and the vertical silicon nanowires 400 arrays are connected in a zigzag form. Current route.

In this case, since a current flows through the nanowire lower electrode, it is a necessary structure.

In addition, as shown in the schematic of FIG. 5, by connecting the bottom electrode, the measurement equipment may be contacted at both ends of the top electrode, and thus the measurement may be easily performed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it should be understood that various changes and modifications will be apparent to those skilled in the art. Obviously, the invention is not limited to the embodiments described above. Accordingly, the scope of protection of the present invention should be construed according to the following claims, and all technical ideas which fall within the scope of equivalence by alteration, substitution, substitution and the like within the scope of the present invention, Range. In addition, it should be clarified that some configurations of the drawings are intended to explain the configuration more clearly and are provided in an exaggerated or reduced size than the actual configuration.

2000: Bottom electrode of vertical silicon nanowire
1000: pattern structure 100: template
110: photoresist 200: catalytic metal thin film (Au)
300: silicide forming metal thin film (NiPt)
400: vertical silicon nanowire 500: silicide

Claims (12)

(a) forming a pattern structure in which a catalyst metal thin film having a mesh shape on the silicon substrate and a silicide forming metal thin film are stacked on the catalyst metal thin film;
(b) fabricating vertical silicon nanowires on the silicon substrate by a metal catalyst etching process; And
(c) a method of forming a lower electrode using vertical silicon nanowires, wherein the silicide-forming metal thin film causes silicon reaction to form a silicide by a heat treatment process.
The method of claim 1,
The catalyst metal thin film or the silicide-forming metal thin film having the mesh form may include at least one of gold (Au), silver (Ag), and platinum (Pt), which are catalyst metals. Electrode formation method.
The method of claim 1,
The catalyst metal thin film or the silicide forming metal thin film having the mesh form may include at least one of titanium (Ti), cobalt (Co), nickel (Ni), and tungsten (W). Lower electrode forming method using.
The method of claim 3, wherein
As the titanium, cobalt, nickel or tungsten is redeposited or capped by a catalyst metal including gold (Au), silver (Ag) and platinum (Pt), the silicide-forming metal thin film is HF solution during the metal catalyst etching process. A method of forming a lower electrode using vertical silicon nanowires, which prevents etching by etching.
The method of claim 1,
In the metal catalyst etching process, the length of the vertical silicon nanowires is a lower electrode formation method using a vertical silicon nanowires, characterized in that the length of the etch aqueous solution mixed with HF solution and H 2 O 2 is adjusted.
The method of claim 1,
And forming the catalyst metal thin film and the silicide forming metal thin film on the pattern structure by a physical vapor deposition method or a chemical vapor deposition method.
The method of claim 1,
In the process of forming the silicide by the heat treatment process,
According to the heat treatment temperature and the heat treatment time, the contact resistance value between the silicide-forming metal thin film and the silicon substrate and the phase change of the silicide is characterized in that the lower electrode forming method using a vertical silicon nanowire.
A pattern structure including a catalyst metal thin film having a mesh shape on a silicon substrate and a pattern in which a silicide forming metal thin film is stacked on the catalyst metal thin film;
Vertical silicon nanowires fabricated on the silicon substrate through a metal catalyst etching process; And
A lower electrode having vertical silicon nanowires including silicide formed by causing a silicon reaction of the silicide-forming metal thin film through a heat treatment process.
The method of claim 8,
The vertical silicon nanowire is a lower electrode having a vertical silicon nanowire, characterized in that consisting of a group III-V compound (GaAs, InP) or group IV combination (SiGe).
The method of claim 8, wherein the silicon substrate,
A lower electrode having vertical silicon nanowires, characterized in that it has a structure of a silicon on insulator (SOI).
The method of claim 8, wherein the pattern structure,
The lower electrode having vertical silicon nanowires having a pattern including at least one hole by patterning through one of photolithography, AAO (anodic aluminum oxide), and block copolymer process. .
The method of claim 11, wherein the pattern structure,
A lower electrode having a vertical silicon nanowire, characterized in that it comprises a pattern comprising at least one of ring or line form.
KR1020120088457A 2012-08-13 2012-08-13 Bottom electrode using by vertical silcon nanowires and fabrication method of the same KR101354006B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019182186A1 (en) * 2018-03-23 2019-09-26 한국과학기술연구원 Vertical nanogap dielectrophoretic electrode, manufacturing method therefor, and particle capture and separation method using same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006228726A (en) 2005-02-15 2006-08-31 Samsung Sdi Co Ltd Method for forming carbon nanotube, and method for manufacturing field emission device using the same
KR20110024892A (en) * 2009-09-03 2011-03-09 한국표준과학연구원 Semiconductor nanowires array and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006228726A (en) 2005-02-15 2006-08-31 Samsung Sdi Co Ltd Method for forming carbon nanotube, and method for manufacturing field emission device using the same
KR20110024892A (en) * 2009-09-03 2011-03-09 한국표준과학연구원 Semiconductor nanowires array and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019182186A1 (en) * 2018-03-23 2019-09-26 한국과학기술연구원 Vertical nanogap dielectrophoretic electrode, manufacturing method therefor, and particle capture and separation method using same

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