KR101351389B1 - A display device and a method for driving the same - Google Patents

Abstract

The present invention relates to a display device capable of improving image quality by selecting and applying an FRC data pattern according to a gradation difference between image data of a previous frame and image data of a current frame. An image comparison unit for comparing the gray levels between the images; A lookup table storing a plurality of FRC data pattern sets including a plurality of FRC data patterns; And selecting one of a plurality of FRC data pattern sets stored in the lookup table according to a comparison result from the image comparator, and using the FRC data patterns included in the selected FRC data pattern set, an image of the current frame. A data processor for modulating data; Each FRC data pattern consists of a plurality of data elements having a first value or a second value; The number of data elements having a first value in the FRC data patterns included in the same FRC data pattern set increases at a predetermined rate according to the gray level, and the increase rate is different for each FRC data pattern set.

LCD, Frame Rate Control, Dithering

Description

A display device and a method for driving the same}

1 illustrates a display device according to an exemplary embodiment of the present invention.

2 to 4 are diagrams illustrating a set of FRC data patterns included in the signal controller of FIG. 1.

* Explanation of symbols on the main parts of the drawings

600: signal controller 601: data processor

602: lookup table 603: video comparison unit

400: Gate driver 500: Data driver

800: gray voltage generator 300: liquid crystal panel

The present invention relates to a display device, and more particularly, to a display device and a driving method thereof capable of improving image quality by selectively applying an FRC data pattern according to a gray level difference between image data of a previous frame and image data of a current frame.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix form and connected to a switching element such as a thin film transistor (TFT) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit forming a pixel together with a switching element connected thereto.

In such a liquid crystal display device, a voltage is applied to the two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation due to long-term application of an electric field in one direction to the liquid crystal layer, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row, or pixel.

In such a liquid crystal display, red, green, and blue image data are input from an external graphics source. The signal control unit of the liquid crystal display device processes the video data appropriately and then provides the data driver to a data driving unit made of a data driving IC. The data driver selects an analog gray voltage corresponding to the applied image data and applies it to the liquid crystal panel.

In general, it is ideal that the number of bits of the image data input to the signal controller and the number of bits that can be processed by the data driver are the same, but a data driver having a low processing capacity may be used to reduce the manufacturing cost of the liquid crystal display. For example, when the image data applied to the signal controller is 8 bits, the data driver for processing the 8 bits of image data is very expensive, and therefore, processing power lower than 8 bits, for example, 6 bits of image data is processed. Using the data driver lowers the unit cost of the product.

The proposed technique is frame rate control (FRC). Frame rate control is to reconstruct the image data generated by taking only the upper bits corresponding to the number of bits that can be processed by the data driver among the bits of the input image data in units of frames based on the lower bits.

To this end, the signal controller stores a correction value of the image data for each pixel according to the value of the lower bit in a lookup table or the like. The set of correction values corresponding to the basic pixel units of the frame rate control is called an FRC data pattern.

However, the conventional display device has a problem in that the image quality is deteriorated by always applying a constant FRC data pattern regardless of the gray level difference between the image data.

The present invention has been made to solve the above problems, to prepare a plurality of FRC patterns having data elements increasing at different rates, to compare the grayscale between the image data of the previous frame and the image data of the current frame, It is an object of the present invention to provide a display device and a driving method thereof that can improve image quality by modulating image data by applying one of the plurality of FRC patterns according to the comparison result.

According to an aspect of the present invention, there is provided a display device including an image comparison unit comparing a gray level of image data of a previous frame and a gray level between current frame image data; A lookup table storing a plurality of FRC data pattern sets including a plurality of FRC data patterns; And selecting one of a plurality of FRC data pattern sets stored in the lookup table according to a comparison result from the image comparator, and using the FRC data patterns included in the selected FRC data pattern set, an image of the current frame. A data processor for modulating data; Each FRC data pattern consists of a plurality of data elements having a first value or a second value; The number of data elements having a first value in the FRC data patterns included in the same FRC data pattern set increases at a predetermined rate according to the gray level, and the increase rate is different for each FRC data pattern set.
In addition, a display device according to the present invention for achieving the above object, the display unit having a plurality of pixels for displaying an image; A lookup table storing a plurality of FRC data pattern sets including a plurality of FRC data patterns; And among the plurality of FRC data pattern sets stored in the lookup table according to a position of each pixel, a frame period of pixels to display a current image, and a logic state of a lower n bit among bits of data to be supplied to each pixel. A data processor for selecting any one and modulating the image data of the current frame using the FRC data patterns included in the selected FRC data pattern set; Each FRC data pattern consists of a plurality of data elements having a first value or a second value; The number of data elements having a first value in the FRC data patterns included in the same FRC data pattern set increases at a predetermined rate according to the gray level, and the increase rate is different for each FRC data pattern set.
In addition, the driving method of the display device according to the present invention for achieving the above object comprises the steps of comparing the grayscale between the image data of the previous frame and the current frame image data; Selecting one of the plurality of FRC data pattern sets according to a comparison result from the image comparator; And modulating image data of a current frame by using FRC data patterns included in the selected FRC data pattern set; Each FRC data pattern consists of a plurality of data elements having a first value or a second value; The number of data elements having a first value in the FRC data patterns included in the same FRC data pattern set increases at a predetermined rate according to the gray level, and the increase rate is different for each FRC data pattern set.

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Hereinafter, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a display device according to an embodiment of the present invention.

As shown in FIG. 1, the display device according to the exemplary embodiment of the present invention includes a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm that cross each other. ), The gate driver 400 for driving the gate lines G1 to Gn, the data driver 500 for driving the data lines D1 to Dm, and the data driver 500. A gray voltage generator 800 for supplying the required gray voltage and a signal controller 600 for controlling the gate driver 400 and the data driver 500 are included.

 In the liquid crystal panel 300, pixel areas defined by a plurality of gate lines G1 to Gn and data lines D1 to Dm are formed, and pixels are formed in each pixel area.

The pixel is turned on according to a gate on signal from a gate line to switch a data voltage from the data line, a pixel electrode to receive a data voltage from the thin film transistor TFT, And a common electrode positioned to face the pixel electrode, and a liquid crystal layer disposed between the pixel electrode and the common electrode.

A liquid crystal capacitor Clc is formed by the pixel electrode, the common electrode, and the liquid crystal layer. The common electrode functions as a first electrode of the liquid crystal capacitor Clc, the pixel electrode functions as a second electrode of the liquid crystal capacitor Clc, and the liquid crystal layer is a dielectric of the liquid crystal capacitor Clc. Function as.

The storage capacitor Cst is formed by overlapping a separate signal line (common line) and the pixel electrode with an insulating layer therebetween. This signal line functions as a first electrode of the storage capacitor Cst, the pixel electrode functions as a second electrode of the storage capacitor Cst, and the insulating film serves as a dielectric of the storage capacitor Cst. .

Alternatively, the storage capacitor Cst may be formed at a portion where the front gate line and the pixel electrode overlap with the insulating layer interposed therebetween.

The gray voltage generator 800 generates a plurality of positive gray voltages and a plurality of negative gray voltages. A gray voltage having a value greater than the common voltage is called a positive gray voltage, and a gray voltage having a value smaller than the common voltage is called a negative gray voltage.

The gate driver 400 drives the gate lines G1 to Gn by supplying a gate signal including a gate on signal and a gate off signal to each gate line G1 to Gn.

The data driver 500 selects a gray voltage corresponding to the image data supplied through the signal controller 600 from the gray voltage generator 800, and supplies the selected gray voltage to each of the data lines D1 to Dn. do.

The signal controller 600 controls operations of the gate driver 400, the data driver 500, and the like, and includes an image comparator 603, a data processor 601, and a lookup table 602. The lookup table 602 stores a number of FRC data patterns necessary for frame rate control.

The signal controller 600 controls image data R, G, and B inputted from an external graphic controller (not shown), and a control signal for controlling the display thereof, for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync), main clock MCLK, and data enable signal DE are provided.

The image comparison unit 603 stores the previous frame image data, calculates a gray level difference between the average gray level of the stored previous frame image data and the average gray level of the current frame image data, and between the calculated gray level difference and the preset threshold gray level. Compare Then, the first or second control signal is output in accordance with the comparison result.

The data processor 601 adapts the image data R, G, and B to the operating conditions of the liquid crystal display based on the predetermined number of bits of the image data R, G, and B and the first or second control signals. Proper processing is performed to generate a gate control signal CONT1, a data control signal CONT2, and the like. The gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image data DAT are sent to the data driver 500. In this case, the data processor 601 selects one of the FRC data pattern sets from the lookup table 602 to process the image data, which selection depends on a control signal from the image comparator 603. .

The data processing of the signal controller 600 includes frame rate control using an FRC data pattern stored in the lookup table 602, which is a bit of data that can be processed by the data driver 500. If the number is smaller than the number of bits of the image data R, G, and B, only the upper bits of the number of bits that can be processed by the data driver 500 are selected, and the data represented by the remaining lower bits is a temporal and spatial average of these upper bits. It means to implement as. For example, if the number of bits of the image data (R, G, B) is 8 bits and the number of bits of data that the data driver 500 can process is 6 bits, the signal controller 600 generates the image data (R, G, B). Only the upper 6 bits of the bit of) are output. At this time, the lower two bits determine the spatial and temporal arrangement of the upper six bits of data and this pattern is an FRC data pattern stored in the lookup table 602. Such frame rate control will be described in detail later.

The gate control signal CONT1 is a vertical synchronization start signal STV for indicating the start of output of the gate-on voltage Von, a gate clock signal CPV for controlling the output timing of the gate-on voltage Von, and a gate-on. An output enable signal OE or the like that defines the duration of the voltage Von.

The data control signal CONT2 is a horizontal synchronization start signal STH indicating the start of input of the image data DAT, a load signal LOAD for applying a corresponding data voltage to the data lines D1 to Dm, and a common voltage Vcom. And the inversion signal RVS and the data clock signal HCLK for inverting the polarity of the data voltage with respect to (hereinafter, referred to as "polarity of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage").

The data driver 500 sequentially receives and shifts the image data DAT for one row of pixels according to the data control signal CONT2 from the signal controller 600, and the gray level from the gray voltage generator 800. The image data DAT is converted into a corresponding data voltage by selecting a gray scale voltage corresponding to each image data DAT among the voltages, and then applied to the data lines D1 to Dm.

The gate driver 400 applies a gate-on voltage Von to the gate lines G1 to Gn according to the gate control signal CONT1 from the signal controller 600, and is connected to the thin film transistors connected to the gate lines G1 to Gn. The TFT is turned on, and thus, the data voltage applied to the data lines D1 to Dm is applied to the corresponding pixel through the turned-on thin film transistor TFT.

The difference between the data voltage applied to the pixel and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage.

The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage, and the polarization of light passing through the liquid crystal layer changes accordingly. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the liquid crystal panel.

After one horizontal period (or "1H") (one period of the horizontal synchronization signal Hsync, the data enable signal DE, or the gate clock CPV), the data driver 500 and the gate driver 400 The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 to Gn during one frame to apply data voltages to all the pixels.

When one frame ends, the next frame starts, and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to the polarity of the previous frame ("frame" reversal"). In this case, the polarity of the data voltage flowing through one data line may be changed ("line inversion") or the polarity of the data voltage applied to one row may be different according to the characteristics of the inversion signal RVS within one frame (" Invert dots ").

In the present invention, a liquid crystal display device in which the dot inversion is applied will be described. However, this dot inversion is two dot inversion, and the polarities of the pixels are inverted in units of two rows. That is, if the pixels of two adjacent rows show positive polarity, the pixels of two adjacent rows show negative polarity.

Next, the frame rate control performed by the data processing unit 601 of the signal control unit 600 will be described with reference to FIGS. 2 to 4.

2 is a diagram illustrating an FRC data pattern set included in the signal controller of FIG. 1, FIG. 2 illustrates a first FRC data pattern set, and FIG. 3 illustrates a second FRC data pattern set.

The first and second FRC data pattern sets are stored in the look-up table 602 of the signal controller 600, and each of the FRC data patterns belonging to each FRC data pattern set is determined according to the lower 2-bit value of the image data and the frame number. It is decided. That is, for four consecutive frames, there are a total of 12 FRC data patterns, one for each of the lower two bit values for (01, 10, 11). The data pattern when the lower two bits are (00) is not specified.

As shown in FIG. 2 and FIG. 3, the basic unit of the spatial arrangement in each FRC data pattern is an 8 * 8 data matrix, which repeatedly applies the FRC data pattern using the corresponding 8 * 8 pixel matrix as a base unit. It means. The data element of each FRC data pattern has a value of "1" or "0". In the figure, data elements having a value of "0" are shown in white, and data elements having a value of "1" are hatched.

Looking at the FRC data patterns belonging to the first FRC data pattern set, it can be seen that the number of data elements having a value of "1" increases by eight whenever the gray level increases by one step.

For example, in the FRC data pattern for the image data having the lower bit "01" in the first frame, the total number of data elements having a value of "1" is 8, and the FRC data pattern for the image data having the lower bit 10 The total number of data elements having a value of "1" is 16, and the total number of data elements having a value of "1" is 24 in the FRC data pattern for image data having a lower bit of 11. In other words, it can be seen that each time the gray level increases from 01 to 11, the number of data elements having the value of "1" increases by eight.

Looking at each FRC data pattern belonging to the second FRC data pattern set, it can be seen that the number of data elements having a value of "1" increases by five when the gray level increases by one step.

For example, in the FRC data pattern for the image data having the lower bit "01" in the first frame, the total number of data elements having a value of "1" is 8, and the FRC data pattern for the image data having the lower bit 10 Has a total of 13 data elements having a value of "1" and a total of 18 data elements having a value of "1" in an FRC data pattern for video data having a lower bit of 11. In other words, it can be seen that each time the gray level increases from 01 to 11, the number of data elements having the value of "1" increases by five.

The signal controller 600 modulates the image data of the current frame by using the FRC data patterns in any one of the first and second FRC data pattern sets to modulate the image data of the current frame. .

In this case, the image comparison unit 603 of the signal controller 600 obtains a difference between the average gray level of the image data of the previous frame and the average gray level of the current frame image data, compares the difference between the gray level difference and the preset threshold gray level, According to the comparison result, the first or second control signal is output and supplied to the data processor 601.

That is, the image comparator 603 outputs a first control signal when the gray level difference is greater than the threshold gray level, and outputs a second control signal when the gray level difference is equal to or smaller than the threshold gray level.

Then, the data processor 601 selects one of the first FRC data pattern set and the second FRC data pattern set according to the first or second control signal, and uses the FRC data patterns in the selected FRC data pattern set. The image data of the current frame is modulated.

That is, the data processor 601 selects a first set of FRC data patterns when the first control signal is input (when the gradation difference is greater than the threshold gradation), and when the second control signal is input (the If the gray level difference is equal to or smaller than the threshold gray level, the second FRC data pattern set is selected. Then, image data of the current frame is modulated using FRC data patterns belonging to the selected FRC data pattern set as follows.

In detail, the data processor 601 may include a plurality of FRC data patterns for image data (R, G, B) of a certain pixel according to the value and frame number of the lower two bits of the image data (R, G, B). To select one of the plurality of FRC data patterns in the first or second FRC data pattern set, read the data value of the data element corresponding to the position of the pixel, and output the data value to the data driver 500 based thereon. Determine the image data DAT.

Specifically, when the data value of the selected position is "0", the data processing unit 601 determines the final gray level value determined by the upper six bits of the image data R, G, and B. However, when the data value stored at the corresponding position is "1", the data processing unit 601 determines the final gray level by adding "1" to the predetermined gray level value of the upper six bits. The signal controller 600 outputs 6-bit image data DAT corresponding to the final gray level to the data driver 500.

However, when the lower two bits of the image data R, G, and B are "00", the data processor 601 does not read the FRC data pattern stored in the lookup table 602, but immediately before the upper six bits of the image data control signal. The value of the gradation determined by the bit is determined as the final gradation.

Meanwhile, three or more FRC data pattern sets may be made.

To this end, the signal controller 600 sets a plurality of threshold gray levels having different sizes. Then, the difference between the gradation of the image data of the previous frame and the gradation of the image data of the current frame is compared, and it is determined to which threshold gradation this gradation difference is located. According to the determination result, one set of a plurality of preset FRC data pattern sets is selected, and the final gray scale of the image data is determined by applying the FRC data patterns in the selected set.

As described above, in the present invention, a plurality of FRC data pattern sets are set, one of the FRC data pattern sets is selected according to the gradation size between the image data of the previous frame and the image data of the current frame, and the FRC data in the selected set. Since the gray level of the image data is determined by applying the patterns, dithering optimized for the gray level of the image of the current frame can be performed. Therefore, the image quality is improved.

As shown in FIG. 4, the lookup table may further include a third FRC data pattern set.

This third FRC data pattern set includes FRC data patterns in which the number of data elements having a value of "1" increases irregularly.

For example, in the FRC data pattern of the image data having the lower bit 01 of FIG. 4, the total number of data elements having a value of "1" is eight, and the FRC data pattern of the image data having the lower bit 10 is "1". The total number of data elements having the value of "is 18, and the total number of data elements having the value of" 1 "is 27 in the FRC data pattern for the image data having the lower bit 11. In other words, the number of data elements having the value of "1" increases by 10 when the gray level increases from 01 to 10, and the number of data elements having the value of "1" when the gray level increases from 10 to 11 9 increase.

Further, in the third FRC data pattern set, the FRC data patterns for each frame number have different values of "1".

For example, among the FRC data patterns for the image data having the lower bit of FIG. 4, the FRC data pattern having the frame number of 1 has a total of 18 data elements having a value of "1", and the frame number is The FRC data pattern of 2 has a total of 16 data elements having a value of "1", and the FRC data pattern having a frame number of 3 has a total of 18 data elements having a value of "1" and a frame number. The FRC data pattern having a value of 4 has a total of 17 data elements having a value of "1".

A plurality of FRC data pattern sets in which the number of data elements is regularly increased may be input to the lookup table, or only FRC data pattern sets in which the number of data elements is irregularly increased as described above may be input.

On the other hand, the data processor 601 is configured according to the logic state of the lower n bits (n is a natural number) among the bits of the data to be supplied to each pixel, the frame period of the pixels to display the current image. One of a plurality of FRC data patterns from the storage unit may be selected, and the image data R, G, and B of the current frame may be modulated using the selected FRC data pattern. In the display unit 300, a plurality of pixels are arranged in a matrix form. The data processor 601 modulates image data R, G, and B of one frame, and different FRC data for each pixel. Apply a pattern set.

Specifically, the data processor 601 supplies data to one pixel through the FRC data pattern in the first FRC data pattern set, and other pixels through the FRC data pattern in the second FRC data pattern set. Modulated data can be supplied.

At this time, the data processing unit 601 sets any FRC data pattern according to the position of each pixel, the frame period of the pixels for which the current image is to be displayed, and the logical state of the lower n bits among the bits of each data to be supplied to each pixel. Information about whether or not to apply is stored.

Accordingly, the data processing unit 601 modulates each data corresponding to each image to be displayed by all pixels of the display unit for one frame period based on the information.

In other words, the data processor 601 is supplied with image data R, G, and B to be displayed in one frame period, and the image data R, G, and B of the one frame includes data for each pixel. do. The data processor 601 detects the position of the pixel to which each data is to be supplied, the logical state of the lower bits of the data, and the frame period for each data in the image data R, G, and B of this one frame. The FRC data pattern set to be applied to the corresponding pixel is determined according to the grasped result.

The lower n bits may be the two lower bits described above, and as described above, the lower bits may have a value of '00', '01', '10', or '11'.

When the data processor 601 operates as described above, the display device according to the present invention does not include the image comparator 603 described above. That is, image data R, G, and B from the graphic controller are directly input to the data processor 601.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

As described above, the display device according to the present invention has the following effects.

According to the present invention, a plurality of FRC patterns having data elements increasing at different ratios are prepared, the gray level between the image data of the previous frame and the image data of the current frame is compared, and among the plurality of FRC patterns according to the comparison result. The image quality can be improved by modulating the image data by applying one.

As described above, the display device according to the present invention has the following effects.

According to the present invention, a plurality of FRC patterns having data elements increasing at different ratios are prepared, the gray level between the image data of the previous frame and the image data of the current frame is compared, and among the plurality of FRC patterns according to the comparison result. The image quality can be improved by modulating the image data by applying one.

Claims (15)

An image comparison unit comparing the gray level of the image data of the previous frame with the gray level of the current frame image data; A lookup table storing a plurality of FRC data pattern sets including a plurality of FRC data patterns; And Select one of a plurality of FRC data pattern sets stored in the lookup table according to a comparison result from the image comparator, and use the FRC data patterns included in the selected FRC data pattern set to obtain image data of a current frame. A data processor for modulating; Each FRC data pattern consists of a plurality of data elements having a first value or a second value; The number of data elements having a first value in the FRC data patterns included in the same FRC data pattern set increases at a predetermined rate according to the gray level, and the increase rate is different for each FRC data pattern set. The method of claim 1, FRC data patterns belonging to different sets of FRC data patterns, A first FRC data pattern composed of a plurality of data elements having a first value or a second value and increasing in number by n (n is a natural number) according to the grayscale; And Comprising a second FRC data pattern consisting of a plurality of data elements having a first value or a second value and increasing the number of data elements having the first value by p (p is a natural number different from n) according to the gray level. Display device characterized in that. The method of claim 2, The image comparison unit compares the gradation of the image data of the previous frame with the gradation of the image data of the current frame, and outputs a first control signal when the difference between the gradations is smaller than a preset threshold gradation. 2 A display device characterized by outputting a control signal. The method of claim 3, wherein The data processor selects an FRC data pattern set to which the first FRC data pattern belongs according to a first control signal from the image comparator, and an FRC data pattern to which the second FRC data pattern belongs according to the second control signal. Display device characterized in that for selecting the collection box. The method of claim 2, Each time one gradation increases, the number of data elements having the first value of the first FRC data pattern increases by eight, and And the number of data elements having the first value of the second FRC data pattern increases by five each time one gradation increases. The method of claim 1, And each FRC data pattern has an 8 * 8 matrix. The method of claim 1, And a data driver configured to supply a data voltage corresponding to the modulated image data from the data processor to the display unit. A display unit having a plurality of pixels for displaying an image; A lookup table storing a plurality of FRC data pattern sets including a plurality of FRC data patterns; And Any one of a plurality of FRC data pattern sets stored in the lookup table according to the position of each pixel, the frame period of the pixels for which the current image is to be displayed, and the logical state of the lower n bits of the bits of data to be supplied to each pixel And a data processor for modulating the image data of the current frame using the FRC data patterns included in the selected FRC data pattern set; Each FRC data pattern consists of a plurality of data elements having a first value or a second value; The number of data elements having a first value in the FRC data patterns included in the same FRC data pattern set increases at a predetermined rate according to the gray level, and the increase rate is different for each FRC data pattern set. Comparing the gray level of the image data of the previous frame with the gray level of the current frame image data; Selecting one of the plurality of FRC data pattern sets according to a comparison result from the image comparator; And Modulating image data of a current frame using FRC data patterns included in the selected FRC data pattern set; Each FRC data pattern consists of a plurality of data elements having a first value or a second value; The number of data elements having a first value in the FRC data patterns included in the same FRC data pattern set increases at a predetermined rate according to the gray level, and the increase rate is different for each FRC data pattern set. . The method of claim 9, FRC data patterns belonging to different sets of FRC data patterns, A first FRC data pattern composed of a plurality of data elements having a first value or a second value and increasing in number by n (n is a natural number) according to the grayscale; And Comprising a second FRC data pattern consisting of a plurality of data elements having a first value or a second value and increasing the number of data elements having the first value by p (p is a natural number different from n) according to the gray level. Method of driving a display device characterized in that. 11. The method of claim 10, Selecting the FRC data pattern set, Comparing the gray level of the image data of the previous frame with the gray level of the image data of the current frame; And Selecting the FRC data pattern set to which the first FRC data pattern belongs if the difference between the gray levels is smaller than the preset threshold gray scale; and selecting the FRC data pattern set to which the second FRC data pattern belongs if the difference is greater than the threshold gray scale. Method of driving a display device, characterized in that. 11. The method of claim 10, Each time one gradation increases, the number of data elements having the first value of the first FRC data pattern increases by eight; And, And the number of data elements having the first value of the second FRC data pattern increases by five each time one gradation increases. The method of claim 9, Wherein each of the FRC data patterns has a form of an 8 * 8 matrix. The method of claim 9, And supplying a data voltage corresponding to the modulated image data to a display unit. delete

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