KR101349783B1 - Driving circuit for liquid crystal display device and method of dirving thereof - Google Patents

Abstract

The present invention discloses a driving circuit of a liquid crystal display device. More specifically, the present invention relates to a driving circuit for a liquid crystal display device and a method of driving the same, which implement the functions of the timing controller and the data driving circuit as one IC, and apply color temperature correction without increasing the size of a separate memory means and IC. will be.
The driving circuit for the liquid crystal display according to the exemplary embodiment of the present invention receives a timing signal and image data from an external system to generate a control signal, and collectively uses color coordinates by using preset correction values for all gray levels of the image data. And a timing controller to output the corrected image data, and a data driver to convert the corrected image data in response to the control signal into a data voltage of an analog waveform and output the converted image data to the liquid crystal panel.
Accordingly, the present invention omits the LUT memory section for the DGA in the integrated driving circuit IC, sets a register value for color coordinate correction in an existing register module, and collectively corrects each gray level of the input image data to provide a correction for the driving circuit IC. There is an effect that it is possible to provide a liquid crystal display device having a color temperature correction without increasing the size.

Description

Driving circuit for liquid crystal display device and driving method thereof {DRIVING CIRCUIT FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DIRVING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display device, and in particular, implements the functions of a timing controller and a data driving circuit as a single IC, but uses a memory unit and a driving circuit for applying a color temperature correction without increasing the size of the IC. And a driving method thereof.

Recently, various portable devices such as mobile phones and laptop computers, and information electronic devices that implement high resolution and high quality images such as HDTVs have been developed. The demand for display devices is gradually increasing. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

In particular, an active matrix liquid crystal display device using a thin film transistor as a switch element is suitable for displaying a dynamic image.

FIG. 1 is a block diagram showing a basic configuration of a conventional liquid crystal display device, and includes a liquid crystal panel 1 and various driving circuits 3 to 6.

In the liquid crystal panel 1, a plurality of gate lines GL and a plurality of data lines DL intersect in a matrix form on a substrate using glass, and form a plurality of pixel regions at intersections, and a thin film in each pixel region. The transistor T and the liquid crystal capacitor Clc are provided to display an image.

The driving circuits 3 to 6 include a timing control circuit 3, a gate driving circuit 4, and a data driving circuit 5. The timing control circuit 3 receives the image data and the timing signal applied from the external system 2 to generate the control signals of the gate and data driving circuits 4 and 5.

Here, the external system 2 and the timing control circuit 3 transmit and receive image data using a low voltage differential signal (LVDS) interface method or a TTL interface method.

The gate driving circuit 4 turns on / off the thin film transistors T arranged on the liquid crystal panel 10 in response to the gate control signal GCS input from the timing control circuit 3. Perform control. The gate driving circuit 4 outputs a gate driving signal to sequentially enable the gate wiring GL on the liquid crystal panel 1 by one horizontal synchronizing time, thereby enabling the gate driving signal on the liquid crystal panel 10. The thin film transistor T is sequentially driven every one horizontal period so that the data voltage supplied from the data driving circuit 5 is applied to the liquid crystal capacitor Clc connected to each of the thin film transistors T.

The data driving circuit 5 modulates the image data of the digital waveform into the data voltage of the analog waveform in response to the data control signal DCS input from the timing control circuit 3. Next, one modulated data voltage is supplied to the liquid crystal panel 1 through all the data lines DL every horizontal period to control the rotation angle of the liquid crystal molecules.

Such LCDs employ techniques such as frame rate control (FRC) and digital gamma algorithm (DGA) to improve image quality. In particular, DGA is a technique for compensating the luminance and color temperature variation of each grayscale, and sets the compensation values for all the grayscales in a nonvolatile memory such as an electrically erasable and programmable read only memory (EEPROM) that is provided separately. The control circuit 3 reads from the EEPROM, stores it in the form of a look-up table (LUT) 3a, and matches the input image data to display gray scales.

Therefore, the conventional liquid crystal display device has a separate external image compensating means 6 including the FRC 6a and the EEPROM 6b, and improves the image quality through the timing control circuit 3 and the LUT 3a. do.

2 is a diagram illustrating an example of an 8-bit LUT included in a timing control circuit using a DGA.

As shown in the figure, in the case of an 8-bit driving color liquid crystal display, the LUT memory unit maps 512 DGA correction values finely corrected by extending 1 bit for each of 256 gray levels. ) The setter repeatedly compares the input image data with the image displayed through the actual LCD to determine a DGA correction value mapped to a specific gray scale to have a desired color temperature.

Accordingly, the LUT memory unit must have a space capable of storing at least the correction values shown for each of the three primary colors of R, G, and B, and at least 393216 according to the RGB (3) X correction value (512) X gray level (256). bit, 6144 kbytes of storage is required.

However, recently, in a liquid crystal display, a timing control circuit and a data driving circuit are integrated into a single driving circuit IC. In the integrated driving circuit IC, an internal memory does not have a memory cell structure such as an SRAM in a manufacturing process. Flip-flop structure is applied.

This is because the SRAM method has a complicated design structure, and one or more transistors and a sense amplifier must be provided for one memory cell. The sense amplifier is expensive and its size is also LUT memory using flip-flops. Because it is similar to implementing a wealth, it is not applied to a low-capacity LUT memory part to reduce cost and simplify the design structure.

Therefore, in the DGA-applied liquid crystal display device, the above-described LUT memory part must be further embedded in the driving circuit IC in which the timing control circuit and the data driving circuit are integrated, which is a main cause of increasing the size of the driving circuit IC.

3 is a view schematically showing an example of an external structure of a conventional integrated driving circuit IC.

As shown in the drawing, the driving circuit IC 40 in which the timing control circuit and the data driving circuit are integrated has a plurality of pads PAD connected to an external system, a gate driving circuit, and a liquid crystal panel vertically and horizontally. An area L / A corresponding to a LUT memory unit implemented by a plurality of flip-flops is located in the region.

The LUT memory area L / A occupies about 170um in the y direction when the total length in the Y direction is 1480um in the integrated driving circuit IC.

As a result, the size of the wafer increases in the manufacture of the integrated driving circuit IC, and the number of pieces of the wafer is reduced, resulting in an increase in the manufacturing cost of the driving circuit IC.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the size of the driving circuit IC is increased by omitting the LUT storage space in the liquid crystal display device including the driving circuit IC in which the timing control circuit and the data driving circuit are integrated into one IC. It is an object of the present invention to provide a driving circuit for a liquid crystal display device and a driving method thereof, which perform color temperature correction without using the same.

In order to achieve the above object, the driving circuit for a liquid crystal display according to the preferred embodiment of the present invention receives a timing signal and image data from an external system and generates a control signal, and in advance for all gray levels of the image data. A timing controller configured to output image data in which color coordinates are collectively corrected using the set correction value; And a data driver converting the corrected image data into a data voltage of an analog waveform and outputting the corrected image data to a liquid crystal panel in response to the control signal.

The timing controller may include a control signal processor configured to generate the control signal in response to the timing signal; And an image data processing unit which performs a preprocessing process of expanding a bit value according to whether color coordinates of the image data are corrected, and corrects the image data using the correction value.

The image data processor may include: a preprocessing module configured to add lower 2 bits when the input image data is 6 bits, and output original image data when 8 bits; A calculation module for generating the corrected image data by subtracting the correction value from the image data output from the preprocessing module; And a register module for storing the correction value.

The preprocessing module may add 0x00 bits for the lowest grayscale (0 gray) of the 6-bit image data and add 0x11 bits for the remaining grayscales (1 gray to 63 gray).

The correction value is characterized in that the data of three bits for each of the three primary colors (RGB).

The register module further stores a 1-bit DGA identification value for determining whether to correct color coordinates.

In order to achieve the above object, a driving method of a driving circuit for a liquid crystal display device according to an embodiment of the present invention, the step of receiving a timing signal and image data from an external system; Generating a control signal in response to the timing signal, and outputting image data in which color coordinates are collectively corrected using preset correction values for all gray levels of the image data; And converting the output corrected image data into a data voltage of an analog waveform in response to the control signal and outputting the converted data voltage to a liquid crystal panel.

The outputting of the corrected image data may include: adding lower 2 bits when the image data is 6 bits, and outputting original image data when the image data is 6 bits according to a result of the determination of correction; And generating the corrected image data by subtracting the correction value from the output image data.

According to the determination result of the correction, the step of adding the lower 2 bits when the image data is 6 bits, and outputting the original image data when 8 bits, the lowest gray level (0 gray) of the 6-bit image data Adding a value of 0x00; And adding 0x11 values to the remaining gray levels (1 gray to 63 gray).

The correction value is characterized in that the data of three bits for each of the three primary colors (RGB).

According to a preferred embodiment of the present invention, by omitting the LUT memory unit for the DGA in the integrated driving circuit IC, by setting a register value for color coordinate correction in the existing register module to collectively correct each gray level of the input image data. It is possible to provide a liquid crystal display device which performs color temperature correction without increasing the size of the driving circuit IC.

1 is a block diagram showing a basic configuration of a conventional liquid crystal display device.
2 is a diagram illustrating an example of an 8-bit LUT included in a timing control circuit using a DGA.
3 is a view schematically showing an example of an external structure of a conventional integrated driving circuit IC.
4 is a diagram illustrating a configuration of a liquid crystal display device including a driving circuit according to an exemplary embodiment of the present invention.
5 is a diagram illustrating a structure of an integrated driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.
6A and 6B illustrate an example of a method of correcting image data according to an embodiment of the present invention.
7 is a diagram illustrating an example of a data storage structure of a register module according to an embodiment of the present invention.
8 is a view illustrating a driving method of a driving circuit for a liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, a driving circuit for a liquid crystal display device and a driving method thereof according to a preferred embodiment of the present invention will be described with reference to the drawings.

4 is a diagram illustrating a configuration of a liquid crystal display device including a driving circuit according to an exemplary embodiment of the present invention.

As illustrated, the liquid crystal display device of the present invention includes a liquid crystal panel 100 for displaying an image, a gate driving circuit 140 for driving the liquid crystal panel 100, and an integrated driving circuit 160.

In the liquid crystal panel 100, a plurality of gate lines GL and a plurality of data lines DL intersect in a matrix form on a substrate using glass, and define a plurality of pixel regions at intersections. Each pixel area includes a thin film transistor T and a liquid crystal capacitor Clc to implement an image.

The driving circuit 160 receives timing signals and image data from an external system through the built-in timing controller 130 to generate control signals of the gate driving circuit 140 and the embedded data driver 150, and generates digital image data. Is converted into a data voltage of an analog waveform corresponding to the gray level of the image.

In detail, the timing controller 130 is mounted in the driving circuit 160 to transmit image data RGB data, a clock signal DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, A timing signal such as a data enable signal DE is applied to generate control signals of the gate driver circuit 140 and the data driver 150.

Here, the horizontal synchronization signal Hsync represents the time taken to display one horizontal line of the screen, and the vertical synchronization signal Vsync represents the time taken to display the screen of one frame. In addition, the data enable signal DE indicates a period in which a data voltage is supplied to a pixel defined in the liquid crystal panel 100.

In addition, the timing controller 130 generates a gate driving circuit 140 and a control signal for driving the data driver 150 in synchronization with the input timing control signal, and provides a gate control to the gate driving circuit 140. The signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like.

The gate start pulse GSP described above is applied to a shift register (not shown) of the gate driving circuit 140 as a signal for determining when to output a gate driving signal to the first gate wiring GL. The gate shift clock GSC is a clock signal commonly applied to each shift register, and the next shift register is activated in synchronization with the gate shift clock GSC. The gate output enable signal GOE is a signal for controlling the output of the shift register.

In addition, the timing controller 130 generates a control signal DCS of the data driver 150, and the data control signal DCS includes a source start pulse SSP and a source shift clock SSC. ) And Source Output Enable (SOE).

The source start pulse SSP is a signal that determines the sampling timing of the image data of the data driver 150. The source shift clock SSC is a clock signal that controls the data sampling operation in the data driver 150. In addition, the source output enable signal SOE is a signal for controlling the output of the data driver 150.

In addition, the timing controller 130 according to an embodiment of the present invention receives the image data RGB DATA through a normal interface method, and the data driver 150 processes the input image data RGB DATA. The output will be sorted. Here, the aligned image data RGB DATA 'is modulated by applying a color coordinate correction algorithm for improving image quality and is collectively changed according to the size of the image data and output to the data driver 150.

The above-described color coordinate correction algorithm is a method of modulating the gray scale values by applying the correction values set in the register module (not shown) built in the timing controller 130 to all the gray scales. Therefore, unlike the conventional DGA method, there is no internal LUT memory unit, and a separate EEPROM for storing calibration related data may be omitted. The image data correction method applying the color coordinate correction algorithm and the structure of the register module will be described in detail later.

At least one gate driving circuit 140 is provided at one end of the liquid crystal panel 100 and includes a plurality of shift registers. The gate driving circuit 140 may be implemented as a separate gate driving circuit IC and connected to the liquid crystal panel 100 or may be formed in a thin film pattern on a first substrate of the liquid crystal panel 100.

The gate driving circuit 140 may include a gate driving signal VG which has been moved for one horizontal period through the gate wiring GL formed on the liquid crystal panel 100 in response to the gate control signal GCS input from the timing controller 130. ) Accordingly, the thin film transistor T connected to the corresponding gate wiring GL is turned on, and at the same time, the data voltage of the analog waveform supplied from the data driving circuit 140 is transferred through the data wiring DL. It is applied to the pixels connected to the thin film transistor (T).

The data driver 150 sorts the digital image data RGB DATA input in response to the data control signal DCS input from the timing controller 130, and selectively converts the analog image data according to the reference voltage Vref. Convert to data voltage VD. The data voltage VD is latched by one horizontal line and input to the liquid crystal panel 100 simultaneously through all the data lines DL during one horizontal period.

According to the above-described structure, the LCD including the integrated driving circuit according to the embodiment of the present invention implements the timing controller 130 and the data driver 140 as one IC, but omits the LUT memory unit and the existing register. By using the module to correct the color coordinates, the size of the driving circuit IC can be minimized, thereby reducing the manufacturing cost. Hereinafter, a structure of a timing controller according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a diagram illustrating a structure of an integrated driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown, the driving circuit 130 for the liquid crystal display device of the present invention includes a control signal processor 132 for generating gate and data control signals GCS and DCS, and an image data processor for modulating the image data RGB DATA. 134.

The control signal processor 132 may include a gate driver circuit and a data driver in response to timing signals such as the vertical and horizontal synchronization signals Vsync and Hsync, the data enable signal DE, and the clock signal DCLK input from an external system. Generate and output control signals DCS and GCS to control operation timing.

The image data processor 134 receives the image data RGB DATA, and outputs the corrected image data RGB DATA 'by being aligned and corrected. In particular, the timing controller 130 preprocesses each gray value of the digital image data (RGB DATA) in order to improve the image quality according to the color temperature, and collectively corrects the gray value through the correction value stored in the register module. And then output to the data driver.

To this end, the image data processing unit 134 includes a preprocessing module 1341 for modulating the input image data into a correctable form, a calculation module 1343 for correcting a gray value through a difference operation, and correcting the preprocessed image data; It consists of a register module 1347 in which a value is set.

In detail, the preprocessing module 1341 is for processing data appropriately according to bit values of video data set differently for each external system. The image data may be input in a size of 6 bits or 8 bits, and when the 6 bit image data is input, the preprocessing module 1341 expands and modulates 8 bits by adding lower 0x11 data. At this time, when the grayscale value is 0 (0 gray), 0x00 data is added. In addition, when 8-bit image data is input, the preprocessing module 1341 provides the operation module 1343 with the original data without adding bits.

The calculation module 1343 differentially calculates a preset correction value with respect to the preprocessed image data, and outputs the value to the data driver (not shown) as the compensated image data RGB DATA '. Here, the correction value is stored for each color (RGB) in the register module 1347, which will be described later, and the calculation module 1343 corrects the data with different correction values for each gray level of each image data with reference to the register module 1347. The image data is corrected by subtracting the correction value for all the gradations at once.

The register module 1347 is not provided separately, but utilizes a register storage area embedded in a conventional timing controller to store data related to control of the liquid crystal display. According to an embodiment of the present invention, the register module 1347 secures a correction value storage area of 3 bits for each of the three primary colors RGB, and provides the stored setting values at the request of the operation module 1343.

Hereinafter, an image data correction method by the image data processor described above will be described with reference to the accompanying drawings.

6A and 6B illustrate an example of a method of correcting image data according to an embodiment of the present invention.

Referring to FIG. 6A, FIG. 6A illustrates a correction method for 6-bit image data. When 6-bit image data of 0x000000 to 0x111111 corresponding to 0 to 63 gray levels (64 gray) is input from an external system (a1 ), The preprocessing module adds the lower 2 bits of data and expands and modulates the data into 8 bits. In this case, except for data corresponding to zero grayscale (0 gray), 0x11 bits are collectively added, and 0x00 bits are added to zero grayscale (0 gray) data. This is because when 0x11 bits are added to the lowest gray level, 0x00000000 bits are lost, and gray scale expression for full-white or full-black is impossible.

According to the above-described extended modulation on the image data, as an example, 0x111101, which is 61 gray (61 gray) data before modulation, is extended modulated to 0x11110111 according to the addition of two bits of data (a2).

Next, the calculation module performs a difference operation on the modulated image data with reference to the correction value set in the register module to correct the bit value. As an example, when the correction value stored in the register module is 0x111, 0x111 is subtracted from the bit values of all image data. Therefore, data 0x11110111 of the expanded 61 gray levels (61 gray) is corrected to 0x11110000 (a3).

6B illustrates a correction method for 8-bit image data. When 8-bit image data of 0x00000000 to 0x11111111 corresponding to 0 to 63 gray levels (64 gray) is input from an external system (b1), the preprocessing module Determines the bit size and inputs 0x11110110, which is the original image data, into the operation module without expansion modulation.

Next, the calculation module performs a difference operation on the modulated image data with reference to the correction value set in the register module to correct the bit value. This is the same process as the 6-bit image data correction described above. When the correction value stored in the register module is 0x010, 0x010 is subtracted from the bit values of all the image data. Therefore, 0x11110110, which is the original data value of 61 gray levels (61 gray), is corrected to 0x11111011 (b2).

The corrected image data is input to the data driver to convert the data voltage and provided to the liquid crystal panel to display the gray scale. The setter can find the desired gamma curve by repeatedly changing the correction value until the color coordinate is optimized for the gamma curve. Will be.

According to the data correction of the lower 3 bits, color coordinate change of up to 8/1000 level is possible.

7 is a diagram illustrating an example of a data storage structure of a register module according to an embodiment of the present invention.

As shown in the figure, in the register module included in the driving circuit of the liquid crystal display device of the present invention, basic control data for the timing controller is set, and a storage area for image data correction is allocated.

The correction value set in the register module is a value subtracted from the lower 3 bits for each of the three primary colors (RGB), and the magnitude thereof is 3 bits of the correction values (GGM [0] to GGM [2]) for green data, 3 bits of correction value (RGM [0] ~ RGM [2]) for red data and 3 bits of correction value (BGM [0] ~ BGM [2]) for blue, and DGA setting value for identification of correction One bit, a total of 10 bits may be allocated to the storage area of the register.

Therefore, the driving circuit for the liquid crystal display according to the exemplary embodiment of the present invention performs color coordinate correction using only the 10-bit storage region instead of the LUT memory unit which occupies the conventional 6144 kbyte storage region.

Hereinafter, a driving method of a driving circuit for a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the drawings.

8 is a view illustrating a driving method of a driving circuit for a liquid crystal display according to an exemplary embodiment of the present invention.

As shown, the driving method of the driving circuit according to an embodiment of the present invention is the image data receiving step (S100), data preprocessing step (S110), image data correction step (S130), and image data output step (S140) Is done.

The image data receiving step S100 is a step in which a timing controller of the integrated driving circuit receives 6-bit or 8-bit image data from an external system. At this time, one bit DGA identification value is preset in the register module. If the DGA identification value stored in the register module is 0 (DGA = 0), the original image is not corrected. Data is input to the data driver as it is, and when the DGA identification value is 0x1 (DGA = 1), preprocessing of the image data is performed.

The data preprocessing step (S110) is a step of suitably modulating the size of the image data to perform color coordinate correction. The image data may be input in a size of 6 bits or 8 bits, and the preprocessing module determines the bit size of the image data, and when 6 bit image data is input, adds lower 0x11 data and modulates the bit into 8 bits (S115). At this time, when the grayscale value is 0 (0 gray), 0x00 data is added. In addition, when 8-bit image data is input, the image data correction step is performed as it is without adding bits.

The image data correction step (S130) is a step of correcting a bit value by collectively performing a difference operation on the modulated image data with reference to the correction value set in the register module. Here, when the bit value of the original video data is smaller than the correction value, it is calculated as 0x00000000 instead of the negative value.

The image data output step S140 is a step of outputting the original image data that has not been subjected to the above-described DGA color coordinate correction or the image data corrected by the step S130 to the data driver. Accordingly, the data driver receives the corrected image data from the timing controller, converts the image data into an analog data voltage, and provides the data voltage to the liquid crystal panel. The liquid crystal panel displays the gray level of the image in response to the data voltage.

In addition, the setter identifies the gradation of the displayed image to determine whether additional color coordinates are corrected, resets the correction value, and corrects the image data again, or completes the color coordinates correction.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100: liquid crystal panel 120: external system
130: timing controller 140: gate driving circuit
150: data driver 160: integrated drive circuit

Claims (10)

Generates control signals by receiving timing signals and image data from an external system, and collectively corrects color coordinates using correction values, which are 3-bit data for each of the three primary colors (RGB), pre-set for all gray levels of the image data. A timing controller for outputting one image data; And
A data driver converting the corrected image data into a data voltage of an analog waveform and outputting the corrected image data to a liquid crystal panel in response to the control signal;
Wherein the timing control unit comprises:
A preprocessing step of expanding a bit value according to whether color coordinates of the image data are corrected, and an image data processing unit correcting the image data using the correction value stored in a register module;
The timing controller and the data driver are implemented as a single driving circuit IC
A driving circuit for a liquid crystal display device, characterized in that. delete The method of claim 1,
Wherein the image data processing unit comprises:
A preprocessing module for adding lower 2 bits when the input image data is 6 bits and outputting original image data when 8 bits; And
A calculation module for generating the corrected image data by subtracting the correction value from the image data output from the preprocessing module
Driving circuit for a liquid crystal display device comprising a. The method of claim 3, wherein
The pretreatment module,
Add 0x00 bits for the lowest gray level (0 gray) of 6-bit image data,
A driving circuit for a liquid crystal display device, which adds 0x11 bits to the remaining gray levels (1 gray to 63 gray). delete The method of claim 3, wherein
And the register module further stores a 1-bit DGA identification value for determining whether to correct color coordinates. In a driving method of a driving circuit for a liquid crystal display device in which the timing controller and the data driver are implemented by one driving circuit IC,
Receiving timing signals and image data from an external system;
An image in which a control signal is generated in response to the timing signal, and color coordinates are collectively corrected using correction values, which are 3-bit data for each of the three primary colors (RGB) preset in the register module, for all gray levels of the image data. Outputting data; And
Converting the output corrected image data into a data voltage of an analog waveform in response to the control signal and outputting the data to a liquid crystal panel;
Method of driving a driving circuit for a liquid crystal display device comprising a. The method of claim 7, wherein
Wherein the outputting of the corrected image data comprises:
If the image data is 6 bits, adding the lower 2 bits, and outputting the original image data if 8 bits; And
Generating the corrected image data by subtracting the correction value from the output image data.
Method of driving a driving circuit for a liquid crystal display device comprising a. The method of claim 8,
According to the result of the determination of the correction, the step of adding the lower 2 bits when the image data is 6 bits, and outputting the original image data when 8 bits,
Adding a value of 0x00 to a lowest gray level (0 gray) of 6-bit image data; And
Adding 0x11 values for the remaining tones (1 gray to 63 gray)
A driving method of a driving circuit for a liquid crystal display device, characterized in that. delete

Images