KR101348169B1 - Method of manufacturing fet using graphene - Google Patents
Method of manufacturing fet using graphene Download PDFInfo
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- KR101348169B1 KR101348169B1 KR1020120074437A KR20120074437A KR101348169B1 KR 101348169 B1 KR101348169 B1 KR 101348169B1 KR 1020120074437 A KR1020120074437 A KR 1020120074437A KR 20120074437 A KR20120074437 A KR 20120074437A KR 101348169 B1 KR101348169 B1 KR 101348169B1
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- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 307
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 306
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims description 55
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 49
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 49
- 238000000802 evaporation-induced self-assembly Methods 0.000 claims description 17
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 7
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 7
- 238000009832 plasma treatment Methods 0.000 claims description 6
- -1 polyethylene terephthalate Polymers 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 4
- 239000003960 organic solvent Substances 0.000 claims description 4
- 239000002904 solvent Substances 0.000 claims description 4
- GKWLILHTTGWKLQ-UHFFFAOYSA-N 2,3-dihydrothieno[3,4-b][1,4]dioxine Chemical compound O1CCOC2=CSC=C21 GKWLILHTTGWKLQ-UHFFFAOYSA-N 0.000 claims description 3
- 239000010954 inorganic particle Substances 0.000 claims description 3
- 239000002923 metal particle Substances 0.000 claims description 3
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 claims 2
- 239000002245 particle Substances 0.000 claims 1
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- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
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- 238000001459 lithography Methods 0.000 description 4
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- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- 229920000144 PEDOT:PSS Polymers 0.000 description 1
- 229920003171 Poly (ethylene oxide) Polymers 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000002717 carbon nanostructure Substances 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 229920001467 poly(styrenesulfonates) Polymers 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
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- 229960002796 polystyrene sulfonate Drugs 0.000 description 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02628—Liquid deposition using solutions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1606—Graphene
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Carbon And Carbon Compounds (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
The present invention relates to a method for manufacturing a FET using graphene, and more particularly, to a method for manufacturing a FET using graphene, which can be easily formed by a simpler method.
Recently, graphene, a new form of two-dimensional carbon nanostructure, has been studied with great interest due to its unique optoelectronic properties and potential application to electronic devices. In recent years, a major concern in applying graphene to electronic devices is to mass produce graphene in large areas and to effectively obtain graphene patterns having desired structures.
A promising method for producing large-area graphene films is by chemical vapor deposition (CVD), for use in various electronic devices such as transparent conductive films, sensors, field effect transistors (FETs), and the like. Development of CVD-grown graphene has been in progress.
However, in order to implement graphene in an electronic device, development of a patterning method for manufacturing a large area graphene film is required. The graphene pattern is obtained through the growth of graphene or patterning of the catalytic metal film before direct patterning after growth. Although lithography has been widely used to form graphene patterns for electronic devices, there are problems such as low yields such as many process steps required, and difficulty in manufacturing large areas.
Therefore, it is possible to easily form a graphene pattern in a simpler method, to reduce the manufacturing cost, and to develop a method for producing a graphene pattern, which is advantageous for manufacturing a large area graphene pattern.
In addition, there is a demand for the development of a method that can be implemented and produced in the manufacture of various devices, such as FETs used in electronic devices.
Accordingly, the problem to be solved by the present invention is that the graphene pattern can be easily formed by a simpler method, and the manufacturing cost can be reduced, and the graphene to which the graphene pattern manufacturing method is applied is advantageous for the production of a large area graphene pattern. It is to provide a method for manufacturing a FET using.
In order to manufacture a field effect transistor (FET) using graphene according to an exemplary embodiment of the present invention, graphene is first formed on a substrate. Subsequently, a pattern forming jig is disposed on the graphene formed substrate. Next, a solution is supplied onto the graphene formed substrate. Subsequently, the pattern forming jig is transferred to cause an EISA (Evaporation-Induced Self Assembly) phenomenon in the solution to form a first solute pattern on the graphene. Next, a first graphene pattern is formed corresponding to the first solute pattern. Subsequently, a second graphene pattern is formed to cross the first graphene pattern. Next, a dielectric layer is formed on the second graphene pattern so as to connect two adjacent portions that intersect the first graphene pattern and neighbor each other. Subsequently, a gate electrode is formed on the dielectric layer.
In an embodiment, the forming of the first graphene pattern corresponding to the first solute pattern may include removing the remaining graphene except for the graphene corresponding to the first solute pattern and the remaining graphene. And removing the remaining solute corresponding to the. At this time, the exposed graphene to be removed is removed by a plasma treatment, the residual solute corresponding to the remaining graphene can be removed by an organic solvent (solvent).
In an embodiment, the forming of the second graphene pattern to cross the first graphene pattern may include forming graphene on the substrate on which the first graphene pattern is formed, the first graphene pattern and Disposing a pattern forming jig so as to intersect the first graphene pattern on the graphene-formed substrate, supplying a solution on the first graphene pattern and the substrate on which the graphene is formed, and the EISA phenomenon in the solution Transferring the pattern forming jig so as to cross the first graphene pattern to form a second solute pattern on the graphene and forming a second graphene pattern corresponding to the second solute pattern; It may include. The forming of the second graphene pattern corresponding to the second solute pattern may include removing the remaining graphene except for the graphene corresponding to the second solute pattern and corresponding to the remaining graphene. Removing residual solutes. In addition, in the step of removing the remaining graphene except for the graphene corresponding to the second solute pattern, portions of the first graphene pattern that do not correspond to the second solute pattern may be simultaneously removed. Portions of the first graphene pattern that are intersected by the second graphene pattern may be left, and the first graphene pattern left below the second graphene pattern may be alternately positioned.
For example, the dielectric layer may include an ion-gel, and the dielectric layer may be formed on the second graphene pattern by ion gel printing. For example, the gate electrode may include poly 3,4-ethylenedioxythiophene (PEDOT), and the gate electrode may be formed on the dielectric layer by PEDOT printing.
In one embodiment, the concentration of the solution may be adjusted before supplying the solution on the graphene-formed substrate.
In an embodiment, when the pattern forming jig is transferred to form a first solute pattern on the graphene, the feeding speed of the pattern forming jig may be adjusted to control the shape of the first graphene pattern.
In one embodiment, the pattern forming jig may include a cylindrical roller, and when the pattern forming jig is transferred to form a first solute pattern on the graphene, the first solute pattern is formed on the cylindrical roller. It can be formed by rotating the cylindrical roller by a conveying plate disposed. For example, irregularities may be formed in the cylindrical roller.
In another embodiment, the pattern forming jig may have a plate shape, and the pattern forming jig may be transferred by linear movement to form a first solute pattern on the graphene.
For example, the solute may include at least one of polymethyl methacrylate (PMMA), metal particles, and inorganic particles, and the substrate may include at least one of polyethylene terephthalate (PET) and SiO 2 / Si. .
In an embodiment, the step of forming the graphene on the substrate to the step of forming the first graphene pattern corresponding to the first solute pattern may be repeatedly performed at least two or more times to at least two or more first graphenes. Patterns can be formed.
According to the present invention, by supplying a solution on the graphene-formed substrate and transferring the pattern forming jig to generate an EISA phenomenon and by forming a graphene pattern corresponding to the solute pattern obtained therefrom in at least two or more patterns to cross each other In addition, it is possible to easily form a FET using a graphene pattern, which can be manufactured only through a complicated process such as a conventional lithography process, in a simpler manner, thereby greatly reducing the manufacturing cost of the FET.
In addition, since the graphene pattern to be manufactured is formed very uniformly, a high quality graphene pattern can be obtained, and in the case of manufacturing a large-area FET using a large-area graphene pattern, the same method is applied as it is in addition to the enlargement of the target substrate. This makes it possible to manufacture high quality large area FETs more easily and at low cost.
1 is a flowchart illustrating a method of manufacturing a graphene pattern according to an embodiment of the present invention.
2 to 4 are perspective views illustrating a graphene pattern manufacturing method and a graphene pattern manufacturing apparatus according to an embodiment of the present invention.
5 is a side view illustrating a process of forming a solute pattern by transferring the pattern forming jig of FIG. 1.
6 is a conceptual diagram illustrating an EISA phenomenon in the step of forming the solute pattern of FIG. 1.
7 to 10 are images showing graphene patterns formed according to the method for manufacturing a graphene pattern according to FIGS. 1 to 5.
11 is a flowchart illustrating a method of manufacturing a FET according to an embodiment of the present invention.
12 is a flowchart illustrating a process of forming the second graphene pattern of FIG. 11 in detail.
13 to 15 are perspective views illustrating a process of forming the second graphene pattern of FIG. 12.
16 to 18 are perspective views illustrating a process of forming the dielectric layer and the gate electrode of FIG. 11.
19 is a cross-sectional view illustrating a FET formed by an embodiment of the present invention.
The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.
The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprising" or "having ", and the like, are intended to specify the presence of stated features, integers, steps, operations, elements, parts, or combinations thereof, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.
Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted as ideal or overly formal in meaning unless explicitly defined in the present application Do not.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
1 is a flow chart showing a method for manufacturing a graphene pattern according to an embodiment of the present invention, Figures 2 to 4 are graphene pattern manufacturing method and graphene pattern manufacturing apparatus according to an embodiment of the present invention 5 is a side view illustrating a process of forming a solute pattern by transferring the pattern forming jig of FIG. 1.
1 to 5, the graphene
In order to manufacture a graphene pattern according to an exemplary embodiment of the present invention, first, graphene (G) is formed on the substrate 10 (S110).
For example, the
Alternatively, the
The graphene (G) may be formed as a single layer, and may be grown on a copper foil using a chemical vapor deposition (CVD) method.
As a specific example, a copper foil is loaded into a quartz tube of a CVD system, flowed with H2 for a predetermined time and then heat treated to expand the single-crystal sized copper foil. Growth is initiated, for example, by a CH4: H2 reaction gas mixture, flowing H2 and quenching to room temperature. In order to transfer the graphene films to a polymer film (or Si / SiO 2 wafer) such as PET, which becomes the
Subsequently, a pattern formation jig is disposed on the
The pattern forming jig may include a
Alternatively, the pattern forming jig may have a flat plate shape. The plate-shaped pattern forming jig may be transferred while linearly moving by a jig transfer unit to be described later.
Next, a solution (STN) is supplied onto the
For example, the solution (STN) may be a polymer solution in which a polymer material is dissolved as a solute (STE). For example, the solute (STE) may include polymethyl methacrylate (PMMA), and the solution (STN) may be a PMMA solution in which PMMA is dissolved using toluene as a solvent. In addition, the solute may be a mixture of at least one of metal particles and inorganic particles in PMMA (polymethyl methacrylate).
In one embodiment, the graphene pattern manufacturing apparatus may further include a concentration control unit for adjusting the concentration of the solution supplied by the solution supply. Before supplying the solution STN onto the
According to the concentration of the solution STN, the shape of the graphene pattern GP described later may be adjusted.
Subsequently, the pattern forming jig is transferred to cause an EISA (Evaporation-Induced Self Assembly) phenomenon in the solution (STN) to form a solute pattern on the graphene (G) (S140). For example, when the solute (STE) is PMMA, the pattern forming jig may be transferred to form the PMMA pattern (PP) on the graphene (G).
The jig transfer unit transfers the pattern forming jig so that the solute pattern is formed by the EISA phenomenon of the solution. In one embodiment, when the pattern forming jig is a
6 is a conceptual diagram illustrating an EISA phenomenon in the step of forming the solute pattern of FIG. 1.
Referring to FIG. 6, for example, a PMMA solution is supplied between a roller-shaped pattern forming jig disposed above and a
When the roller is rotated clockwise and transported to the right, a sticking force for the PMMA solution injected between the substrate and the roller to adhere to the substrate and the lower part of the roller, and the liquid level of the PMMA solution The capillary force to concave is applied and evaporation of the solvent is caused. As the roller is transported, the sticking force of the PMMA solution becomes relatively larger than the capillary force, so that the meniscus is expanded and as shown in FIG. 6. PMMA pattern is formed.
Referring back to Figures 1 to 5, in one embodiment, in order to control the shape of the graphene pattern (GP) can be adjusted the feed rate of the pattern forming jig. At this time, the graphene
In another embodiment, the jig transfer part may be transferred by linearly moving the pattern forming jig. In this case, the pattern forming jig may have a flat plate shape, and may have a flat knife or blade shape.
Subsequently, a graphene pattern GP is formed corresponding to the solute pattern (S150). For example, the pattern forming unit forms a graphene pattern GP corresponding to the PMMA pattern PP.
In one embodiment, when forming the graphene pattern (GP) (S150), the remaining graphene except for the graphene corresponding to the solute pattern is removed, and the remaining solute corresponding to the remaining graphene is removed. can do. That is, the PMMA pattern PP functions as a mask to remove the remaining graphene except for graphene positioned below the PMMA pattern PP, and to remove the remaining PMMA pattern PP on the remaining graphene. By removing the graphene pattern GP can be formed. In this case, the exposed graphene to be removed may be removed by plasma treatment, for example, oxygen plasma treatment, and the solute remaining on the graphene pattern may be removed by an organic solvent, for example, acetone. .
The removal of the graphene may be performed by the graphene removal unit, and the removal of the residual solute may be performed by the solute removal unit, respectively.
Unlike this, when the graphene pattern GP is formed (S140), the solute pattern and the graphene corresponding to the solute pattern are simultaneously removed and the remaining graphene is left except for the graphene corresponding to the solute pattern. As a result, the graphene pattern GP may be formed. That is, the graphene pattern (by removing the graphene located under the PMMA pattern PP and the PMMA pattern PP at the same time, and leaving the remaining graphene except for the graphene corresponding to the PMMA pattern PP) GP) may be formed.
Removal of the solute pattern and the graphene corresponding to the solute pattern may be performed by a solute / graphene removal unit.
7 to 10 are images showing graphene patterns formed according to the method for manufacturing a graphene pattern according to FIGS. 1 to 5.
7 to 10, it can be seen that the graphene patterns formed by using the PMMA solution according to the method of manufacturing the graphene patterns according to FIGS. 1 to 5 are uniformly formed at regular intervals.
7 shows graphene patterns prepared when the concentration of the PMMA solution and the feed rate of the cylindrical roller are set to 2.0 mg / mL and 11.2 μm / s, respectively, and FIG. 8 shows the concentration of the PMMA solution and the feed rate of the cylindrical roller. Graphene patterns produced when set to 2.0 mg / mL and 17.8 μm / s, respectively, are shown.
From the images shown in FIGS. 7 and 8, it can be seen that as the feed speed of the cylindrical roller increases, the width of the graphene pattern generally decreases.
9 shows graphene patterns prepared when the concentration of the PMMA solution and the feed rate of the cylindrical roller were set to 2.0 mg / mL and 17.8 μm / s, respectively, and FIG. 10 shows the concentration of the PMMA solution and the feed rate of the cylindrical roller. The graphene patterns produced when set to 1.0 mg / mL and 11.2 μm / s, respectively.
From the images shown in FIGS. 7 and 8, it can be seen that the width of the graphene pattern is generally reduced as the concentration of the PMMA solution is decreased.
As described above, by supplying a solution on a substrate on which graphene is formed and transferring a pattern forming jig to generate an EISA phenomenon and obtaining a graphene pattern corresponding to the solute pattern obtained therefrom, complex processes such as a conventional lithography process may be performed. It is possible to easily form the graphene pattern manufactured through the simpler method, thereby greatly reducing the manufacturing cost of the graphene pattern.
11 is a flowchart illustrating a method of manufacturing a FET according to an embodiment of the present invention, and FIG. 12 is a flowchart illustrating a process of forming the second graphene pattern of FIG. 11 in detail. 13 to 15 are perspective views illustrating a process of forming the second graphene pattern of FIG. 12.
11 to 15, in order to manufacture a field effect transistor (FET) according to an exemplary embodiment of the present invention, first, graphene G is formed on the substrate 10 (S210). A pattern forming jig is disposed on the
Since the above-described steps S210, S220, S230, S240, and S250 are substantially the same as the steps S110, S120, S130, S140, and S150 described with reference to FIGS. 1 to 5, detailed descriptions thereof will be omitted.
The first graphene pattern GP1 may be formed in two or more layers. For example, after forming the graphene G on the substrate 10 (S210), the process of forming the first graphene pattern GP1 (S250) is performed two or more times. One graphene pattern GP1 may be formed in two or more layers.
Next, a second graphene pattern GP2 is formed to cross the first graphene pattern GP1 (S260).
In example embodiments, the forming of the second graphene pattern GP2 may include forming the second graphene pattern GP2 on the
Specifically, first, the graphene G is formed on the
Subsequently, a pattern forming jig is disposed on the
For example, the pattern forming jig may employ a pattern forming jig used to form the first graphene pattern GP1. Alternatively, the pattern forming jig may employ a separate pattern forming jig that is not used to form the first graphene pattern GP1. The pattern forming jig is disposed to cross the first graphene pattern GP1 to form a pattern crossing the first graphene pattern GP1, and the crossing angle may be, for example, approximately 90 degrees.
Next, a solution is supplied onto the
Subsequently, the pattern forming jig is transferred to cross the first graphene pattern GP1 so that an EISA phenomenon occurs in the solution to form a second solute pattern on the graphene (S264). For example, when the second solute is PMMA, the second solute pattern may be a second PMMA pattern PP2. The process may be substantially the same as forming the solute pattern of FIG. 1 except for transferring the pattern forming jig to cross the graphene pattern GP.
For example, the second solute pattern may cross the first solute pattern and the first graphene pattern GP1, and the crossing angle may be, for example, about 90 degrees.
Next, a second graphene pattern GP2 is formed corresponding to the second solute pattern (S265). The process may be similar to the step S150 of forming the graphene pattern GP of FIG. 1.
In an embodiment, when forming the second graphene pattern GP2 (S265), the remaining graphene except for the graphene corresponding to the second solute pattern is removed, and the remaining graphene corresponds to the remaining graphene. Residual solutes may be removed. That is, the second PMMA pattern PP2 functions as a mask to remove the remaining graphene except for graphene positioned under the second PMMA pattern PP2 and to remove the remaining graphene. The second graphene pattern GP2 may be formed by removing the 2 PMMA pattern PP2. In this case, the exposed graphene to be removed may be removed by plasma treatment, for example, oxygen plasma treatment, and the solute remaining on the graphene pattern may be removed by an organic solvent, for example, acetone. .
In addition, when removing the remaining graphene except for the graphene corresponding to the second solute pattern, portions of the first graphene pattern GP1 that do not correspond to the second solute pattern may be simultaneously removed. . That is, between two adjacent patterns of the second PMMA pattern PP2 among the first graphene pattern GP1 positioned under the graphene G for forming the second graphene pattern GP2. Also, portions not covered by the second PMMA pattern PP2 may be removed at the same time. Accordingly, as shown in FIG. 15, portions intersected by the second graphene pattern GP2 of the first graphene pattern GP1 are left, and under the second graphene pattern GP2. The remaining first graphene pattern GP1 may be formed to be alternately positioned.
After forming the second graphene pattern GP2 to cross the first graphene pattern GP1 (S260), a dielectric layer and a gate electrode may be formed as follows.
16 to 18 are perspective views illustrating a process of forming the dielectric layer and the gate electrode of FIG. 11, and FIG. 19 is a cross-sectional view illustrating a FET formed by an embodiment of the present invention.
11 and 16 to 18, the second graphene pattern (eg, intersecting with the first graphene pattern GP1 of the first graphene pattern GP1 and connecting two neighboring portions to each other) is connected to each other. A dielectric layer DL is formed on the GP2 (S270).
In an embodiment, after the second graphene pattern GP2 is formed, as illustrated in FIG. 16, the first graphene pattern GP1 has a rectangular dot shape to form the
For example, the dielectric layer DL may include an ion-gel, and the dielectric layer DL may be formed on the second graphene pattern GP2 by ion gel printing. Can be.
In one embodiment, the ion gel is acetonitrile (acetonitrile) 1-ethyl (ethyl) -3- methylimidazolium (methylimidazolium), bis (trifluoromethylsulfonyl) imide (bis (trifluoromethylsulfonyl) imide), It may be prepared by dissolving a polyethylene oxide powder or the like. The dielectric layer DL may be formed by dropping an ion gel on the second graphene pattern GP2 and then slowly drying it by N2 blowing.
Subsequently, as shown in FIG. 18, a gate electrode GE is formed on the dielectric layer DL (S280).
For example, the gate electrode may include poly 3,4-ethylenedioxythiophene (PEDOT), and the gate electrode may be formed on the dielectric layer by PEDOT printing.
In an embodiment, PEDOT: PSS (polystyrenesulfonate) may be dropped on the dielectric layer DL and then dried to form a gate electrode GE.
In an embodiment, the FET formed as described above may have a two-layer structure in which the first and second graphene patterns GP1 and GP2 are stacked on the left and right sides of the
As described above, by supplying a solution on a substrate on which graphene is formed and transferring a pattern forming jig to generate an EISA phenomenon and forming a graphene pattern corresponding to the solute pattern obtained therefrom in at least two or more patterns so as to intersect with each other, It is possible to easily form a FET using a graphene pattern, which can be manufactured only through complex processes such as a conventional lithography process, by a simpler method, thereby greatly reducing the manufacturing cost of the FET.
In addition, since the graphene pattern to be manufactured is formed very uniformly, a high quality graphene pattern can be obtained, and in the case of manufacturing a large-area FET using a large-area graphene pattern, the same method is applied as it is in addition to the enlargement of the target substrate. This makes it easier and less expensive to manufacture large area FETs.
While the present invention has been described in connection with what is presently considered to be practical and exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Accordingly, the foregoing description and drawings are to be regarded as illustrative rather than limiting of the present invention.
10: substrate 100: graphene pattern manufacturing apparatus
110: cylindrical roller 130: transfer plate
DL: dielectric layer G: graphene
GE: gate electrode GP: graphene pattern
GP1: first graphene pattern GP2: second graphene pattern
PP: PMMA Pattern PP2: Second PMMA Pattern
Claims (16)
Disposing a pattern forming jig on the graphene formed substrate;
Supplying a solution on the graphene-formed substrate;
Forming a first solute pattern on the graphene by transferring the pattern forming jig so that an EISA (Evaporation-Induced Self Assembly) phenomenon occurs in the solution;
Forming a first graphene pattern corresponding to the first solute pattern;
Forming a second graphene pattern to cross the first graphene pattern;
Forming a dielectric layer on the second graphene pattern to connect two neighboring portions intersecting with the first graphene pattern and adjacent to each other among the first graphene pattern; And
A method of manufacturing a field effect transistor (FET) using graphene, including forming a gate electrode on the dielectric layer.
Removing the remaining graphene except for graphene corresponding to the first solute pattern; And
The method of manufacturing a FET using a graphene, comprising the step of removing the residual solute corresponding to the remaining graphene.
The removed exposed graphene is removed by a plasma treatment, the remaining solute corresponding to the remaining graphene is removed by an organic solvent (solvent) method of manufacturing a FET using a graphene.
Forming graphene on the substrate on which the first graphene pattern is formed;
Disposing a pattern forming jig on the first graphene pattern and the graphene formed substrate so as to intersect the first graphene pattern;
Supplying a solution on the first graphene pattern and the substrate on which graphene is formed;
Forming a second solute pattern on the graphene by transferring the pattern forming jig to intersect the first graphene pattern so that an EISA phenomenon occurs in the solution; And
And forming a second graphene pattern in correspondence with the second solute pattern.
Removing the remaining graphene except for graphene corresponding to the second solute pattern; And
The method of manufacturing a FET using a graphene, comprising the step of removing the residual solute corresponding to the remaining graphene.
A portion of the first graphene pattern that is intersected by the second graphene pattern is left, and the first graphene pattern remaining below the second graphene pattern is formed to be alternately positioned. Method for manufacturing a FET using a pin.
The dielectric layer includes an ion-gel,
The dielectric layer is a method of manufacturing a FET using graphene, characterized in that formed on the second graphene pattern by ion gel printing (printing).
The gate electrode includes PEDOT (poly 3,4-ethylenedioxythiophene),
The gate electrode is a method of manufacturing a FET using graphene, characterized in that formed on the dielectric layer by PEDOT printing.
Method for producing a FET using the graphene, characterized in that further comprising the step of adjusting the concentration of the solution.
And adjusting a feed rate of the pattern forming jig to control the shape of the first graphene pattern.
The pattern forming jig includes a cylindrical roller,
In the transferring the pattern forming jig to form a first solute pattern on the graphene,
The first solute pattern is formed by rotating the cylindrical roller by a transfer plate disposed on the cylindrical roller FET manufacturing method using a graphene, characterized in that.
Method for producing a FET using graphene, characterized in that the irregularities formed on the cylindrical roller.
The pattern forming jig has a plate shape,
The pattern forming jig is transferred by linear movement to form a first solute pattern on the graphene manufacturing method of the FET using the graphene, characterized in that.
The solute is a method of manufacturing a FET using graphene, characterized in that it comprises any one of polymethyl methacrylate (PMMA), metal particles (particles) and inorganic particles.
The substrate is a method of manufacturing a FET using graphene, characterized in that containing any one of polyethylene terephthalate (PET) and SiO 2 / Si.
Forming at least two first graphene patterns by repeatedly performing at least two times from forming graphene on the substrate to forming a first graphene pattern corresponding to the first solute pattern. Method for manufacturing a FET using a graphene characterized in that.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP3012847A1 (en) * | 2014-10-21 | 2016-04-27 | Nokia Technologies OY | A multilayer graphene composite |
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| JP2011006265A (en) * | 2009-06-23 | 2011-01-13 | Oki Data Corp | Method for releasing graphene layer, method for producing graphene wafer, graphene wafer and method for producing graphene element |
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| KR20120086618A (en) * | 2011-01-26 | 2012-08-03 | 고려대학교 산학협력단 | Semiconductor device using carbon nano material, and fabricationg method for the device |
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| US10522628B2 (en) | 2014-10-21 | 2019-12-31 | Nokia Technologies Oy | Apparatus with graphene layers intercalated with ion gel |
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