KR101341831B1 - Fabrication Method of Back Contact Solar Cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a back electrode solar cell, and in detail, a method of manufacturing according to the present invention includes: a) forming a hole to penetrate two opposite surfaces of a first conductive semiconductor substrate; b) a doping step of forming a second conductive layer by doping a second conductive impurity on the surface of the semiconductor substrate; c) an etch-resist forming step of forming an etch-resist pattern on one of the two opposing surfaces to cover the opening of the via hole; d) etching the one surface with the etch-resist pattern with an etch mask to remove a second conductive layer present in one surface area where the etch-resist pattern is not formed; And e) a partial etching step of controlling the impurity concentration of the second conductive layer existing on the other surface by partially removing the second conductive layer existing on the other surface which is the opposite surface of the one surface.

Description

Fabrication Method of Back Electrode Solar Cell {Fabrication Method of Back Contact Solar Cell}

The present invention relates to a method for manufacturing a back electrode solar cell, and in detail by a single doping process, the opposite surface of the light receiving surface and the light receiving surface may have a surface resistance different from the back light surface, high short-circuit current, open voltage And a method of manufacturing a back electrode solar cell having fidelity and having excellent photoelectric conversion efficiency.

In recent years, interest in renewable energy has increased due to rising oil prices, global environmental problems, depletion of fossil energy, waste disposal of nuclear power generation, and the selection of locations due to construction of new power plants. The research and development of the is actively progressing.

A solar cell is a device that converts light energy into electrical energy by using the photovoltaic effect. It has advantages such as pollution-free, indefinite resource, and semi-permanent life, and can ultimately solve energy problems for humans regardless of environmental problems. It is expected to be a source of energy.

Solar cells are divided into silicon solar cells, thin film solar cells, dye-sensitized solar cells, and organic polymer solar cells according to the material of the solar cell. The crystalline silicon solar cells account for most of the total production of solar cells in the world. This is the most popular solar cell because the technology is higher than that and continues to lower the manufacturing cost.

As in Korean Patent Laid-Open Publication No. 2007-0004671, the EWT structure of the back electrode silicon solar cell has several advantages over the conventional silicon solar cell. The first advantage is that the back electrode cell has a high conversion efficiency as the contact shadowing losses due to the electrode are eliminated. The second advantage is that the contacts of both poles are on the same surface, making it easier to assemble the back-electrode cell into the electrical circuit, which makes it possible to produce the module at a lower cost. Third, conventional back-electrode silicon solar cells (Interdigited Back Contact) are manufactured on n-type substrates with long electron lifetimes, but they are also manufactured on p-type substrates with low manufacturing cost by forming holes through which electrons can move. This can lower the cost of the process.

There are several approaches for the fabrication of back electrode silicon solar cells. In these approaches, metallization wrap-throughs (MWTs) connect the inside of the hole and the back electrode to an electrode to fabricate a back electrode cell. The unique feature of the back-electrode solar cell compared to the MWT solar cell is that electrons move by connecting the inside of the hole and the back electrode to the emitter. Such conductive channels can be produced by creating holes in the silicon substrate with a laser and then forming emitters inside the holes while simultaneously forming emitters on the front and back surfaces. The back electrode solar cell has both a cathode and an anode collection junction on the backside of the solar cell. Since most of the light is absorbed near the front, the back junction cell requires very high material properties to ensure sufficient time for the carriers to diffuse from the front to the back with the collection junction on the back.

In the case of a solar cell having a back electrode structure, in order to reduce surface recombination and facilitate charge transfer, the surface resistance of each of the light receiving and backing surfaces must be finely adjusted. It is used. However, such a conventional method has a long process time and complicated steps, which impede productivity improvement.

Republic of Korea Patent Publication No. 2007-0004671

The present invention provides a method of manufacturing a back electrode solar cell having high short circuit current, open voltage and fidelity through a single doping process, and having excellent photoelectric conversion efficiency. The present invention provides a method for manufacturing a battery, and provides a method for manufacturing a back electrode solar cell having excellent cost reduction and productivity due to reduced process steps and shortened manufacturing time.

A method of manufacturing a back electrode solar cell according to the present invention includes a) forming a hole for penetrating two opposite surfaces of a first conductive semiconductor substrate; b) a doping step of forming a second conductive layer by doping a second conductive impurity on the surface of the semiconductor substrate; c) an etch-resist forming step of forming an etch-resist pattern on one of the two opposing surfaces to cover the opening of the via hole; d) etching the one surface with the etch-resist pattern with an etch mask to remove a second conductive layer present in one surface area where the etch-resist pattern is not formed; And e) a partial etching step of partially removing the second conductive layer present on the other surface opposite to the one surface to control the impurity concentration of the second conductive layer present on the other surface; .

Method for manufacturing a back electrode solar cell according to an embodiment of the present invention includes the steps of f) forming a passivation film on the surface, and forming an anti-reflection film on the other surface; g) a passivation film removing step of partially applying an etching paste for etching a passivation film on the one surface to expose a semiconductor substrate region from which the second conductive layer is removed by the selective etching step; And h) forming an electrode on the one surface to form a first electrode connected to the exposed semiconductor substrate region and a second electrode connected to the second conductive layer by punch-through.

In the method of manufacturing a back electrode solar cell according to the present invention, a step difference between the surface of the semiconductor substrate and the second conductive layer under the etching-resist pattern is formed by removing the second conductive layer by the selective etching step. The surface step may be 1 to 15㎛.

In the method of manufacturing a back electrode solar cell according to the present invention, the sheet resistance of the second conductive layer formed in the doping step may be 10 to 40 Ω / sq., And the partial etching step may include a second layer located on the other surface. The second conductive layer on the other surface may be partially removed so that the sheet resistance of the conductive layer is 30 to 150 Ω / sq.

In the method of manufacturing a back electrode solar cell according to the present invention, the partial etching may be performed by dry etching.

In the method of manufacturing a back electrode solar cell according to the present invention, by the partial etching, the thickness of the second conductive layer formed on the inner surface of the via hole in the doping step may be controlled.

In the method of manufacturing a back electrode solar cell according to the present invention, the second conductive layer formed on the inner surface of the via hole may be reduced in thickness from one surface to the other by the partial etching.

In the method of manufacturing a back electrode solar cell according to the present invention, after the partial etching is performed, the cleaning using the RCA (Radio Corporation of America) cleaning method may be further performed.

In the method of manufacturing a back electrode solar cell according to the present invention, the etching resist pattern may be formed by a printing process, and the printing process may include screen printing.

The present invention includes a back electrode solar cell manufactured by the above-described manufacturing method.

The manufacturing method of the present invention has a high short-circuit current, open voltage and fidelity through a single doping process, has excellent photoelectric conversion efficiency, has the effect of preventing the generation of leakage current when forming the electrode, the process step is reduced and manufacturing time This shortening has the advantage of excellent cost reduction and productivity.

1 is an example showing a process diagram according to the manufacturing method of the present invention,
FIG. 2 is a scanning electron micrograph of the via hole cross section when the partial etching is performed by using dry etching in the manufacturing method of the present invention.
Figure 3 is another example showing a process diagram according to the manufacturing method of the present invention.
Description of the Related Art [0002]
100: first conductive semiconductor substrate 1: via hole
210: rear emitter layer 220: front emitter layer
230: via hole emitter layer 300: etching-resist pattern
211: patterned back emitter layer 221: front emitter layer with controlled doping concentration
400: antireflection film 500: passivation film
510: etched passivation film 600: p-type electrode
710: first electrode before heat treatment 720: second electrode
711: Punched through first electrode

Hereinafter, a manufacturing method of the present invention will be described in detail with reference to the accompanying drawings. The following drawings are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the following drawings, but may be embodied in other forms, and the following drawings may be exaggerated in order to clarify the spirit of the present invention. Also, throughout the specification, like reference numerals designate like elements.

Hereinafter, the technical and scientific terms used herein will be understood by those skilled in the art without departing from the scope of the present invention. Descriptions of known functions and configurations that may be unnecessarily blurred are omitted.

In the method of manufacturing a back electrode solar cell according to the present invention, after doping a second conductive type impurity on a surface of a first conductive type semiconductor substrate having a via hole penetrating two opposite surfaces of the semiconductor substrate, the opening of the via hole is covered. Forming an etching-resist pattern on at least one surface of the two opposing surfaces, and etching the one surface with the etching-resist pattern with an etching mask to selectively remove the second conductive layer exposed on the one surface; do.

In detail, a method of manufacturing a back electrode solar cell according to the present invention includes a) forming a hole to penetrate two opposite surfaces of a first conductive semiconductor substrate; b) a doping step of forming a second conductive layer by doping a second conductive impurity on the surface of the semiconductor substrate; c) forming an etch-resist pattern on at least one of the two opposing surfaces to cover the opening of the via hole; d) etching the one surface with the etch-resist pattern with an etch mask to remove a second conductive layer present in one surface area where the etch-resist pattern is not formed; And e) partially etching the second conductive layer present on the other surface, which is the opposite surface of the one surface, to partially control the impurity concentration of the second conductive layer present on the other surface.

As shown in FIG. 1, which is a process diagram of a fabrication method according to an embodiment of the present invention, the fabrication method according to an embodiment of the present invention passes through two opposite surfaces of the first conductive semiconductor substrate 100. (1) forming a hole, and diffusing a second conductive type impurity on a surface of the semiconductor substrate 100 including the two opposing surfaces of the semiconductor substrate 100 and an inner surface of the via hole, thereby forming the two opposing surfaces and the vias. A doping step of forming the second conductive layers 210, 220, and 230 on the inner surface of the hole; an etching-resist pattern by applying an etching-resist to at least one of the two opposing surfaces to cover the opening of the via hole 1; An etching-resist forming step of forming (300), wherein the one surface is etched using the etching-resist pattern 300 by an etching mask, so that the etching-resist pattern 300 is present in one surface area where the etching-resist pattern 300 is not formed. The second conductive layer A selective etching step of removing and partially etching away the second conductive layer existing on the other surface that is the opposite surface of the one surface in a depth direction (the shortest straight direction connecting the two opposite surfaces) to the other surface. And a partial etching step of controlling the impurity concentration of the second conductive layer present.

The first conductivity type refers to a p-type or n-type property, and the second conductivity type refers to a conductive property complementary to the first conductivity type. Hereinafter, although the first conductive type is p-type and the second conductive type is n-type, the present invention will be described in detail. However, even if the first conductive type is n-type and the second conductivity type is p-type, This is of course maintained.

The first conductivity type may mean p-type characteristics due to p-type impurities, and the second conductivity type may refer to n-type characteristics due to n-type impurities that are complementary to the p-type impurities. In this case, the p-type impurity includes an impurity that is doped in the semiconductor substrate to provide holes, and the n-type impurity includes an impurity that is doped in the semiconductor substrate to provide electrons. For example, the p-type impurity may be one or two or more selected from aluminum, boron, and indium, and the n-type impurity may be selected from one or more of arsenic and phosphorus.

 The semiconductor substrate 100 may include a group 4 semiconductor substrate including silicon (Si), germanium, or silicon germanium (SiGe); A III-V group semiconductor substrate including gallium arsenide (GaAs), indium phosphide (InP), or gallium phosphide (GaP); A Group 2-6 semiconductor substrate comprising cadmium sulfide (CdS) or zinc telluride (ZnTe); Or a Group 4-6 semiconductor substrate including lead sulfide (PbS). Crystallographically, the semiconductor substrate 100 may include a monocrystalline, polycrystalline or amorphous substrate.

The hole forming step includes forming a via hole 1 penetrating two opposing surfaces of the semiconductor substrate 100, for example, a light receiving surface that receives sunlight and a backside surface that is an opposite surface of the light receiving surface. can do.

The hole forming step may be performed using laser drilling, and may be formed by other methods such as dry etching, wet etching, mechanical drilling, or water-jet machining. When using laser drilling, it is desirable to use a laser of sufficient power or strength at the operating wavelength so that holes can be formed in the shortest time, such as 0.5 ms to 5 ms per hole. An example that can be used for laser drilling is the Nd: YAG laser. The diameter of the via hole 1 manufactured in the hole forming step is, for example, 25 to 125 μm, and preferably, 30 to 60 μm.

In the hole forming step, a plurality of via holes 1 spaced apart from each other are formed in the semiconductor substrate 100, and in detail, openings of the via holes 1 exposed on one surface of the two opposing surfaces are formed. As a reference, a plurality of via holes are arranged so that M (N = 1 natural numbers) openings in the first direction and N (N = 1 natural numbers) via holes openings are regularly spaced in an MxN matrix. This can be formed. In this case, the first direction and the second direction belong to the same plane (surface of the semiconductor substrate), the first direction and the second direction may have a predetermined angle including 90 degrees to each other.

According to the core idea of the present invention, as the photocurrent moving path having a low sheet resistance in the solar cell is formed, the density of the via holes 1 (the number of via holes per substrate surface area) can be reduced, thereby per semiconductor substrate area. The light active area capable of receiving light can be maximized. As a practical example, the density of the via hole 1 may be 0.25 to 0.5 pieces / mm ² .

Since the hole forming step performed by the laser drilling may involve thermal damage to the semiconductor substrate 100, after the via hole 1 forming process, an etching process for removing the damaged region may be performed. damage removal etching) may be further performed.

The etching process for removing the damaged region at the time of hole formation is sufficient if it is a process normally used by a semiconductor process. For example, an etching process for removing damaged areas such as burrs on the surface may be performed using an alkaline etching solution, and in one example, using sodium hydroxide or potassium hydroxide at a temperature of 80 to 90 ° C. Can be.

By the hole forming step, a semiconductor substrate 100 having a plurality of via holes 1 spaced apart from each other may be manufactured, and then a doping step of doping a second conductive impurity may be performed on the semiconductor substrate. .

In the doping step, a second conductive impurity is doped on the surface of the semiconductor substrate including two opposing surfaces of the semiconductor substrate 100 and an inner surface of the hole of the via hole, so that the second conductive impurity is deposited on the surface of the semiconductor substrate 100. Forming a doped surface doping layer.

 A second layer of the second conductive dopant doped with a surface layer on the surface of the semiconductor substrate 100 including two opposing surfaces of the semiconductor substrate 100 and a surface (inner surface) of the via hole 1 in the doping step; The conductive layers 210, 220, and 230 are formed. Hereinafter, a second conductive layer formed on one of the two opposing surfaces is the front emitter layer 220, and a second formed on the surface of the via hole 1. The conductive type layer is referred to as the via hole emitter layer 230, and the second conductive layer formed on the other of the two opposing surfaces is referred to as the back side emitter layer 210.

The doping step may be performed by heat-treating the semiconductor substrate 100 in the presence of a gas containing a second conductive impurity or by using a solid state source or a spray-on diffusion source containing a second conductive impurity. Can be performed. For example, a second conductive type impurity, which is at least one selected from gaseous POCl ₃ , P ₂ O _5, and PH ₃ , is mixed with a carrier gas of an inert gas, and the semiconductor substrate 100 is 800 ° C. to 900 ° C. The second conductive impurities may be doped into the semiconductor substrate 100 by heat treatment at a temperature of ˚C for 10 to 60 minutes. At this time, the step of removing the impurity film, such as phosphorous silicate (glass) produced by the doping heat treatment using the HF etchant may be further performed.

The second conductive layer including the front emitter layer 220, the via hole emitter layer 230, and the back emitter layer 210 is formed by the above-described doping step, wherein the sheet resistance is 10 to 40 Ω in the doping step. A second conductive layer of / sq. may be formed.

At this time, in the doping step, the side surface of the semiconductor substrate 100, that is, the surface parallel to the via hole is properly sealed so as not to be doped with a second conductive impurity, or the side surface of the semiconductor substrate 100. Of course, the process of removing the formed second conductive layer may be performed.

The etching-resist forming step may be a step of forming a pattern of etching-resist so as to cover the opening of the via hole 1 on one of two opposite surfaces of the semiconductor substrate 100 through which the via holes 1 pass. have.

In detail, the etch-resist pattern 300 is formed on the surface on which the back emitter layer 210 of the semiconductor substrate 100 is formed, and the pattern of the etch-resist pattern 300 is the via hole emitter layer 230. It may have a shape corresponding to the n-type electrode to be electrically connected with.

The etching-resist paste may be any material that is physicochemically stable at the time of etching the semiconductor substrate, and may be any material having corrosion resistance to an alkali or acidic etching solution. For example, the etching-resist paste may use a commercial product including sgc-2500 (Seoul Chemical Research Institute). The etch-resist paste is preferably applied using a printing method such as ink jet printing, masking, stencil, screen printing. Direct printing of the etch-resist paste simplifies process conditions, reduces production time, and increases manufacturing costs and production efficiency.

The etching-resist pattern 300 may be formed by applying the etching-resist paste in a plurality of band shapes covering the openings of the via holes 1, and the plurality of band shapes may have a bone structure or a comb structure. It may correspond to the n-type electrode shape having.

In detail, the etch-resist pattern 300 generated by applying the etch-resist paste may include a plurality of openings covering the openings of the via holes 1 exposed to the semiconductor substrate 100 on which the back emitter layer 210 is formed. A stripe (etching resist stripe) type pattern may be included.

More specifically, based on the opening of the via hole 1 located on the surface of the semiconductor substrate 100 on which the back emitter layer 210 is formed, M (M < 1 > natural numbers) in the first direction and the second direction When the plurality of via holes 1 are formed such that N (N > 1 natural) via hole 1 openings are regularly spaced apart, the etching-resist patterns 300 are parallel to each other in the first direction. A plurality of bands may be spaced apart from each other, and the bands (etching resist bands) may cover all of the openings of the plurality of via holes 1 located on the same line in the second direction.

In this case, the strip of the etching resist forming the etching resist pattern 300 may have a width of 3 to 6 times the width of the opening of the via hole 1.

After the etching-resist pattern 300 is formed, etching may be performed on the surface on which the back emitter layer 210 of the semiconductor substrate 100 is formed, using the etching-resist pattern 300 as an etching mask. have. In detail, in the region where the etching-resist pattern 300 is not formed, the back side emitter layer 210 may be removed by etching performed in the selective etching step.

The selective etching step is performed by patterning the rear emitter layer 210 by removing the rear emitter layer 210 formed on the remaining surface except for a predetermined region adjacent to the opening of the via hole 1, and performing the selective etching step. The depth of etching may be controlled to remove the backside emitter layer 210 existing in the region where the etching-resist pattern 300 is not formed.

In the etching process performed in the selective etching step, the semiconductor surface on which the back emitter layer 210 is formed is etched to a predetermined depth, so that the back emitter layer 210 existing in the region where the etch-resist pattern 300 is not formed is formed. It can be removed by controlling the time of etching performed in the selective etching step. After the selective etching step is performed, the etching-resist pattern 300 may be removed. After the etching-resist pattern is removed, the semiconductor substrate may be washed with a mixed solution of ammonia water, hydrogen peroxide and water. Of course, further steps may be performed.

By the selective etching step, the back emitter layer 210 may be patterned in a shape corresponding to the etching-resist pattern 300.

In detail, based on the opening of the via hole 1 located on the surface of the semiconductor substrate 100 on which the back emitter layer 210 is formed, M (N = M natural numbers) in the first direction and in the second direction. When a plurality of via holes 1 are formed such that N (N > 1 natural) via hole 1 openings are regularly spaced apart, the back emitter layer 211 patterned by the selective etching step is The surface-doped layer having a plurality of strips arranged parallel to each other in the first direction and having a single strip-shaped second conductive type doped opening has a plurality of openings of the via holes 1 located on the same line in the second direction. It is located on the extension line.

That is, by the selective etching step, a second conductive type surface doping layer is selectively formed on a portion where an n-type electrode (n-type finger electrode), which is positioned on the backside of the back electrode solar cell, is formed. Will be.

In this case, the etching resist pattern may have a pattern in which a plurality of band shapes covering all of the openings of the plurality of via holes 1 positioned on the same line are arranged to be spaced apart from each other, and across the plurality of bands spaced apart from each other. It may further include another strip shape.

That is, the etching-resist pattern 300 includes a pattern coated with an etching resist in a shape and a position corresponding to the shape and position of an n-type finger electrode of a back electrode solar cell, and includes a pattern corresponding to the n-type finger electrode. It may include a pattern coated with an etching resist in a shape and position corresponding to the shape and position of the n-type bus bar electrode to connect the n-type finger electrodes together.

 As a result, a second conductive doping layer (patterned back-emi) is selectively formed in the region where the n-type finger electrode is formed on the semiconductor substrate surface and the region where the n-type bus-bar electrode is formed. A foundation layer 211 may be formed.

By the selective etching step, a surface step may be formed on one surface of the semiconductor substrate 100, that is, the backlight surface.

That is, since the patterned back emitter layer 210 and the etching-resist pattern 300 are not formed, etching may be performed to form a surface step between regions where the p-type semiconductor substrate is exposed to the surface.

By performing the selective etching step, the back emitter layer 210 is patterned into a position and a shape where an n-type finger electrode (and an n-type busbar electrode) are formed, and at the same time, a surface step is formed on the back surface of the semiconductor substrate 100. By doing so, it is possible to prevent the occurrence of leakage current and to improve fidelity.

The etching of the selective etching step may be performed using wet etching or dry etching, and the wet etching may use a conventional etching solution of nitric acid, hydrofluoric acid, acetic acid. When the selective etching step is performed using wet etching, the surface of the semiconductor substrate is immersed in an etchant (one surface on which a back emitter layer is formed), and the etched depth of the one surface is controlled to control the etched depth. Of course, in the case of dry etching, it is also possible to control the etched depth by adjusting the etching time.

After the selective etching step is performed, a partial etching step of etching the surface of the semiconductor substrate 100 on which the front emitter layer 220 is formed to a predetermined depth is performed. The doping step causes heavy doping of the second conductive impurity on the surface of the semiconductor substrate. The partial etching step removes only a part of the thickness of the front emitter layer 200 to remove the second emitter layer 220. Controlling the doping concentration of the biconductive impurity.

As the etching of the front emitter layer 220 proceeds, the concentration of the second conductive impurity remaining on the surface decreases and the sheet resistance of the front emitter layer 220 increases. As the surface resistance of the front emitter layer 220 increases, surface recombination decreases, thereby increasing the collection efficiency of carriers generated by the short wavelength light, thereby increasing the short circuit current density and the open voltage, thereby increasing the conversion efficiency of the solar cell. You can. In this case, the partial etching step may be performed so that the front emitter layer 220 has a sheet resistance of 30 ~ 150Ω / sq.

The etching of the partial etching step may be performed by dry etching. That is, the etching of the partial etching step may be performed by dry etching having directivity in etching, and the dry etching may include plasma etching.

As the partial etching step is performed by the dry etching having the directionality, the impurity concentration of the via hole emitter layer 230 adjacent to the front emitter layer 220 is also adjusted together with the front emitter layer 220 to thereby provide a short circuit current, Open voltage and fidelity can be further improved.

In detail, the surface of the semiconductor substrate 100 on which the front emitter layer 220 is formed is etched to a predetermined depth by using dry etching having a directionality, thereby controlling the thickness of the via hole emitter layer 230 formed on the inner surface of the via hole. Can be. That is, by the partial etching, the via hole emitter layer 230 formed on the inner surface of the via hole 1 may decrease in thickness from the back surface of the semiconductor substrate 100 to the light receiving surface of the semiconductor substrate 100. In addition, the thickness of the via hole emitter layer 230 may be continuously reduced in the direction of the light receiving surface of the semiconductor substrate 100 on the back surface of the semiconductor substrate 100.

 More specifically, when dry etching the surface of the semiconductor substrate 100 on which the front emitter layer 220 is formed, the via hole emitter layer 230 may also be etched through the opening of the via hole 1 by the direction of etching. have. As the dry etching has a straight direction, the closer to the front emitter layer 220, the more etching occurs, and the region of the via hole emitter layer 230 adjacent to the front emitter layer 220 is adjacent to the front emitter layer. The concentration of the second conductive impurity may be controlled to have a similar resistance, and may have a low resistance by heavy doping in the doping step in a region adjacent to the back emitter layer.

FIG. 2 is a cross-sectional scanning electron micrograph of a via hole observed when performing a partial etching step using plasma etching. In FIG. 2, the front surface refers to the light receiving surface and the rear surface refers to the back surface, and P1 to P5 refer to scanning electrons. The area analyzed using EDS (Energy Dispersive Spectroscopy) attached to the microscope device is displayed, and the number (nm) located in the lower part of P1 to P5 is the depth of pn junction in each area of the EDS analysis. And the thickness of the via hole emitter layer.

As can be seen in FIG. 2, when the front emitter layer 220 is etched to a certain depth by dry etching in order to adjust the resistance of the light receiver front emitter layer 220, the pn junction depth between the via hole emitter layer and the substrate. It can be seen that the thinner the thinner the light from the back to the light receiving surface. This is due to the straightness of etching during dry etching, and it can be seen that the depth of the via hole emitter layer gradually decreases in the direction of the light receiving surface from the backside by dry etching.

After forming a 75 μm diameter via hole with a density of 58 pieces / cm ^{2 in} a 150-180 μm-thick p-type semiconductor substrate, and doping with P-type impurities, a second conductive layer of 25 Ω / sq. Was formed on the surface of the semiconductor substrate. By patterning the back emitter layer to have a golgol structure having a width of 1 to 2 mm by the etching resist forming step and the selective etching step, and then plasma-etching the light receiving surface so that the front emitter layer has a resistance of 47 Ω / sq. The solar cell has a short circuit current density (Jsc) of 40.59 mA / cm ² , an open voltage (Voc) of 0.628 V, a figure of merit (FF) of 0.721% and an energy conversion efficiency (η) of 18.37%, but the same 47Ω. For solar cells manufactured by wet etching the light-receiving surface with a resistance of / sq, the short-circuit current density (Jsc) of 40.58 mA / cm ² , the open voltage (Voc) of 0.623 V, the performance index (FF) of 0.676%, and It has an energy conversion efficiency (η) of 17.1%, and the front emitter layer has a low 25? / Sq. Without etching the light receiving surface. The case of the solar cell, has a Figure of Merit (FF), and energy conversion efficiency (η) of 17.03% of the short-circuit current density (Jsc), open-circuit voltage of 0.611 V (Voc), 0.752% of 37.06 mA / cm ² having a Confirmed.

As described above, by controlling the resistance of the front emitter layer, the open current and the short-circuit current density can be improved, and further, the fidelity can be further improved by adjusting the resistance of the front emitter layer using dry etching.

After dry etching is performed in the partial etching step, cleaning using a RCA (Radio Corporation of America) cleaning method may be further performed. Specifically, RCA cleaning methods used for cleaning substrates in the semiconductor field include sulfuric acid (H ₂ SO ₄ ), hydrochloric acid (HCI), ammonium hydroxide (NH 4 _O H), hydrofluoric acid (HF), and hydrogen peroxide (H ₂ O ₂ ). A method of removing oxides and metal impurities using a combination of chemical solutions, and the cleaning step may be performed using a conventional RCA cleaning method. At this time, during the cleaning using the RCA cleaning method, SC-1 cleaning may be performed, followed by SC-2 cleaning.

As described above, the manufacturing method according to the present invention uniformly forms the surface layer of the second semiconductor impurity on the two opposing surfaces of the semiconductor surface and the inner surface of the via hole by the doping step, and then, using the selective etching step, n The doping layer of the non-etched region of the etching-resist pattern 300 is etched away so that a high concentration of emitter layer is formed only in the region where the type electrodes (finger electrode and bus bar electrode) are formed and doped using the partial etching step. The concentration of the front emitter layer 221 may be formed.

In the manufacturing method according to an embodiment of the present invention, after the partial etching step, preferably, the cleaning step is performed, as shown in Figure 1, to form a passivation film 500 on the surface, the other one The dielectric film forming step of forming the anti-reflection film 400 on the surface may be further performed.

In detail, after the second impurity concentration of the front emitter layer 220 is controlled by the partial etching step, an anti-reflection film 400 is formed on the front emitter layer, and the patterned back emitter layer 210 is formed. The dielectric film forming step of forming the passivation film 500 on one surface of the formed semiconductor substrate may be performed.

The anti-reflection film 400 formed on one surface of the semiconductor substrate 100 on which the front emitter layer 220 is formed serves to prevent the light received into the solar cell from escaping back to the outside of the solar cell and the semiconductor. It refers to a film that performs both the passivation of the surface defects that act as a trap site of the electrons on the surface of the substrate 100.

As in the case in which the anti-reflection action and the passivation action are performed by a single material, the anti-reflection film 400 may be a single layer thin film. When the anti-reflection action and the passivation action are performed by different materials, The anti-reflection film 400 may be a multilayer thin film in which different material layers are stacked.

In addition, even when the anti-reflection action and the passivation action are performed by a single material, in order to maximize the anti-reflection action and passivate defects effectively, the anti-reflection film 400 may be formed by stacking different material layers. It may be a multilayer thin film.

For example, the anti-reflection film 400 may be selected from a semiconductor oxide, a semiconductor nitride, a semiconductor oxide containing nitrogen, a semiconductor nitride containing hydrogen, Al ₂ O ₃ , MgF ₂ , ZnS, MgF ₂ , TiO _2, and CeO ₂ . It may be a single film or a multilayer film in which two or more films selected therefrom are stacked.

As an example of the silicon solar cell, the antireflection film 400 of the single layer thin film may be a silicon nitride film, a silicon nitride film containing hydrogen or a silicon oxynitride film, and the antireflection film 400 of the multilayer thin film may be formed of silicon oxide, And a laminated thin film in which at least two films selected from silicon nitride, Al ₂ O ₃ , MgF ₂ , ZnS, MgF ₂ , TiO ₂ and CeO ₂ are laminated.

The passivation film 500 formed on the other surface on which the patterned back emitter layer 210 of the semiconductor substrate 100 is formed serves as a trap site for electrons on the surface of the semiconductor substrate 100. It refers to a film that serves to passivate surface defects.

For example, the passivation film 500 may include a semiconductor oxide, a semiconductor nitride, a semiconductor oxide containing nitrogen, a semiconductor nitride containing hydrogen, alumina, titania, or a laminated thin film thereof.

As an example of a silicon solar cell, the passivation film 500 may be a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, an alumina film, or a silicon oxynitride film, and a passivation film 500 of a multilayer thin film. ) Includes a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, an alumina film, a silicon oxynitride film, and a laminated thin film in which two or more films selected from titania are stacked.

The anti-reflection film 400 and the passivation film 500 may be formed using a thin film formation method commonly used in a semiconductor passivation process, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma deposition (PECVD) and thermal evaporation may be formed by one or more selected methods, and may also be formed by a general printing process using ink or paste.

As shown in the example of FIG. 3, after the anti-reflection film 400 and the passivation film 500 are formed in the dielectric film forming step, the passivation film 500 partially positioned on the patterned back emitter layer is partially formed. A passivation film partial removal step for removal is performed.

Partial removal of the passivation film 500 may be performed by application of an etching paste for etching the passivation film.

The etching paste may be any paste capable of etching the passivation layer 500. For example, the etching paste may use a product including a SolarEtch series (MERCK).

Application of the etching paste may be made by printing. Specifically, the etch paste is applied using printing methods such as inkjet printing, masking, stencils, screen printing, and direct printing of the etch paste simplifies process conditions, reduces production time, and increases manufacturing costs and production efficiency. Let's do it.

The etching paste is applied on the passivation layer in a predetermined pattern, so that the etched passivation layer 510 is formed as the passivation layer of the coated region is partially etched away.

The etching paste is applied in a shape and position corresponding to the shape and position of the p-type finger electrode, preferably the p-type finger electrode and the p-type busbar electrode, which are connected to the p-type semiconductor substrate, thereby exposing the p-type semiconductor to the surface. Be sure to

That is, in the passivation film removing step, the etching paste is etched so that the p-type semiconductor region by the semiconductor substrate corresponds to the shape and position of the p-type finger electrode, preferably the p-type finger electrode and the p-type busbar electrode. do.

A p-type electrode 600 is formed in a p-type semiconductor region surface exposed by removing the passivation layer. The p-type electrode 600 includes a plurality of band-shaped finger electrodes and the plurality of finger electrodes spaced apart from each other. It may include a bus bar electrode electrically connected to each other.

The n-type electrode (n-type finger electrode and n-type busbar electrode) and the p-type electrode (p-type finger electrode and p-type busbar electrode) may each have a fish bone shape, and the p-type electrode is n It may have an interdigitate structure with the type electrode.

As described above, for the formation of the second impurity layer by one step doping, the formation of a high concentration backside emitter layer by selective etching, the formation of a low concentration front surface emitter layer by partial etching, the formation of a dielectric film and the formation of a p-type electrode The passivation film removal configuration is a simple process of partial etching using one step doping and printing method compared to the conventional solar cell manufacturing process, and has a high short circuit current, an open voltage and fidelity, and prevents generation of leakage current when forming electrodes. It is possible to manufacture a high efficiency solar cell in a short time by a simple process, resulting in cost reduction and excellent productivity.

After the passivation film removing step is performed, an electrode forming step of forming the n-type electrode and the p-type electrode is performed. In detail, the n-type electrode material is applied, the p-type electrode material is applied, and then heat-treated to apply the n-type electrode. And a p-type electrode.

More specifically, the passivation film is removed to apply a p-type electrode material over the p-type region (surface exposed p-type semiconductor substrate) exposed to the surface, and n on the passivation film on the patterned back emitter layer 210. A type electrode material is applied and heat treated to connect the p-type electrode 600 to the semiconductor substrate, and the n-type electrodes 710 and 720 are connected to the patterned back emitter layer 210 by punch-through. .

The application of the p-type electrode material and the application of the n-type electrode material may be performed independently of each other by printing of a paste containing the electrode material, and the printing may include inkjet printing, masking, stencil or screen printing.

In forming the p-type electrode 600, the p-type electrode material preferably contains aluminum to form a back surface field (BSF) 610 by heat treatment and to bind the semiconductor substrate.

The n-type electrode includes a first electrode 711 and a second electrode 720, wherein the first electrode 711 is the patterned back surface through a punch through phenomenon passing through the passivation film The second electrode 720 is connected to the rotor layer 210 and is formed on the first electrode 711 so as not to penetrate the passivation layer and cover the first electrode 711.

The first electrode (the first electrode before the heat treatment, 710) is a connection electrode that penetrates the passivation film and connects with the patterned back emitter layer, and minimizes damage of the passivation film and electrically connects the patterned back emitter layer. The second electrode 720 is configured to reduce an increase in resistance caused by the extreme microstructure of the first electrode 710.

The first electrode penetrating the passivation film means that the material of the first electrode is interfacially reacted with the passivation film so that the material of the first electrode is in physical contact with the patterned back emitter layer. The through means means that the material of the first electrode comes into contact with the patterned back emitter layer. For a detailed mechanism related to the punch through phenomenon, see J. Hoomstra, et al., 31st IEEE PVSC Florida 2005.

In detail, penetration of the passivation film is performed by etching the passivation film by subjecting the electrode material of the first electrode (the first electrode before heat treatment) 710 applied on the passivation film to the redox reaction at the interface with the passivation film by thermal energy. The conductive material contained in the first electrode material is melted and recrystallized to contact the patterned back emitter layer through a region where the passivation film is etched.

For example, the first electrode material may include a glass frit for etching the passivation film through an interfacial reaction, and may include a conductive metal material that passes through the passivation film etched through melting and recrystallization to form a low resistance passage.

Representative examples of the conductive metal material contained in the first electrode include silver (Ag), copper (Cu), titanium (Ti), gold (Au), tungsten (W), nickel (Ni), chromium (Cr), and molybdenum One or more materials selected from (Mo), platinum (Pt), lead (Pb), palladium (Pd) and their alloys, and in terms of low melting point and good electrical conductivity, silver, copper, nickel, aluminum or It is preferable that it is these alloys. As a glass frit contained in the first electrode to etch the passivation film, lead glass containing lead oxide, bismuth oxide, and boron oxide, which are commonly used to form a solar cell electrode, may be used. Examples of the lead glass frit include PbO-SiO ₂ -B ₂ O ₃ -Al ₂ O ₃ glass frit, PbO-SiO ₂ -B ₂ O ₃ -Al ₂ O ₃ -ZrO ₂ glass frit, PbO-SiO ₂ -B ₂ O ₃ -Al ₂ O ₃ -ZnO glass frit or PbO-SiO ₂ -B ₂ O ₃ -Al ₂ O ₃ -ZnO-TiO ₂ glass frit, the lead-free glass-based frit, Bi ₂ O ₃ -ZnO-SiO ₂ -B ₂ O ₃ -Al ₂ O ₃ glass frit, Bi ₂ O ₃ -SrO-SiO ₂ -B ₂ O ₃ -Al ₂ O ₃ glass frit, Bi ₂ O ₃ -ZnO-SiO ₂ -B ₂ O ₃ -La ₂ O ₃ -Al ₂ O ₃ glass frit, Bi ₂ O ₃ -ZnO-SiO ₂ -B ₂ O ₃ -TiO ₂ glass frit, Bi ₂ O ₃ -SiO ₂ -B ₂ O ₃ -SrO glass frit or Bi ₂ O ₃ -SiO ₂ -B ₂ O ₃ -ZnO-SrO glass frit. In this case, the lead glass or the lead-free glass is one or more additives selected from Ta ₂ O ₅ , Sb ₂ O ₅ , HfO ₂ , In ₂ O ₃ , Ga ₂ O ₃ , Y ₂ O ₃ and Yb ₂ O ₃ It may further contain. The first electrode preferably contains 3 to 5% by weight of the lead glass or lead-free glass.

The first electrode (the first electrode before the heat treatment 710) may have a plurality of dot shapes or a fine line shape that are uniformly arranged.

The second electrode 720 is formed on the first electrode 710 before the first electrode heat treatment 710 and the passivation layer so as to cover the first electrode (the first electrode before the heat treatment 710). Covering the first electrode means that all surfaces of the first electrode are wrapped in the second electrode.

Among the first and second electrodes, the second electrode does not penetrate the passivation film, and only the first electrode selectively penetrates the passivation film to connect with the substrate, which means that the second electrode does not penetrate the passivation film. Means that the material of the second electrode does not interfacially react with the passivation film, and even when thermal energy is applied, the punch-through of the passivation film by the second electrode material does not occur.

Preferably, the second electrode 720 contains a glass frit and a conductive metal material which do not interface react with the passivation film.

The glass frit contained in the second electrode does not interface with the passivation layer, improves the physical bonding strength of the second electrode, and increases the interfacial bonding force between the patterned back emitter layer and the first electrode. .

It is preferable that the conductive material contained in the second electrode is a conductive material that smoothly densifies and grows particles by heat applied for punch-through of the first electrode.

Representative examples of the conductive material contained in the second electrode include silver (Ag), copper (Cu), titanium (Ti), gold (Au), tungsten (W), nickel (Ni), chromium (Cr), and molybdenum (Mo). ), Platinum (Pt), lead (Pb), palladium (Pd) and alloys of one or more selected from these, and the glass frit contained in the second electrode does not etch the passivation film is B, It is preferable that it is a normal silica type or phosphate type glass which does not contain Bi and Pb. More preferably, the glass frit contained in the second electrode has a vitrification temperature of 1.2 to 2 times based on the vitrification temperature (Tg) of the glass frit contained in the first electrode and does not contain B, Bi, and Pb. It is preferable that it is a silica type or a phosphate type glass.

The silica-based glass frit has a mesh forming component of SiO ₂ , Li ₂ O, Na ₂ O, K ₂ O, MgO, CaO, BaO, SrO, ZnO, Al ₂ O ₃ , TiO ₂ , ZrO ₂ , Ta ₂ One or two or more selected from O ₅ , Sb ₂ O ₅ , HfO ₂ , In ₂ O ₃ , Ga ₂ O ₃ , Y ₂ O ₃ and Yb ₂ O ₃ , wherein the phosphate-based glass frit is P ₂ O ₅ -V ₂ O ₅ of vanadium-phosphate-based glass or _{P 2 O 5 -ZnO-Sb 2} O 3 of a zinc-antimony-and phosphate-based glass, the phosphate-based glass frit is _{K 2 O, Fe 2 O 3} , Preference is given to containing one or more substances selected from Sb ₂ O ₃ , ZnO, TiO ₂ , Al ₂ O ₃ and WO ₃ . In this case, the second electrode preferably contains 3 to 5% by weight of the silica-based or phosphate-based glass.

The second electrode 720 has a strip covering a plurality of dot-shaped first electrodes (first electrode before heat treatment 710) or a first electrode (first electrode before heat treatment 710) having a fine line shape. It may be shaped.

The dot diameter or the width of the fine line of the first electrode (the first electrode before the heat treatment 710) may be 30 μm to 300 μm, and the width of the second electrode 720 may be 50 μm to 1,000 μm. This is a width that can lower the resistance increased by the first electrode while minimizing the reduction of the light receiving area by the second electrode. In detail, an n-type electrode including the first electrode and the second electrode is 3 to 6x10 ^-6 Ωcm. It is the width that can have resistance.

After printing the first electrode (the first electrode 710 before the heat treatment), forming the second electrode 720 to cover the first electrode on the first electrode, and then heat treatment, the first electrode and the second electrode Of these, only the first electrode is selectively connected with the patterned back emitter layer. At this time, printing of the p-type electrode is also performed before the heat treatment, such that the first electrode 711 and the first punched through a single heat treatment are performed. It is preferable that the n-type electrode including the second electrode 720 surrounding the electrode, the p-type electrode 600, and the BSF 610 are formed.

As described above, in the solar cell according to the present invention, an n-type electrode collecting electrons or holes generated by irradiation of light includes the first electrode and the second electrode.

The n-type electrode collecting electrons or holes includes an n-type finger electrode and / or an n-type bus bar electrode of the solar cell.

In this case, a soldering layer for forming a solar cell module for connecting two or more solar cells in series or in parallel to each other may be further formed on the n-type electrode including the first electrode and the second electrode. In detail, in order to connect the electrodes of two or more solar cells in series or in parallel with each other, a conductive ribbon is soldered and attached to the electrodes, and a soldering layer for soldering may be further formed on the electrodes.

In detail, the soldering layer may improve the welding property between the conductive ribbon and the electrode and the wettability of the solder material during the soldering of the conductive ribbon; and the n-type electrode including the first electrode and the second electrode. It is to let.

The conductive ribbon may use a conductive ribbon that is commonly used for modularization of solar cells, and a non-limiting example of the conductive ribbon may be a copper ribbon plated with a soldering material such as tin lead or silver. The soldering layer may be a soldering layer that is commonly used to improve bonding strength and wettability with a soldering material during solar cell modularization, and the soldering layer may be appropriately selected in consideration of the soldering material.

However, it is a matter of course that the above-described modularization of the solar cell can be made by using a thermally, optically or chemically curable conductive adhesive instead of soldering.

In the method of manufacturing a solar cell according to the present invention, after the hole forming step and before the etching resist forming step, a surface texturing step of etching the semiconductor substrate 100 to form fine irregularities on the surface may be further performed. have. The etching includes dry or wet etching, and the organized surface includes a surface in which a plurality of inverse pyramidal fine irregularities are arranged.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Those skilled in the art will recognize that many modifications and variations are possible in light of the above teachings.

Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (10)

a) forming a via hole to penetrate two opposing surfaces of the first conductive semiconductor substrate;
b) a doping step of forming a second conductive layer by doping a second conductive impurity on the surface of the semiconductor substrate;
c) an etch-resist forming step of forming an etch-resist pattern on one of the two opposing surfaces to cover the opening of the via hole;
d) etching the one surface with the etch-resist pattern with an etch mask to remove a second conductive layer present in one surface area where the etch-resist pattern is not formed; And
e) a partial etching step of controlling the impurity concentration of the second conductive layer existing on the other surface by partially removing the second conductive layer existing on the other surface opposite to the one surface;
Method of manufacturing a back electrode solar cell comprising a. The method of claim 1,
f) forming a passivation film on the one surface and forming an anti-reflection film on the other surface;
g) a passivation film removing step of partially applying an etching paste for etching a passivation film on the one surface to expose a semiconductor substrate region from which the second conductive layer is removed by the selective etching step; And
h) an electrode forming step of forming a first electrode connected to the exposed semiconductor substrate region and a second electrode connected to the second conductive layer by punch-through on the one surface;
Method of manufacturing a back electrode solar cell further comprising. The method of claim 1,
And a step difference between the surface of the semiconductor substrate to which the second conductive layer is removed by the selective etching step and the second conductive layer under the etching-resist pattern is formed. The method of claim 1,
The sheet resistance of the second conductive layer formed in the doping step is 10 to 40 Ω / sq., And the partial etching step is such that the sheet resistance of the second conductive layer located on the other surface is 30 to 150 Ω / sq. A method of manufacturing a back electrode solar cell that partially removes a second conductive layer on a surface. The method of claim 1,
The partial etching is a method of manufacturing a back electrode solar cell is performed by dry etching (Dry etching). 6. The method of claim 5,
And the thickness of the second conductive layer formed on the inner surface of the via hole in the doping step is controlled by the partial etching. 6. The method of claim 5,
And the second conductive layer formed on the inner surface of the via hole is reduced in thickness from one surface to the other surface by the partial etching. 6. The method of claim 5,
After the partial etching is carried out, the cleaning method using a RCA (Radio Corporation of America) cleaning method is further performed. The method of claim 1,
The etching resist pattern is a manufacturing method of a back electrode solar cell formed by a printing process. A rear electrode solar cell manufactured by the manufacturing method of any one of claims 1 to 9.

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