KR101339953B1 - Method for producing carbon nanotube semiconductor device - Google Patents

Method for producing carbon nanotube semiconductor device Download PDF

Info

Publication number
KR101339953B1
KR101339953B1 KR1020130002440A KR20130002440A KR101339953B1 KR 101339953 B1 KR101339953 B1 KR 101339953B1 KR 1020130002440 A KR1020130002440 A KR 1020130002440A KR 20130002440 A KR20130002440 A KR 20130002440A KR 101339953 B1 KR101339953 B1 KR 101339953B1
Authority
KR
South Korea
Prior art keywords
carbon nanotubes
semiconductor device
source
drain electrode
photosensitive material
Prior art date
Application number
KR1020130002440A
Other languages
Korean (ko)
Inventor
배명호
김남
Original Assignee
한국표준과학연구원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 한국표준과학연구원 filed Critical 한국표준과학연구원
Priority to KR1020130002440A priority Critical patent/KR101339953B1/en
Application granted granted Critical
Publication of KR101339953B1 publication Critical patent/KR101339953B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2

Abstract

A method of manufacturing a carbon nanotube semiconductor device is disclosed. The carbon nanotube semiconductor device manufacturing method includes applying a photosensitive material to a semiconductor device including a channel layer including an insulator substrate, a source-drain electrode, and carbon nanotubes; Applying a predetermined voltage to the source-drain electrode to remove the photosensitive material coated on the metallic carbon nanotubes in the channel layer, and performing heat treatment on the semiconductor device for a predetermined time to remove the metallic carbon nanotubes. Steps.

Description

Carbon nanotube semiconductor device manufacturing method {METHOD FOR PRODUCING CARBON NANOTUBE SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a carbon nanotube semiconductor device.

Carbon nanotube transistors are nanowire field effect transistors. They are complementary metals (CMOS) due to their excellent electron and hole mobility, heat and light stability, and unique flexibility. Research has been actively conducted in various fields such as various semiconductor devices including various types of memory devices including oxide semiconductor inverters and various memory devices.

Carbon nanotubes can be classified into single-walled carbon nanotubes (SWCNTs), double-walled carbon nanotubes (DWCNTs), multi-walled carbon nanotubes (MWCNTs), ropes, carbon nanohorns, and fullerene-embedded types. Tubes and metallic carbon nanotubes are present in a mixture.

For example, in the case of single-walled carbon nanotubes, about one third is metallic carbon nanotubes and the other is semiconducting carbon nanotubes.

In the case of manufacturing a semiconductor device using carbon nanotubes, if a high on-off ratio is required or a semiconductor gap is required, there is a problem that its use is limited due to metallic carbon nanotubes.

At this time, as a method for selectively removing the metallic carbon nanotubes, a high voltage is applied to the source-drain electrode to remove the metallic carbon nanotubes having low resistance by heat.

However, this method requires a high temperature of about 600 degrees or more, so that the insulator substrate layer may be damaged by high heat.

Korean Patent Publication No. 2012-0126585 discloses a method for controlling the amount of carbon nanotubes that can secure the adsorption amount of carbon nanotubes uniformly through an oxygen plasma treatment process, and a method of manufacturing carbon nanotube devices using the same. However, in this case, there is a problem that the insulator substrate and the semiconducting carbon nanotubes are also directly affected by the oxygen plasma treatment process.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a carbon nanotube semiconductor device capable of selectively removing metallic carbon nanotubes while protecting an insulator substrate from external heat and at the same time preventing performance degradation on the semiconductor device. have.

According to an aspect of the present invention, the method includes: applying a photosensitive material to a semiconductor device including a channel layer including an insulator substrate, a source-drain electrode, and carbon nanotubes; Applying a predetermined voltage to the source-drain electrode to remove the photosensitive material coated on the metallic carbon nanotubes in the channel layer, and performing heat treatment on the semiconductor device for a predetermined time to remove the metallic carbon nanotubes. It provides a carbon nanotube semiconductor device manufacturing method comprising the step.

The method of manufacturing a carbon nanotube semiconductor device according to the present invention can selectively remove metallic carbon nanotubes while protecting an insulator substrate from external heat and preventing performance degradation on the semiconductor device.

1 to 6 are cross-sectional views illustrating a method for manufacturing a carbon nanotube semiconductor device according to an embodiment of the present invention;
7 to 9 are plan views illustrating a method of manufacturing a carbon nanotube semiconductor device according to an embodiment of the present invention.

The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated and described in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms including ordinal, such as second, first, etc., may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be referred to as a first component, and similarly, the first component may also be referred to as a second component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, wherein like or corresponding elements are denoted by the same reference numerals, and redundant description thereof will be omitted.

1 to 6 are cross-sectional views illustrating a method for manufacturing a carbon nanotube semiconductor device according to an embodiment of the present invention, and FIGS. 7 to 9 illustrate a method for manufacturing a carbon nanotube semiconductor device according to an embodiment of the present invention. It is a top view for doing this.

A method of manufacturing a carbon nanotube semiconductor device according to an embodiment of the present invention includes a photosensitive material 40 in a semiconductor device including an insulator substrate 10, a source-drain electrode 30, and a channel layer 20 formed of carbon nanotubes. ) Applying a predetermined voltage to the source-drain electrode 30 to remove the photosensitive material 40 coated on the metallic carbon nanotubes 20 (b) of the channel layer 20, Performing heat treatment on the semiconductor device for a predetermined time to remove the metallic carbon nanotubes 20 (b), removing the photosensitive material 40, and gate insulating layer 50 on the source-drain electrode 30. And forming the gate electrode 60 on the gate insulating layer 50.

First, referring to FIG. 1, an insulator substrate 10 having a channel layer 20 and a source-drain electrode 30 formed thereon is provided.

The insulator substrate 10 may be, for example, a silicon oxide substrate.

The source-drain electrode 30 may be formed of a commonly used electrode material, and may be, for example, a metal, an alloy, or an indium-tin-oxide (ITO), indium-zinc-oxide (IZO), SnO 2, or ZnO 2. It may be formed of a conductive metal oxide such as.

The channel layer 20 is a mixture of semiconducting carbon nanotubes and metallic carbon nanotubes, such as single-walled carbon nanotubes (SWCNT), double-walled carbon nanotubes (DWCNT), multi-walled carbon nanotubes (MWCNT), rope type, It may be one of carbon nanohorn and fullerene inclusion type.

Referring to FIG. 7, a source-drain electrode 30 is formed on the insulator substrate 10, and the semiconductor carbon nanotubes 20 (a) and the metallic carbon nanotubes 20 (b) are interposed therebetween. It can be seen that the channel layer 20 including) is formed.

Next, referring to FIG. 2, the photosensitive material 40 is coated on the semiconductor device.

The photosensitive material 40 is applied to the upper surface of the substrate and is applied to cover the channel layer 20 and the source-drain electrode 30 entirely.

The photosensitive material 40 may be, for example, a polymer-based material, and may be polymethyl methacrylate (PMMA).

However, the photosensitive material 40 according to the present invention is not limited to methyl polymethacrylate, and it is understood that the polymer-based material may be evaporated in an environment of about 300 degrees or less.

Next, referring to FIG. 3, a voltage is applied to both ends of the source-drain electrode 30.

When a voltage is applied to both ends of the source-drain electrode 30, a current flows in the channel layer 20 electrically connected to the source-drain electrode 30.

When current flows through the channel layer 20, heat is generated by internal resistance of the channel layer 20.

At this time, a larger amount of current flows through the metallic carbon nanotubes 20 (b) having a smaller internal resistance than the semiconducting carbon nanotubes 20 (a) with respect to the same source-drain electrode 30. Therefore, more heat is generated in the metallic carbon nanotubes 20 (b), and thus the photosensitive material 40 coated around the metallic carbon nanotubes 20 (b) is evaporated first.

As such, when a predetermined voltage is applied to the source-drain electrode 30, only the photosensitive material 40 coated around the metallic carbon nanotubes 20 (b) may be selectively evaporated.

When the photosensitive material 40 is polymethyl methacrylate, the voltage applied to the source-drain electrode 30 is adjusted so that the temperature of the metallic carbon nanotubes 20 (b) is about 300 degrees.

Referring to FIG. 8, it can be seen that only the photosensitive material 40 coated on the metallic carbon nanotubes 20 (b) is selectively removed and exposed to the outside.

Next, referring to FIG. 4, heat treatment is applied to a semiconductor device in which the metallic carbon nanotubes 20 (b) are exposed to the outside.

When the heat treatment is performed on the semiconductor device, only the metallic carbon nanotubes 20 (b) exposed to the outside may be selectively removed.

The heat treatment can be, for example, an oxygen plasma treatment process.

At this time, the oxygen plasma treatment process should be performed before the insulator substrate 10 or the semiconducting carbon nanotubes 20 (a) are exposed to the outside. That is, the photosensitive material 40 coated on the insulator substrate 10 or the semiconducting carbon nanotubes 20 (a) must be performed until all of them are evaporated by the oxygen plasma treatment process.

For this purpose, when the resistance value or the current value is monitored in real time between the source and drain electrodes 30 by a resistance meter or a current meter, a finer oxygen plasma treatment process is possible. For example, when the oxygen plasma treatment is performed while a predetermined resistance value or current value range is set in advance, when the oxygen plasma treatment falls within this range, an automatic control or a user stops the oxygen plasma treatment, thereby ensuring a stable and reliable process.

According to yet another method, a database of current values or resistance values according to the oxygen plasma treatment time may be used. In other words, the resistance value or the current value is measured before and after each plasma treatment and stored in a database. Therefore, the database stores information on how much the original resistance value or current value is lowered according to the oxygen plasma treatment time. Using this database, fine control is possible by adjusting only the oxygen plasma treatment time.

Next, referring to FIG. 5, the photosensitive material 40 not removed by heat treatment is removed.

If the heat treatment process is performed until the insulator substrate 10 or the semiconducting carbon nanotubes 20 (a) is exposed to the outside, the insulator substrate 10, the semiconducting carbon nanotubes 20 (a) and the source-drain electrodes The applied photosensitive material 40 remains on 30.

The photosensitive material 40 may be removed using a mechanical or chemical method, for example, may be removed by applying acetone.

Referring to FIG. 9, after all of the applied photosensitive material 40 has been removed, it can be seen that only the channel layer 20 including the source-drain electrode 30 and the carbonaceous nanotubes remains on the substrate.

Next, referring to FIG. 6, the gate insulating layer 50 is formed on the source-drain electrode 30, and the gate electrode 60 is formed on the gate insulating layer 50.

For example, the gate insulating layer 50 may be formed of Al 2 O 3 .

The gate electrode 60 may be formed of a commonly used electrode material, and may be a metal, an alloy, or a conductive metal oxide such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), SnO 2, or ZnO 2 . It can be formed as.

Alternatively, the gate electrode 60 may be formed in the form of a back electrode, and in this case, the gate electrode 60 may be formed between the insulator substrate 10 and the source-drain electrode 30.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

10: insulator substrate
20: channel layer
30: source-drain electrode
40: photosensitive material
50: gate insulating layer
60: gate electrode

Claims (6)

Applying a photosensitive material to a semiconductor device comprising an insulator substrate, a source-drain electrode and a channel layer comprised of carbon nanotubes;
Applying a predetermined voltage to the source-drain electrode to remove the photosensitive material coated on the metallic carbon nanotubes in the channel layer;
And removing the metallic carbon nanotubes by performing heat treatment on the semiconductor device for a predetermined time.
The method of claim 1,
Removing the photosensitive material,
And applying a predetermined voltage to the source-drain electrode such that the temperature of the metallic carbon nanotubes is 200 to 300 degrees.
The method of claim 1,
The heat treatment is an oxygen plasma (Oxygen Plasma) treatment process carbon nanotube semiconductor device manufacturing method.
The method of claim 3,
Removing the metallic carbon nanotubes,
A method of manufacturing a carbon nanotube semiconductor device, which is performed until semiconductor carbon nanotubes in the insulator substrate or the channel layer are exposed to the outside.
The method of claim 1,
Carbon nanotube semiconductor device manufacturing method further comprising the step of removing the photosensitive material.
The method of claim 5,
Forming a gate insulating layer on the source-drain electrode; and
Forming a gate electrode on the gate insulating layer further comprising a carbon nanotube semiconductor device manufacturing method.
KR1020130002440A 2013-01-09 2013-01-09 Method for producing carbon nanotube semiconductor device KR101339953B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020130002440A KR101339953B1 (en) 2013-01-09 2013-01-09 Method for producing carbon nanotube semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130002440A KR101339953B1 (en) 2013-01-09 2013-01-09 Method for producing carbon nanotube semiconductor device

Publications (1)

Publication Number Publication Date
KR101339953B1 true KR101339953B1 (en) 2013-12-10

Family

ID=49987985

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130002440A KR101339953B1 (en) 2013-01-09 2013-01-09 Method for producing carbon nanotube semiconductor device

Country Status (1)

Country Link
KR (1) KR101339953B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100847467B1 (en) 2003-10-17 2008-07-21 인텔 코포레이션 Method of sorting carbon nanotubes

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100847467B1 (en) 2003-10-17 2008-07-21 인텔 코포레이션 Method of sorting carbon nanotubes

Similar Documents

Publication Publication Date Title
Xu et al. Highly stretchable carbon nanotube transistors with ion gel gate dielectrics
Zhao et al. Photocatalytic reduction of graphene oxide–TiO2 nanocomposites for improving resistive‐switching memory behaviors
Bhowmick et al. Quantum dots and nanoroads of graphene embedded in hexagonal boron nitride
WO2012024544A3 (en) Variable resistance memory element and fabrication methods
Fan et al. Effect of electrode twisting on electronic transport properties of atomic carbon wires
Jiang et al. Impact of Thickness on Contact Issues for Pinning Effect in Black Phosphorus Field‐Effect Transistors
Cao et al. Origins and characteristics of the threshold voltage variability of quasiballistic single-walled carbon nanotube field-effect transistors
Yu et al. Modulating electronic transport properties of carbon nanotubes to improve the thermoelectric power factor via nanoparticle decoration
Jiménez et al. A simple drain current model for Schottky-barrier carbon nanotube field effect transistors
TW200717657A (en) Semiconductor device and fabrication method thereof
Cocchi et al. Designing all-graphene nanojunctions by covalent functionalization
JP6469484B2 (en) Strain sensor
Wali et al. Satisfiability attack-resistant camouflaged two-dimensional heterostructure devices
Hierold et al. Carbon nanotube devices: properties, modeling, integration and applications
Tybrandt et al. Multilayer patterning of high resolution intrinsically stretchable electronics
Li et al. Diode rectification and negative differential resistance of dipyrimidinyl–diphenyl molecular junctions
US8278658B2 (en) Electrically connected graphene-metal electrode device, and electronic device, electronic integrated circuit and electro-optical integrated circuit using same
Kim et al. Analysis of the interface characteristics of CVD-grown monolayer MoS2 by noise measurements
Chen et al. Variability in output characteristics of single-walled carbon nanotube thin-film transistors
KR101339953B1 (en) Method for producing carbon nanotube semiconductor device
Sardarzadeh et al. Adsorption of SO2, H2S, NH3, PH3, and AsH3 Gas Molecules on Pristine Armchair Phosphorene Nanoribbon: A First‐Principles Study
Lu et al. All-carbon thin-film transistors using water-only printing
Agrawal et al. Multishell carrier transport in multiwalled carbon nanotubes
Pimparkar et al. Performance assessment of subpercolating nanobundle network thin-film transistors by an analytical model
Brunel et al. Integrating multiple resistive memory devices on a single carbon nanotube

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20161107

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee