KR101328261B1 - 3 dimensional resistive random access memory and operating method thereof - Google Patents

Abstract

The present invention relates to a three-dimensional resistance change memory and a driving method thereof. The three-dimensional resistance change memory according to the present invention comprises a plurality of bit lines spaced apart in parallel directions, a plurality of vertical memory strings which are branched to the bit lines, and comprise a plurality of series of memory cells, the vertical memory. A resistive memory material attached to a side end of the string, a plurality of word lines respectively corresponding to the plurality of memory cells and coupled in a vertical direction to the resistive memory material, and formed on top of the vertical memory string, and different bit lines An upper gate extended and coupled in a direction crossing the vertical memory string connected to the upper gate, and a lower gate formed at a lower end of the vertical memory string and extended and coupled in a direction crossing the vertical memory string connected to different bit lines. It includes.

Description

3D resistive change memory and its driving method {3 dimensional resistive random access memory and operating method

The present invention relates to a three-dimensional resistance change memory and a driving method thereof, and more particularly, to a nonvolatile variable resistance memory having a three-dimensional structure suitable for a large-capacity bipolar resistance memory.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. Nonvolatile memory devices include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), Flash memory devices, Phase-change RAM (PRAM), and Magnetic RAM (MRAM). ), Resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like. Flash memory devices are largely divided into NOR type and NAND type.

In particular, with the acceleration of power, high speed, and large capacity, the current NAND flash memory will not be able to develop devices due to physical limitations at 10nm in the next five years, which will overcome the physical scaling limits of the patterning technology currently used. There is a need for a three-dimensional nonvolatile memory.

The background technology of the present invention is described in Republic of Korea Patent No. 735533 (2007. 06. 28).

Accordingly, an object of the present invention is to provide a resistance change memory having a three-dimensional structure suitable for a large capacity bipolar resistance memory and a driving method thereof.

According to an embodiment of the present invention, a three-dimensional variable resistance memory includes a plurality of bit lines spaced apart in parallel directions, branched to the bit lines, and a plurality of serial memory cells. A plurality of vertical memory strings, a resistive memory material attached to a side end of the vertical memory string, a plurality of word lines respectively corresponding to the plurality of memory cells and coupled in a vertical direction to the resistive memory material, the vertical memory string An upper gate formed at an upper end of the upper gate and extending in a direction intersecting with a vertical memory string connected to different bit lines, and a vertical memory string formed at a lower end of the vertical memory string and connected to different bit lines; Including a bottom gate extending and joined in an intersecting direction .

The vertical memory string may include a first string having a first polarity and a second string and a third string coupled to both ends of the first string and having a second polarity.

The word line has the first polarity, the second string and the word line are connected through the resistive memory material, and may form a PN junction diode.

The first string, the second string and the word line may form a PNP bipolar transistor or an NPN bipolar transistor.

As described above, according to the present invention, by forming a three-dimensional memory structure with a three-dimensional architecture structure for bipolar resistive memory that has an advantage in operating stability, such as operating current and repeatability, the NAND flash memory, which is expected to reach the limit in the future, is used as the resistive memory. It is possible to replace.

1A is a block diagram illustrating a 3D variable resistance memory according to an exemplary embodiment of the present invention.
FIG. 1B is a block diagram showing a part of the three-dimensional variable resistance memory shown in FIG. 1A.
FIG. 1C shows an equivalent circuit for the three-dimensional variable resistance memory shown in FIGS. 1A and 1B.
2A and 2B are diagrams for explaining a preprocessing process of writing to a three-dimensional variable resistance memory according to a first embodiment of the present invention.
3A and 3B are diagrams for describing a step of writing data in a three-dimensional variable resistance memory according to a first embodiment of the present invention.
FIG. 4 is a partial block diagram of a three-dimensional variable resistance memory for explaining a process of erasing data stored in the three-dimensional variable resistance memory according to the second embodiment of the present invention.
FIG. 5 is an equivalent circuit diagram of a three-dimensional variable resistance memory for explaining a process of reading data stored in the three-dimensional variable resistance memory according to the third embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In addition, the expression that voltage is maintained throughout the specification indicates that even if the potential difference between two specific points changes over time, the change is within an allowable range in the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Include cases by. In addition, since the threshold voltage of a semiconductor device (transistor, diode, etc.) is very low compared to the discharge voltage, the threshold voltage is regarded as 0V and approximated.

In addition, the switches described in the entire specification include all elements used to change the opening and closing state of the electric circuit, and may include power control semiconductor elements such as SCR, GTO thyristor, bipolar transistor, MOSFET, IGBT and the like.

FIG. 1A is a block diagram illustrating a 3D variable resistance memory according to an exemplary embodiment of the present invention, and FIG. 1B is a block diagram illustrating a part of the 3D variable resistance memory illustrated in FIG. 1A. 1C shows an equivalent circuit for the three-dimensional variable resistance memory shown in FIGS. 1A and 1B.

As shown in Figure 1a and Figure 1b, the three-dimensional variable resistance memory according to an embodiment of the present invention has a large data storage, suitable for bipolar resistance memory, cross-point structure of less than 4F2, according to the present invention three-dimensional variable The structure of the resistive memory and the operation method when writing, erasing and reading will be described.

As shown in FIG. 1A, in the 3D variable resistance memory according to the exemplary embodiment of the present invention, a plurality of vertical bipolar transistors are three-dimensionally connected, and a plurality of bit lines BL are formed at an upper end thereof. An upper gate (USG, upper select gate) and a lower gate (LSG, lower select gate) are respectively coupled to the bottom.

FIG. 1B illustrates a single vertical bipolar transistor, wherein the vertical bipolar transistor includes a vertical memory string, an upper select gate (USG), a lower select gate (LSG), an RRAM resistive material, a word line (WL, Word). Line) and bit line (BL).

Here, the vertical memory string includes a vertical p-type string 101 including a silicon (Si) layer doped with P-type impurities and a silicon (Si) layer doped with N-type impurities. It consists of three vertical n-type strings (102, 103). Here, the vertical P-type string 101 is inserted between the two vertical N-type strings 102 and 103.

An upper select gate (USG) is formed in a vertical direction at an upper end of the vertical memory string, and a lower select gate (LSG) is formed in a vertical direction at a lower end of the vertical memory string. That is, the upper gate USG and the lower gate LSG are formed at the top and bottom of the vertical memory string in a direction crossing the vertical memory string. 1A and 1C, bit lines BL are connected to upper ends of the vertical N-type strings 102 and 103 to apply a Vcc voltage to the vertical N-type strings 102 and 103.

One side of the vertical N-type string 103 is attached to an RRAM material, which is a resistive memory material, and a plurality of word lines WL doped with P-type impurities are attached to the RRAM material in a vertical direction.

Here, the vertical P-type string 101, the vertical N-type string 103, and the word line WL form a vertical bipolar transistor in which PNPs are bonded, and a PNP junction vertical according to an embodiment of the present invention. A current may flow in both directions to the vertical P-type string 101, the vertical N-type string 103, and the word line WL forming the bipolar transistor. That is, according to the exemplary embodiment of the present invention, current may flow in both directions of the PNP junction transistor through the RRAM material, which is a resistive memory material, and thus may operate as a bipolar resistive memory. For convenience of explanation, set the data bit to " 1 " if the state of the RRAM material is a high resistance state and set the data bit to " 0 "

FIG. 1C is an equivalent circuit diagram of a plurality of strings connected to the bit line BL, the upper gate USG and the lower gate LSG, and the word line WL. The string shown in FIG. 1C is a circuit diagram of the vertical N-type string 103 among the PNP junction vertical bipolar transistors, and the strings having the same arrangement order among the strings connected to different bit lines BL are the upper gate USG. And share the bottom gate (LSG). In addition, the vertical N-type string 103 and the word line WL form a PN junction diode, which is conceptually shown in FIG. 1C.

The portion where the adjacent vertical P-type string 101 and the word line WL are coupled based on the RRAM material is referred to as " cell "

Hereinafter, a process of writing data in the 3D variable resistance memory will be described with reference to FIGS. 2A through 3D. 2A and 2B are diagrams for explaining a preprocessing process of writing to a three-dimensional variable resistance memory according to a first embodiment of the present invention, and FIG. 2A is a three-dimensional variable resistor according to a first embodiment of the present invention. The equivalent circuit diagram of the memory observed from the front view, and FIG. 2B is an equivalent circuit diagram of the strings connected to the bit line 1 BL1 from the bit lines shown in FIG. 2A.

As shown in FIG. 2A, a plurality of strings are connected to the plurality of bit lines BL1, BL2, and BL3, respectively. Strings S1, S2 and S3 are connected to bit line 1 BL1, strings S4, S5 and S6 are connected to bit line 2 BL2, and strings S7, S8 and S9 are connected to bit line 3 BL3. . Since the string structure is the same as that of the strings S3, S6, and S9, the structure of the remaining strings is omitted.

The strings S1, S4, and S7 have the same upper gate USG1 and the lower gate LSG1, and the strings S2, S5, and S8 also have the same upper gate USG2 and the lower gate LSG2. Similarly, the strings S3, S6, and S9 also have the same upper gate USG3 and lower gate LSG3.

Also, as shown in FIG. 2B, the strings S1, S2, and S3 connected to the bit line 1 BL1 are described in detail. The string S1 includes cells 10, 11, and 12, and the string S2 includes cells 7, cells 8, and 9. String S3 comprises cell 4, cell 5, cell 6. Here, the same word line WL1 is connected to cells 4, 7, and 10, and the same word line WL2 is connected to cells 5, 8, and 11, and cells 6, 9, and 12 also have the same word. Line WL3 is connected.

Referring again to FIG. 2A, it is assumed that the string S6 includes cells 1, 2, and 3, and that cells 1, 2, and 3 are unselected cells programmed to not be selected. In addition, it is assumed that cells 4, 5, and 6 included in the string S3 are selected cells programmed to be selected.

Herein, it is assumed that the string including at least one selection cell is a selection string, and in FIGS. 2A and 2B, the strings S3 and S9 correspond to the selection string. On the other hand, a string that does not include any selection cell is a non-selection string, and it is assumed in FIGS. 2A and 2B that the strings S1, S2, S4, S5, S6, S7, and S8 correspond to the non-selection string.

In the preprocessing process as shown in FIG. 2A, in the case of the bit line 2 BL2 to which only the unselected strings S4, S5, and S6 are connected, the Vcc voltage is applied to precharge. That is, since only the unselected strings programmed to not select the cell are connected to the bit line 2 (BL2), the Vcc voltage corresponding to the high voltage is applied through the bit line 2 (BL2), and accordingly, the bit line 2 (BL2) All unselected strings S4, S5, and S6 connected to are in a precharge state.

Therefore, in the case of the unselected string S6 including the unselected cells (cell 1, cell 2, cell 3), when the Vcc voltage is applied through the bit line 2 BL2, the current (from the top to the bottom of the string S6) Since i) flows, current passes in the order of Cell 1, Cell 2, and Cell 3.

On the other hand, the bit line BL to which at least one selection string is connected is precharged with a voltage of 0V. Therefore, according to FIG. 2A, the bit lines BL1 and BL3 to which the selection strings S3 and S9 are connected are precharged with a voltage of 0V. In particular, since the string S1 is a selected string including selected cells (cells 4, 5 and 6), the bit line 3 BL3 is precharged to a voltage of 0V.

2A and 2B, a Vcc voltage is applied to the upper gate USG3 including at least one selection string, and a 0V voltage is applied to the lower gate LSG3. In addition, a 0 V voltage is applied to the upper gates USG1 and USG2 including only the unselected strings, and a Vcc voltage is applied to the lower gate LSG3. The 0V voltage is applied to all word lines WL connected to the selected and non-selected cells.

3A and 3B are diagrams for describing a step of writing data in a 3D variable resistance memory according to a first embodiment of the present invention. FIG. 3A is an equivalent circuit diagram of a 3D variable resistance memory observed from a front view. FIG. 3B is an equivalent circuit diagram of lateral observation of strings connected to bit line 1 BL1 among the bit lines shown in FIG. 3A.

That is, FIGS. 3A and 3B illustrate a process of converting a data bit value of a 3D variable resistance memory from 1 to 0 and writing it.

As shown in FIGS. 3A and 3B, a programmed voltage Vpgm is applied to a word line WL including a selection cell. That is, a word voltage Vpgm is applied to word line 1 WL1 that includes at least one selected cell (cells 4 and 9), and word lines 2 (WL2) and word lines that do not contain any selected cells. A voltage of 0 V is applied to 3 (WL3).

In the preprocessing process as shown in FIGS. 2A and 2B, since the voltage of the selection string is set to 0 V, the forward current flows from the word line 1 (WL1) toward the string in the selection cells (cells 4 and 9). That is, word line 1 WL1 has a P-type, and the string corresponds to the vertical N-type string 103 so that not only has N-type, but also the voltage Vpgm applied to word line 1 WL1 and the string. Since the magnitude difference between the voltages 0V is greater than the switching voltage Vth, current flows in the forward direction in the PN junction diode corresponding to the selected cell (cell 4) in FIG. 2B. The RRAM material, which is the resistive memory material corresponding to the selected cell (cell 4), is changed from the high resistance state to the low resistance state.

On the other hand, since the 0V voltage is applied to the unselected cells (cells 5, 6, 10, and 11) during the preprocessing, the 0V voltage is applied to the word lines 2 (WL2) and 3 (WL3). No current flows.

In particular, in the case of the non-selected cell (cell1) to which the Vpgm voltage is applied through the word line 1 (WL1), the Vpgm voltage is applied to the word line 1 (WL1) because the string is precharged to the Vcc voltage in the previous preprocess. However, since the value obtained by subtracting the Vcc voltage from the Vpgm voltage is smaller than the switching voltage Vth, the reverse current does not flow.

Hereinafter, a process of erasing data stored in the 3D variable resistance memory will be described with reference to FIG. 4.

FIG. 4 is a partial block diagram of a three-dimensional variable resistance memory for explaining a process of erasing data stored in the three-dimensional variable resistance memory according to the second embodiment of the present invention.

For convenience of description, it is assumed that only the second cell 11 of FIG. 4 is a selected cell, and the remaining cells 10 and 12 are non-selected cells.

According to the exemplary embodiment of the present invention, in the page erase operation, a Vp voltage is applied to the vertical P-type string 101 including the selection cell (cell 11) and the word line WL corresponding to the selection cell (cell 11). Apply the -Vers voltage to.

A Vcc voltage is applied to the upper gate USG, and 0 V is applied to the bit line BL to convert the PNP junction vertical bipolar transistor into a turn-on state. The vertically from the bottom of the N-type string 103 to the top of the base current of the flow is i _base current, and the vertical P-type string 101 corresponding to the Emitter into the word line (WL) corresponding to the collector of emitter current i _emitter Current will flow. Here, the size and direction of the i _emitter current may be adjusted by adjusting the size and direction of the i _base current.

For example, when the _ibase current flowing from the bottom to the top is 10 ⁻⁵ A, the i _emitter current of the PNP junction vertical bipolar transistor is about 10 ⁻³ A.

Therefore, according to the embodiment of the present invention, a current flows through the resistance change thin film of the low resistance state between the P type and the N type of the PNP junction vertical bipolar transistor, thereby erasing data stored in the selected cell. That is, the RRAM material corresponding to the selected cell is changed from the low resistance state to the high resistance state to reset the data bit '0' to the data bit '1'.

As described above, the current flows only in the direction of the vertical P-type string 101 from the word line WL by the PN junction diode. However, in the case of the PNP junction vertical bipolar transistor according to the present invention, the current flows in both directions. This becomes possible.

Hereinafter, a process of reading data stored in the 3D variable resistance memory will be described with reference to FIG. 5.

FIG. 5 is an equivalent circuit diagram of a three-dimensional variable resistance memory for explaining a process of reading data stored in the three-dimensional variable resistance memory according to the third embodiment of the present invention.

As shown in FIG. 5, the forward voltage Vread voltage is applied to the word line WL corresponding to the selected cell, and each bit line BL makes a discharge state at 0V. A Vcc voltage is applied to the upper gate USG of the string including the unselected cells, and a Vcc voltage is opened. The lower gate LSG is closed at 0V.

First, in the case of a cell programmed in a low resistance state as shown in cell A of FIG. 5, a current i applied by a forward voltage Vread of a PN junction diode flows through a resistance change material in a low resistance state, and thus a bit to which cell A belongs. The line BL is charged with a Vcc voltage.

On the other hand, in the case of a memory cell programmed in a high resistance state as shown in cell B of FIG. 5, since the current flowing into the bit line BL to which cell B belongs is weak by the selected word line WL, the corresponding bit line ( BL) is maintained at 0V.

Therefore, when the voltage charged to the bit line BL is Vcc, it is read as data "0" representing the low resistance state, and when the voltage charged to the bit line BL is 0V, Read into data "1" indicating the resistance state.

As described above, according to the exemplary embodiment of the present invention, a forward voltage Vread voltage is applied to the word line WL corresponding to the selected cell, each bit line BL is discharged, and after a predetermined time, The resistance state corresponding to the selected cell can be read from the voltage.

Thus, according to the embodiment of the present invention, by forming a three-dimensional memory configuration with a three-dimensional architecture structure for the bipolar resistive memory that has an advantage in operating stability, such as operating current, repeatability, etc., NAND flash memory that is expected to reach the limit in the future It is possible to replace it with a resistive memory.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of right.

101: vertical P-type string
102, 103: vertical N-type string

Claims (15)

A plurality of bit lines spaced in parallel directions,
A plurality of vertical memory strings formed in a vertical direction on each of the plurality of bit lines, each of the plurality of vertical memory strings including a plurality of serial memory cells;
A resistive memory material attached to a side end of each of the plurality of vertical memory strings,
A plurality of word lines respectively corresponding to the plurality of memory cells and coupled to the resistive memory material in a vertical direction;
A plurality of top gates formed on top of the plurality of vertical memory strings and coupled to a plurality of vertical memory strings connected to different bit lines in a vertical direction, and
And a plurality of bottom gates formed at lower ends of the plurality of vertical memory strings and coupled to a plurality of vertical memory strings connected to different bit lines in a vertical direction. The method of claim 1,
Each of the plurality of vertical memory strings is
A first string having a first polarity, and
And a second string and a third string coupled to both ends of the first string and having a second polarity. 3. The method of claim 2,
The word line has the first polarity;
And the second string and the word line are connected through the resistive memory material and form a PN junction diode. The method of claim 3,
And the first string, the second string, and the word line form a PNP bipolar transistor or an NPN bipolar transistor. In the driving method of the three-dimensional variable resistance memory according to any one of claims 1 to 4,
The plurality of memory cells are divided into selected cells selected for storing information and non-selected cells except the selected cells.
The plurality of vertical memory strings may include an unselected memory string including only the non-selected cells and a selected memory string including one or more selected cells.
A first step of applying a first voltage to a bit line connected only to the unselected memory string, and applying a second voltage lower than the first voltage to the bit line connected to the selected memory string; and
Among the plurality of top gates and the plurality of bottom gates, the first voltage is applied to an upper gate to which one or more selection memory strings are connected, and to the lower gate to which one or more selection memory strings are connected. And a second step of applying a second voltage to the lower gate to which only the unselected memory strings are connected, and then applying the first voltage to the lower gate. The method of claim 5,
The first and second steps may be performed simultaneously, and the second voltage may be applied to the plurality of word lines in the course of performing the first and second steps. The method according to claim 6,
After completing the first and second steps,
Applying a programmed third voltage to a word line including one or more selection cells, and applying the second voltage to a word line not including the selection cell. Driving method. The method of claim 7, wherein
And a resistance memory material corresponding to the selection cell is changed from a high resistance state to a low resistance state. 9. The method of claim 8,
And the second voltage is a ground voltage. In the driving method of the three-dimensional variable resistance memory according to any one of claims 1 to 4,
The plurality of memory cells are divided into selected cells selected for storing information and non-selected cells except the selected cells.
The plurality of vertical memory strings may include an unselected memory string including only the non-selected cells and a selected memory string including one or more selected cells.
Applying a first voltage to the first string included in the selected memory string,
Applying a second voltage to a word line connected to at least one of the selected cells of the plurality of word lines, and
Among the plurality of upper gates and the plurality of lower gates, a third voltage is applied to an upper gate to which at least one selected memory string is connected, and the lower gate is connected to a lower gate to which at least one selected memory string is connected. And applying a fourth voltage lower than three voltages. The method of claim 10,
And a resistance memory material corresponding to the selection cell is changed from a low resistance state to a high resistance state. 12. The method of claim 11,
And the fourth voltage is a ground voltage. In the driving method of the three-dimensional variable resistance memory according to any one of claims 1 to 4,
The plurality of memory cells are divided into selected cells selected for storing information and non-selected cells except the selected cells.
The plurality of vertical memory strings may include an unselected memory string including only the non-selected cells and a selected memory string including one or more selected cells.
Applying a first voltage to a word line connected to at least one selected cell of the plurality of word lines, and applying a second voltage lower than the first voltage to a word line connected only to the non-selected cell; ,
Applying the second voltage to the plurality of bit lines;
Among the plurality of top gates and the plurality of bottom gates, a third voltage higher than the second voltage is applied to an upper gate to which one or more selection memory strings are connected, and one or more selection memory strings are connected to each other. Applying the second voltage to the lower gate; and
And applying the second voltage to an upper gate and a lower gate to which only the non-selected memory strings are connected. The method of claim 13,
And reading the resistance state of the selected cell in accordance with the voltage change of the bit line. 15. The method of claim 14,
And the second voltage is a ground voltage.

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