KR101325449B1 - Thin film transistor array substrate and method for testing thin film pattern - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate and a method of inspecting thin film patterns, the thin film transistor array substrate including thin film patterns formed on a display region of a substrate; And an alignment inspection pattern formed in a non-display area of the substrate and used for alignment inspection of the thin film patterns. Wherein the alignment inspection patterns include a first inspection line and a second inspection line formed in parallel with each other; First finger portions extending in the first test line in the second test line direction and spaced equidistant from each other; And second finger portions extending in the direction of the first test line in the second inspection line and having an equal interval from each other. A capacitor is formed between the first and second fingers.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor array substrate,

1 is a plan view showing a conventional alignment inspection pattern.

2 is a plan view showing a thin film transistor array substrate according to the present invention.

3 is a sectional view showing a thin film transistor formed on the thin film transistor array substrate of FIG.

4 is a cross-sectional view showing an alignment inspection pattern according to the present invention;

5 is a cross-sectional view taken along line I-I 'of FIG. 4;

FIG. 6 shows experimental data on the capacitance of the capacitor C of 5. FIG.

Description of the Related Art

10,110: alignment pattern

80, 180: thin film transistor array substrate

15,115: First test line 19,119: Second test line

11,111: first finger refusal 13,113: second finger refusal

106: thin film transistor 118: pixel electrode

108: gate electrode 102: gate line

The present invention relates to a liquid crystal display panel, and more particularly, to a thin film transistor array substrate and a thin film pattern inspection method capable of precisely measuring and determining degree of alignment between thin film patterns.

In recent information society, the importance of display devices as visual information delivery media is emphasized more than ever. Cathode Ray Tube (CRT) or cathode ray tube, which is currently mainstream, has a problem in weight and volume. Many types of flat panel displays capable of overcoming the limitations of the cathode ray tube have been developed.

A flat panel display device includes a liquid crystal display device (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence (EL) Most of these are commercialized and put on the market.

Liquid crystal display devices can meet the trend of light and small size of electronic products and have improved mass productivity and are rapidly replacing cathode ray tubes in many applications.

In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has an advantage in that it has excellent image quality and low power consumption. And research and development achievements are rapidly evolving into larger size and higher resolution.

The manufacturing process for manufacturing the active matrix type liquid crystal display device includes a substrate cleaning process, an array substrate formation process, a thin film pattern inspection process, a substrate adhesion process, a scribing process, a liquid crystal injection process, a grinding process, Inspection process, and repair process.

In the substrate cleaning process, contaminated foreign substances are removed by the cleaning liquid on the substrate surface of the liquid crystal display element.

In the array substrate formation step, a color filter array substrate is formed and a thin film transistor array substrate is formed.

The thin film pattern inspection process is a process for confirming whether thin film patterns formed on the thin film transistor array substrate are normally formed using the alignment inspection pattern shown in FIG.

In the liquid crystal injection process, the liquid crystal is injected into the liquid crystal display panel through the liquid crystal injection hole, and then the liquid crystal injection hole is sealed.

1 is a view showing an alignment inspection pattern in which an inspection process of a thin film pattern is used.

The alignment inspection pattern shown in Fig. 1 is formed in the non-display area of the thin film transistor array substrate.

The alignment inspection patterns shown in FIG. 1 include a first inspection line 15 and a second inspection line 19 which are formed in parallel with each other and a second inspection line 17 extending from the first inspection line 15 toward the second inspection line 19 And first fingers 11 and second finger fingers 13 extending in the direction of the first test line 15 in the second test line 19. The first and second fingers 11 and 13 are positioned to face each other and are positioned at the middle of the first fingers 11a and the second fingers 13 located at the center among the first fingers 11 And the ends of the second fingers 13a positioned at the center are designed to completely overlap each other (A).

Accordingly, the end of the first finger 11a located at the center and the end of the second finger 13a positioned at the center among the second finger fingers 13 among the first finger fingers 11 overlap It is possible to determine the degree of accuracy of the alignment of the thin film patterns formed in the display region P1. That is, the error can be confirmed by determining the distance from 0 占 퐉.

It is determined whether thin film patterns formed in the display region of the thin film transistor array substrate are normally formed according to the degree of the error.

In the case of discriminating the alignment of the conventional thin film pattern, the degree of error is confirmed by checking directly through the microscope. As a result, there arises a problem that the discrimination of the degree of error itself has another error, and as a result, the reliability of the alignment inspection process of the thin film pattern is deteriorated.

The present invention provides a thin film transistor array substrate and an inspection method of a thin film pattern in which an alignment inspection pattern is formed to precisely measure and determine the degree of alignment between thin film patterns.

The thin film transistor array substrate of the present invention comprises thin film patterns formed on a display region of a substrate; And an alignment inspection pattern formed in a non-display area of the substrate and used for alignment inspection of the thin film patterns. Wherein the alignment inspection pattern comprises: a first inspection line and a second inspection line formed in parallel with each other; First finger portions extending in the first test line in the second test line direction and spaced equidistant from each other; And second finger portions extending in the direction of the first test line in the second inspection line and having an equal interval from each other. A capacitor is formed between the first and second fingers.

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A method of inspecting a thin film pattern for inspecting a degree of alignment of thin film patterns formed on a display region of a substrate, the method comprising the steps of: forming first finger portions having an equal spacing from each other and spaced apart from each other with the first finger portions And forming an alignment inspection pattern including the second finger portions alternately non-heated; Measuring a capacitance of a capacitor formed between the first and second fingers; And comparing the capacitance with a preset reference capacitance to determine a formation position of the first and second finger portions.

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Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 6. FIG.

2 is a plan view schematically showing a thin film transistor array substrate 180 according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing the thin film transistor 106 and the pixel electrode 118 in FIG. 2 in detail.

2 and 3, the thin film transistor array substrate of the present invention is divided into a display region P1 and a non-display region P2 outside the display region P1.

A thin film transistor 106 (not shown) formed in a crossing region of the gate line 102 and the data line 104, the gate line 102, and the data line 104 formed to cross each other is formed in the display region P1 of the thin film transistor array substrate 180 And a pixel electrode 118 connected to the thin film transistor 106.

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The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a gate insulating film 144 formed to cover the gate electrode 108, a semiconductor pattern 147 formed on the gate insulating film 144, A source electrode 130 formed on the semiconductor pattern 147 and connected to the data line 104 and a drain electrode 132 facing the source electrode 130. The semiconductor pattern 147 includes an active layer 148 which forms a channel between the source electrode 130 and the drain electrode 132 and an ohmic contact layer 144 for ohmic contact between the active layer 148 and the source and drain electrodes 130 and 132 114).

The pixel electrode 118 is in contact with the drain electrode 132 of the thin film transistor 106 through the contact hole 151 passing through the protective film 150.

The gate pad 103 connected to the gate line 102, the data pad 105 connected to the data line 104 and the alignment test pattern 110 are formed in the non-display area P2 of the TFT array substrate 180 do.

Fig. 4 is a plan view specifically showing the alignment inspection pattern 110 in Fig. 2, and Fig. 5 is a cross-sectional view taken along the line I-I 'in Fig.

The alignment inspection pattern 110 shown in FIG. 4 includes a first inspection line 115 and a second inspection line 119 which are formed in parallel with each other, and a second inspection line 115 extending in a direction from the first inspection line 115 to the second inspection line 119 And second fingers 113 extending in the direction of the first inspection line 115 in the second inspection line 119. The first fingers 111 extend in the first inspection line 115 direction. The first and second fingers 111 and 113 are arranged side by side and alternately. The line width D1 of the first and second fingers 111 and 113 are equal to each other and the distance D2 between the first fingers 111 is equal to the distance D2 between the second fingers 113 Do.

The first inspection line 115 and the first finger 111 are formed simultaneously with the same material as the gate electrode 108 and the gate line 102 of the display area P1.

The second inspection line 119 and the second finger 113 are formed simultaneously with the same material as the pixel electrode 118 of the display area P1.

Referring to FIG. 4, the first and second fingers 111 and 113 are partially overlapped with each other. A gate insulating layer 144 and a protective layer 150 are formed between the first and second fingers 111 and 113.

Accordingly, a capacitor C is formed between the first and second fingers 111 and 113. At this time, a capacitance (capacitance) of the capacitor C formed between the first and second fingers 111 and 113 is measured. The capacitance of the capacitor C formed between the first and second fingers 111 and 113 satisfies the following equation (1).

C =? X (A / d) (A: cross-sectional area of electrode, d: distance between electrodes,

It can be seen that the capacitance of the capacitor C is proportional to the cross-sectional area A of the electrode.

The total capacitance when the capacitors C are connected in parallel can be calculated by the sum of the capacitances of the capacitors C. [ The capacitance between the first and second fingers 111 and 113 is substantially small, so that the sum of the capacitors C is measured.

By using these principles, the total capacitance of the capacitors C formed between the first and second fingers 111 and 113 is measured and compared with the previously set reference capacitance, and according to the comparison result, It is possible to discriminate the degree of error of the thin film patterns of the thin film transistor 106 and the like.

For example, the first fingers 111 and the second fingers 113 are overlapped with each other so that the cross-sectional area A of the electrode forming the capacitor B becomes larger and the distance d becomes closer The electric capacity becomes larger. Conversely, if the degree of overlap between the first finger 111 and the second finger 113 is small or non-overlapping, the electric capacity becomes small.

By using this principle, it is possible to measure the capacitance value when the thin film patterns are formed in the right position, to determine the error degree by using the measured capacitance, and to proceed the process in the state where the error is corrected in the forming process .

As described above, the inspection process of the thin film pattern in the present invention can discriminate the degree of alignment of the thin film patterns formed in the display area accurately and delicately by using electric capacity instead of conventional conventional error discrimination.

This makes it possible to improve the reliability of the alignment inspection process of the thin film pattern.

FIG. 6 shows experimental data on the capacitance of the capacitor C. FIG.

In FIG. 6, the X-axis represents the degree of alignment between opposing electrodes, and the Y-axis represents the capacitance of the capacitor C formed between the electrodes. The straight line E in Fig. 6 represents an ideal relationship of the capacitance value according to the alignment state between the electrodes.

In Fig. 6, when the alignment value in the X axis is "O" mu m, the capacitance value of the Y axis is about 250 (fF). That is, when the capacitance value between the first and second fingers 111 and 113 is about 250 (fF), the alignment between the first and second fingers 111 and 113 is determined as "0" When the aligned state is "0 ", the first and second fingers 111 and 113 are formed at the right positions, and it is determined that the thin film patterns are normally formed in the normal position in the display region P1.

On the other hand, the increase in the value of capacitance means that the area where the first and second fingers 111 and 113 are overlapped with each other is widened, and the alignment value of the X axis is the overlapping width between the first and second finger parts 111 and 113 it means.

The small value of the capacitance means that the first and second fingers 111 and 113 move away from each other.

Therefore, not only the alignment value is larger than "0 " but also the smaller value means that the position is far from the position.

The points in FIG. 6 represent values measured by an actual experiment. It can be seen that the distribution of the points has the same pattern as the curve E although there is some error.

When the capacitance value is measured to be larger than the reference value as a result of measuring the capacitance, the user corrects the process condition so that the first and second fingers 111 and 113 are not overlapping with each other. If the capacitance value is measured to be smaller than the reference value, And the second fingers 111 and 113 are narrowed.

That is, the process conditions that allow the capacitance between the first and second fingers 111 and 113 to coincide or approximate the reference capacitance and the first and second fingers 111 and 113 and thin film patterns formed thereafter are corrected It is formed by process conditions.

As a result, the reliability of the alignment inspection process of the thin film pattern can be improved, and the thin film patterns can be formed in place.

As described above, in the thin film transistor array substrate and the thin film pattern inspection method according to the embodiment of the present invention, the alignment pattern is formed on the thin film transistor array substrate, the capacitance of the alignment pattern is measured, Whether or not a predetermined position of the inspection patterns is formed. Then, the process conditions for forming the thin film pattern are corrected based on the measured capacitance value. Accordingly, the degree of alignment of the thin film patterns formed in the display region of the thin film transistor array substrate can be more accurately and finely determined than in the conventional error discrimination, and the process variations and errors can be accurately corrected.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, the technical idea of the present invention has been described mainly on the electrical inspection of the liquid crystal display panel in the embodiment, but the same can be applied to the electrical inspection for the signal wirings formed on the other flat panel display devices. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

Thin film patterns formed on a display region of a substrate; And an alignment inspection pattern formed on a non-display area of the substrate and used for alignment inspection of the thin film patterns, In the alignment inspection pattern, A first inspection line and a second inspection line formed in parallel with each other; First finger portions extending in the first test line in the second test line direction and spaced equidistant from each other; And second finger portions extending in the first test line in the first test line direction and spaced apart from each other, And a capacitor is formed between the first and second fingers. The method according to claim 1, In the alignment inspection pattern, Further comprising a gate insulating layer and a protective layer disposed between the first and second fingers. delete The method according to claim 1, The thin film patterns formed in the display region A gate line and a data line formed so as to intersect with each other, a thin film transistor formed in an intersection region of the gate line and the data line, and a pixel electrode connected to the thin film transistor. 5. The method of claim 4, The first inspection line and the first finger portions are simultaneously formed of the same material as the gate line, Wherein the second inspection line and the second finger portions are simultaneously formed of the same material as the pixel electrode. A method of inspecting a thin film pattern for inspecting a degree of alignment of thin film patterns formed in a display region of a substrate, Forming first finger portions having an equal distance from each other and an alignment inspection pattern including first finger portions which are equally spaced from each other and which are parallel to each other and which are alternately non-heated; Measuring a capacitance of a capacitor formed between the first and second fingers; And comparing the capacitance with a predetermined reference capacitance to determine formation positions of the first and second finger portions. The method according to claim 6, Determining the degree of alignment of the thin film patterns by the formation positions of the first and second finger portions; And correcting the process condition according to a result of comparison between the capacitance and a preset reference capacitance. 8. The method of claim 7, Wherein the capacitance of the capacitor is increased as the overlap region between the first and second fingers is widened. 8. The method of claim 7, Wherein the capacitance of the capacitor decreases as the distance between the first and second fingers increases. 8. The method of claim 7, The step of correcting the process condition according to the comparison result of the capacitance and the preset reference capacitance Wherein the process condition is corrected so that the magnitude of the capacitance of the capacitor matches the magnitude of the reference capacitance.

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