KR101323555B1 - Organic Light Emitting Display Device And Manufacturing Method Of The Same - Google Patents

Abstract

An organic light emitting display device according to an embodiment of the present invention includes a substrate, an active layer and a silicon pattern disposed on the substrate, a first insulating pattern disposed on the active layer, and a second insulation disposed on the silicon pattern. A pattern, a capacitor lower electrode disposed on the second insulating pattern, a gate insulating layer positioned on the first insulating pattern and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer and corresponding to the active layer A capacitor upper electrode positioned on the capacitor lower electrode and a first electrode spaced apart from the gate electrode and the capacitor upper electrode, an interlayer disposed on the gate electrode, the capacitor upper electrode, and the first electrode; An insulating film, wherein the insulating film is on the interlayer insulating film and is connected to the active layer; A source layer and a drain electrode connected to the first electrode, a bank layer on the substrate including the source electrode and the drain electrode, the bank layer exposing a portion of the first electrode, a spacer on the bank layer, the exposed agent The organic layer may be disposed on one electrode, and the second electrode may be disposed on the substrate including the organic layer.

Description

Organic Light Emitting Display Device And Manufacturing Method Of The Same

The present invention relates to an organic light emitting display device and a method of manufacturing the same.

2. Description of the Related Art In recent years, the importance of flat panel displays (FPDs) has been increasing with the development of multimedia. Accordingly, liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), organic light emitting display devices (Organic Light Emitting Display Devices), and the like. Various flat panel displays have been put to practical use.

Among them, the liquid crystal display device has better visibility than the cathode ray tube, the average power consumption and the heat generation amount are small, and the organic light emitting display device has a fast response time with a response speed of 1 ms or less, and a low power consumption. Because it is self-luminous, there is no problem in viewing angle, and thus, it is attracting attention as a next-generation flat panel display.

1 is a view illustrating a conventional organic light emitting display device.

Referring to FIG. 1, a buffer layer 110 is positioned on a substrate 100, an active layer 115a and a capacitor lower electrode 115b are positioned on a buffer layer 110, and a gate insulating layer 120 isolating them. Located. A gate electrode 130a and a capacitor upper electrode 130b are positioned on the gate insulating layer 120, and an interlayer insulating layer 135 is insulated from the gate insulating layer 120. The thin film transistor TFT is formed by the source electrode 145a and the drain electrode 145b connected to the active layer 115a through the contact holes 140a and 140b on the interlayer insulating layer 135.

The passivation layer 150 is positioned on the thin film transistor TFT, and the first electrode 160 connected to the drain electrode 145b is disposed through the via hole 155. The bank layer 165 including the opening 170 exposing the first electrode 160 is positioned on the substrate 100, and the organic layer 175 is positioned on the first electrode 160. The spacer 180 is positioned around the organic layer 175, and the second electrode 185 is positioned on the substrate 100 to form an organic light emitting display device.

The conventional organic light emitting display device has an active layer 115a, a capacitor lower electrode 115b, a gate electrode 130a, contact holes 140a and 140b, a source electrode 145a, a drain electrode 145b, and a via hole ( 155, the first electrode 160, the opening 170, and the spacer 180 may be manufactured using a total of nine masks.

However, the conventional organic light emitting display device has a problem in that the productivity is low due to the high number of processes and the high cost required by using nine masks.

The present invention provides an organic light emitting display device and a method of manufacturing the same, which can reduce cost by reducing the number of masks and improve productivity and manufacturing yield.

In order to achieve the above object, an organic light emitting display device according to an embodiment of the present invention, a substrate, an active layer and a silicon pattern on the substrate, a first insulating pattern and the silicon on the active layer A second insulating pattern on the pattern, a capacitor lower electrode on the second insulating pattern, a gate insulating layer on the first insulating pattern and the capacitor lower electrode, and a second insulating pattern on the gate insulating layer A gate electrode corresponding to the layer, a capacitor upper electrode positioned correspondingly on the capacitor lower electrode, and a first electrode spaced apart from the gate electrode and the capacitor upper electrode, the gate electrode, the capacitor upper electrode, and the An interlayer insulating layer on the first electrode, and an active layer on the interlayer insulating layer A bank layer connected to the first electrode and a source electrode and a drain electrode connected to the first electrode, the bank layer exposing a portion of the first electrode, the bank layer being on the bank layer; A spacer may be disposed, an organic layer positioned on the exposed first electrode, and a second electrode positioned on the substrate including the organic layer.

The gate electrode may have a first metal oxide pattern and a first metal pattern stacked thereon, and the capacitor upper electrode may have a second metal oxide pattern and a second metal pattern stacked thereon.

The first electrode may be a laminate of a third metal oxide pattern and a third metal pattern.

The spacer may be made of the same material as the bank layer.

In addition, the method of manufacturing an organic light emitting display device according to an embodiment of the present invention comprises the steps of sequentially forming a polycrystalline silicon layer, an insulating layer, and a first metal layer on a substrate, by applying a first photosensitive film on the substrate Thereafter, by patterning using a first halftone mask, an active layer and a silicon pattern are formed, and at the same time, a first insulating pattern is formed on the active layer, a second insulating pattern is formed on the silicon pattern, and the second Forming a capacitor lower electrode on the insulating pattern, forming a gate insulating film on the active layer and the capacitor lower electrode, sequentially laminating and patterning a metal oxide layer and a second metal layer on the gate insulating film, and A gate electrode on which a first metal oxide pattern and a first metal pattern are stacked, and a capacitor on which a second metal oxide pattern and a second metal pattern are stacked Forming a first electrode on which a negative electrode, a third metal oxide pattern, and a third metal pattern are stacked; forming an interlayer insulating layer on the gate electrode, the capacitor upper electrode, and the first electrode; Stacking and patterning a third metal layer on the substrate to form a source electrode and a drain electrode, and simultaneously patterning a first metal pattern positioned on the first electrode, wherein the source electrode, the drain electrode, and the first electrode are patterned Forming a bank layer and a spacer by applying a second photoresist film on a substrate including a second halftone mask, forming an bank layer and a spacer on the first electrode, and including the organic film layer The method may include forming a second electrode on the substrate.

The sequentially forming the polycrystalline silicon layer, the insulating layer, and the first metal layer may include forming an amorphous silicon layer on the substrate, crystallizing the amorphous silicon layer into a polycrystalline silicon layer by irradiating a laser to the amorphous silicon layer, And forming an insulating layer on the polycrystalline silicon layer and forming the first metal layer on the insulating layer.

Forming the active layer and the silicon pattern, and simultaneously forming a first insulating pattern on the active layer, a second insulating pattern on the silicon pattern, and forming a capacitor lower electrode on the second insulating pattern After applying the first photoresist layer on the first metal layer, forming a first photoresist layer pattern and a second photoresist layer pattern having a thickness step using the first halftone mask, the polycrystalline silicon layer, and the insulation A layer and the first metal layer are etched to position the active layer, the silicon pattern, a first insulating pattern located on the active layer, a second insulating pattern located on the silicon pattern, and a first insulating pattern. Forming a second metal pattern and a capacitor lower electrode on the second insulating pattern, and forming the first photoresist pattern and the second photoresist pattern Ashing to reduce the thickness of the first photoresist pattern and to remove the second photoresist pattern, etching and removing the exposed second metal pattern by removing the second photoresist pattern, and removing the first photoresist pattern It may include the step of removing.

The forming of the bank layer and the spacer may include applying a second photosensitive film on the substrate, aligning and exposing the second halftone mask on the second photosensitive film, and exposing the second photosensitive film. And developing the bank layer and the spacers.

An organic light emitting display device and a method of manufacturing the same according to an embodiment of the present invention, unlike the conventional manufacturing of the organic light emitting display device using a total of nine masks, the organic light emitting display device using a total of five masks It can manufacture.

Therefore, by reducing the number of four masks, there is an advantage that the manufacturing cost can be reduced, and the productivity and manufacturing yield can be improved.

1 is a view showing a conventional organic light emitting display device.
2 is a cross-sectional view of an organic light emitting display device according to an embodiment of the present invention.
3A to 3J are cross-sectional views illustrating a method of manufacturing an organic light emitting display device according to one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of an organic light emitting display according to an embodiment of the present invention.

Referring to FIG. 2, in the organic light emitting display device 200 according to an exemplary embodiment, a buffer layer 215 is disposed on a substrate 210, and an active layer 220a and a silicon pattern are disposed on a buffer layer 215. 220b is located. The active layer 220a is doped with impurities to include a source region 221 and a drain region 222.

The first insulating pattern 223a is positioned on the active layer 220a, and the second insulating pattern 223b is positioned on the silicon pattern 220b. The capacitor lower electrode 226 is positioned on the second insulating pattern 223b.

The gate insulating layer 230 is positioned on the first insulating pattern 223a and the capacitor lower electrode 226. The gate electrode 235a and the capacitor upper electrode 235b are positioned on the gate insulating layer 230. The gate electrode 235a is positioned to correspond to the active layer 220a, and the capacitor upper electrode 235b is positioned to correspond to the capacitor lower electrode 226. The gate electrode 235 may be formed of a double layer in which the first metal oxide pattern 231 and the first metal pattern 232 are stacked. The capacitor upper electrode 235b may be formed of a double layer in which the second metal oxide pattern 236 and the second metal pattern 237 are stacked.

The first electrode 235c is positioned in a region spaced apart from the gate electrode 235a and the capacitor upper electrode 235b. The first electrode 235c may be formed of a double layer in which the third metal oxide pattern 238 and the third metal pattern 239 positioned at one edge of the third metal oxide pattern 238 are stacked.

An interlayer insulating layer 240 is disposed on the gate electrode 235a, the capacitor upper electrode 235b, and the first electrode 235c.

The interlayer insulating layer 240 includes a contact hole 241 exposing the source region 221 and the drain region 222 of the active layer 220a, and an opening region 242 exposing the first electrode 235c. It is provided.

A source electrode 245a and a drain electrode 245b are positioned on the interlayer insulating layer 240. The source electrode 245a and the drain electrode 245b contact the source region 221 and the drain region 222 of the active layer 220a, respectively, and the drain electrode 245b contacts the first electrode 235c. .

The bank layer 250 and the spacer 257 are positioned on the substrate 210 on which the source electrode 245a and the drain electrode 245b are formed. The bank layer 250 is provided with an opening 255 exposing the first electrode 235c. The spacer 257 protrudes from the surface of the bank layer 250 to be integrated with the bank layer 250, and is positioned around the exposed first electrode 235c.

The organic layer 260 is positioned on the exposed first electrode 235c. The organic layer 260 may include at least a light emitting layer, and may include at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. In addition, the second electrode 270 may be positioned on the substrate 210 including the organic layer 260 to configure the organic light emitting display device 200 according to an exemplary embodiment.

Hereinafter, a manufacturing method of manufacturing the organic light emitting display device according to the embodiment of the present invention described above will be described.

3A to 3J are views illustrating a method of manufacturing an organic light emitting display device according to one embodiment of the present invention.

First, referring to FIG. 3A, a buffer layer 315 is formed on a first substrate 310 made of glass, plastic, or a conductive material. The buffer layer 315 prevents impurities present on the surface of the substrate 310 from being eluted and diffused into the amorphous silicon layer during the laser crystallization process of the amorphous silicon layer to be performed later, and includes silicon oxide (SiOx), silicon nitride (SiNx) or It may be made of a laminated structure thereof.

An amorphous silicon layer 320a is deposited on the buffer layer 315. Next, a laser crystallization process of irradiating a laser onto the amorphous silicon layer 320a is performed. In this case, the laser crystallization process may be performed by excimer laser annealing (ELA). Thus, the amorphous silicon layer 320a is crystallized into the polycrystalline silicon layer 320b.

Next, referring to FIG. 3B, a first insulating layer 325 is stacked on the polycrystalline silicon layer 320b, and a first metal layer 330 is stacked on the first insulating layer 325. In this case, the first insulating layer 325 is formed of silicon oxide (SiOx) or silicon nitride (SiNx), and the first metal layer 330 is made of aluminum (Al), molybdenum (Mo), tungsten (W), and titanium (Ti). ) Or an alloy thereof.

Next, the first photosensitive film 335 is coated on the substrate 310 including the first insulating layer 325 and the first metal layer 330 by spin coating. The first photoresist layer 335 may be a material that is later decomposed and removed when light is irradiated with a positive photoresist.

Subsequently, after aligning the first halftone mask 340 including the transmission part 341, the transflective part 342, and the blocking part 343 on the substrate 310 on which the first photoresist film 335 is formed, ultraviolet (UV) light is emitted. Investigate

Next, referring to FIG. 3C, the first photoresist pattern 345 and the second photoresist pattern 346 having a thickness step are formed by using a diffraction exposure technique through the first halftone mask 340. .

In more detail, by using a diffraction exposure technique using the first halftone mask 340, the blocking part 343 is applied to the first photoresist film 335 facing the blocking part 343, which is left as it is. The photosensitive film pattern 345 and the transflective part 342 are applied to the first photosensitive film 335 opposite to the transflective part 342 to be diffracted and transmitted. The second photosensitive film pattern 346 remaining in the thickness is formed. The first photoresist layer 335 facing the transmissive portion 341 is decomposed and removed during development, thereby exposing the surface of the first metal layer 330.

In this case, the first photoresist pattern 345 is formed in the region where the capacitor lower electrode is to be formed later, and the second photoresist pattern 346 is formed in the region where the active layer will be formed later.

Next, referring to FIG. 3D, the polycrystalline silicon layer 320b, the first insulating layer 325, and the first metal layer 330 are etched using the first photoresist pattern 345 and the second photoresist pattern 346. Thus, the active layer 351a, the first insulating pattern 352a positioned on the active layer 351a, the first metal pattern 353a positioned on the first insulating pattern 352a, the silicon pattern 351b, and the silicon pattern A second insulating pattern 352b disposed on 351b and a capacitor lower electrode 353b positioned on the second insulating pattern 352b are formed.

Subsequently, the second photoresist pattern 346 is removed by an ashing process, and the thickness of the first photoresist pattern 345 is reduced by the removed thickness of the second photoresist pattern 346.

Next, referring to FIG. 3E, the first metal pattern 353a in the region where the second photoresist pattern 346 is removed is etched away using an etchant. In addition, the first photoresist pattern 345 remaining on the substrate 310 is stripped and removed.

Accordingly, a first insulating pattern 352a is formed on the active layer 351a and the active layer 351a on the buffer layer 315, and a second insulating pattern (2) is formed on the silicon pattern 351b and the silicon pattern 351b. The capacitor lower electrode 353b is formed on the 352b and the second insulating pattern 352b.

Next, referring to FIG. 3F, a gate insulating layer 360 is formed on the substrate 310. The gate insulating layer 360 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a stacked structure thereof.

Subsequently, the metal oxide layer and the second metal layer are sequentially stacked on the gate insulating layer 360 and patterned by using a first mask to form the gate electrode 370a, the capacitor upper electrode 370b, and the first electrode 370c. Form.

In this case, the metal oxide layer may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). The second metal layer may be a single layer made of aluminum (Al), molybdenum (Mo), tungsten (W), titanium (Ti), or an alloy thereof, and may include molybdenum / aluminum / molybdenum (Mo / Al / Mo) or titanium. It is also possible to form a multilayer of aluminum / titanium (Ti / Al / Ti).

Accordingly, the gate electrode 370a is formed in a structure in which the first metal oxide pattern 371 and the second metal pattern 372 are stacked, and the capacitor upper electrode 370b is formed of the second metal oxide pattern 373 and the third. The metal pattern 374 is formed in a stacked structure, and the first electrode 370c is formed in a stacked structure of the third metal oxide pattern 375 and the fourth metal pattern 376.

Subsequently, an impurity doping process is performed on the substrate 310. At this time, the gate electrode 370a acts as a mask on the active layer 351a so that impurities are doped on both sides of the active layer 351a. Thus, the source region 356 and the drain region 357 are formed in the active layer 351a.

Next, referring to FIG. 3G, an interlayer insulating layer 380 is formed on the substrate 310 on which the impurity doping process is performed. The interlayer insulating layer 380 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a stacked structure thereof.

Subsequently, the interlayer insulating layer 380 is patterned using a second mask to form a contact hole 381 exposing the source region 356 and the drain region 357 of the active layer 351a to form a first electrode ( An opening area 382 exposing 370c is formed.

Next, referring to FIG. 3H, a source layer 385a and a drain electrode 385b are formed by depositing a conductive layer on the substrate 310 and patterning the same using a third mask. In this case, the source electrode 385a and the drain electrode 385b contact the source region 356 and the drain region 357 of the active layer 351a through the contact hole 381, respectively, and the drain electrode 385b is formed of a first electrode. One electrode 370c is contacted.

In this case, during the patterning process using the third mask, the fourth metal pattern 376 of the first electrode 370c is also patterned and positioned only at one edge of the first metal oxide pattern 375. The drain electrode 385b is in contact with the fourth metal pattern 376 of the first electrode 370c.

The source electrode 385a and the drain electrode 385b may be a single layer made of molybdenum (Mo), tungsten (W), titanium (Ti), aluminum (Al), or an alloy thereof. In addition, the source electrode 385a and the drain electrode 385b may be formed of a multilayer of molybdenum / aluminum / molybdenum (Mo / Al / Mo) or titanium / aluminum / titanium (Ti / Al / Ti).

Subsequently, the second photoresist film 400 is coated on the substrate 310 including the source electrode 385a and the drain electrode 385b by spin coating or the like. The second photoresist layer 400 may be made of the same material as the first photoresist layer 335.

Subsequently, after aligning the second halftone mask 390 including the transmissive part 391, the transflective part 392, and the blocking part 393 on the substrate 310 on which the second photoresist film 400 is formed, ultraviolet (UV) light is emitted. Investigate In this case, the blocking portion 393 of the second halftone mask 390 is aligned with the region where the spacer is to be formed, the transflective portion 392 is aligned with the region where the bank layer is to be formed, and the transmitting portion 391 is the first electrode. Align with area 370c.

Next, referring to FIG. 3I, a bank layer 410 and a spacer 415 are formed by developing using a diffraction exposure technique through the second halftone mask 390.

More specifically, by using the diffraction exposure technique using the second halftone mask 390, the blocking portion 393 is applied to the spacer 415 in which the second photosensitive film 400 facing the blocking portion 393 is left as it is. ) And the bank layer 410 remaining less than half the thickness of the spacer 415 by the light transmitted through the second photosensitive film 400 facing the semi-transmissive portion 392 to be transmitted by diffraction. ). The second photosensitive film 400 facing the transmissive portion 391 is decomposed and removed during development, thereby forming an opening 417 that exposes the surface of the first electrode 370c.

Accordingly, as shown in FIG. 3I, the bank layer 410 and the spacer 415 may be simultaneously formed and integrally formed.

Next, the substrate 310 having the bank layer 410 and the spacer 415 formed thereon is mounted in a vacuum chamber, and the shadow mask 420 is aligned on the substrate 310. At this time, the shadow mask 420 is aligned on the spacer 415.

The organic layer is deposited on the substrate 310 to form the organic layer 430 on the first electrode 370c as shown in FIG. 3J. The organic layer 430 may include at least a light emitting layer, and may include at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer.

Next, a second electrode 440 is formed by stacking a metal material on the substrate 310. The second electrode 440 may be made of magnesium (Mg), silver (Ag), aluminum (Al), calcium (Ca), or an alloy thereof having low wiring resistance and work function.

Therefore, the organic light emitting display device according to the exemplary embodiment of the present invention is manufactured by forming the second electrode 440.

As described above, the organic light emitting display device and the manufacturing method thereof according to an embodiment of the present invention, unlike the conventional manufacturing of the organic light emitting display device using a total of nine masks, the first to third masks, The organic light emitting display device may be manufactured using a total of five masks of the first and second halftone masks.

Accordingly, the present invention has the advantage of reducing the total number of masks of four, reducing the manufacturing cost, and improve the productivity and manufacturing yield.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

Claims (8)

Board;
An active layer and a silicon pattern on the substrate;
A first insulating pattern on the active layer and a second insulating pattern on the silicon pattern;
A capacitor lower electrode on the second insulating pattern;
A gate insulating layer on the first insulating pattern and the capacitor lower electrode;
A gate electrode disposed on the gate insulating layer and corresponding to the active layer, a capacitor upper electrode positioned to correspond to the capacitor lower electrode, and a first electrode spaced apart from the gate electrode and the capacitor upper electrode;
An interlayer insulating layer on the gate electrode, the capacitor upper electrode, and the first electrode;
A source electrode and a drain electrode on the interlayer insulating layer and connected to the active layer, one of which is connected to the first electrode;
A bank layer on the substrate including the source electrode and the drain electrode, the bank layer exposing a portion of the first electrode;
A spacer located on the bank layer;
An organic layer disposed on the exposed first electrode; And
An organic light emitting display device comprising a second electrode on the substrate including the organic layer.
The method of claim 1,
The gate electrode has a first metal oxide pattern and a first metal pattern are stacked, the capacitor upper electrode is an organic light emitting display device is a second metal oxide pattern and a second metal pattern is stacked.
The method of claim 1,
The first electrode is an organic light emitting display device in which a third metal oxide pattern and a third metal pattern are stacked.
The method of claim 1,
The spacer is made of the same material as the bank layer.
Sequentially forming a polycrystalline silicon layer, an insulating layer, and a first metal layer on the substrate;
After applying a first photoresist film on the substrate, patterning using a first halftone mask to form an active layer and a silicon pattern, and at the same time to form a first insulating pattern on the active layer and on the silicon pattern Forming a second insulating pattern and forming a capacitor lower electrode on the second insulating pattern;
Forming a gate insulating film on the active layer and the capacitor lower electrode;
A metal oxide layer and a second metal layer are sequentially stacked and patterned on the gate insulating layer to form a gate electrode on which a first metal oxide pattern and a second metal pattern are stacked, and a capacitor on which a second metal oxide pattern and a third metal pattern are stacked. Forming a first electrode on which the upper electrode, the third metal oxide pattern, and the fourth metal pattern are stacked;
Forming an interlayer insulating layer on the gate electrode, the capacitor upper electrode, and the first electrode;
Stacking and patterning a third metal layer on the interlayer insulating layer to form a source electrode and a drain electrode, and simultaneously patterning a fourth metal pattern on the first electrode;
Forming a bank layer and a spacer by coating a second photosensitive film on a substrate including the source electrode, the drain electrode, and the first electrode, and then patterning the same using a second halftone mask;
Forming an organic layer on the first electrode; And
And forming a second electrode on the substrate including the organic layer.
6. The method of claim 5,
Forming the polycrystalline silicon layer, the insulating layer, and the first metal layer sequentially,
Forming an amorphous silicon layer on the substrate;
Irradiating the amorphous silicon layer with a laser to crystallize the polycrystalline silicon layer;
Forming an insulating layer on the polycrystalline silicon layer; And
And forming the first metal layer on the insulating layer.
The method according to claim 6,
Forming the active layer and the silicon pattern, and simultaneously forming a first insulating pattern on the active layer, a second insulating pattern on the silicon pattern, and forming a capacitor lower electrode on the second insulating pattern ,
After applying the first photoresist film on the first metal layer, forming a first photoresist pattern and a second photoresist pattern having a thickness step using the first halftone mask;
Etching the polycrystalline silicon layer, the insulating layer, and the first metal layer to form the active layer, the silicon pattern, a first insulating pattern on the active layer, a second insulating pattern on the silicon pattern, and Forming a first metal pattern on the first insulating pattern and a capacitor lower electrode on the second insulating pattern;
Ashing the first photoresist pattern and the second photoresist pattern to reduce the thickness of the first photoresist pattern and to remove the second photoresist pattern;
Etching and removing the exposed first metal pattern by removing the second photoresist pattern; And
A method of manufacturing an organic light emitting display device comprising removing the first photoresist pattern.
6. The method of claim 5,
Forming the bank layer and the spacer,
Applying a second photosensitive film on the substrate;
Exposing and then aligning said second halftone mask on said second photosensitive film; And
Developing the exposed second photoresist to form a bank layer and a spacer.

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