KR101315859B1 - Circuit for auto gain control output of tuner - Google Patents

Circuit for auto gain control output of tuner Download PDF

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KR101315859B1
KR101315859B1 KR1020070101394A KR20070101394A KR101315859B1 KR 101315859 B1 KR101315859 B1 KR 101315859B1 KR 1020070101394 A KR1020070101394 A KR 1020070101394A KR 20070101394 A KR20070101394 A KR 20070101394A KR 101315859 B1 KR101315859 B1 KR 101315859B1
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gain control
automatic gain
control output
circuit
tuner
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KR1020070101394A
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Korean (ko)
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KR20090036302A (en
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김보용
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엘지이노텍 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/52—Automatic gain control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
    • H03G3/301—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being continuously variable
    • H03G3/3015—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being continuously variable using diodes or transistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/455—Demodulation-circuits

Abstract

본 발명은 튜너의 자동이득제어 출력회로에 관한 것이다.

본 발명은 복조 집적회로에서 검출된 자동이득제어 전압을 고주파증폭기에 공급하는 자동이득제어 출력부에 전류제어부와 버퍼회로를 구비하여 상기 전류제어부와 버퍼회로를 통해서 상기 복조 집적회로의 자동이득제어 전압을 상기 고주파증폭기에 입력함으로써, 상기 자동이득제어 출력부는 자동이득제어 전압 변화에 의한 전류 흐름이 제어되게 되어 리플을 제거할 수 있게 되는 것이다.

Figure R1020070101394

튜너, 자동이득제어출력, 리플

The present invention relates to an automatic gain control output circuit of a tuner.

The present invention includes a current control unit and a buffer circuit in an automatic gain control output unit for supplying the automatic gain control voltage detected by the demodulation integrated circuit to a high frequency amplifier, and through the current control unit and the buffer circuit, the automatic gain control voltage of the demodulation integrated circuit. By inputting to the high-frequency amplifier, the automatic gain control output unit is to control the current flow due to the automatic gain control voltage change to be able to remove the ripple.

Figure R1020070101394

Tuner, Automatic Gain Control Output, Ripple

Description

튜너의 자동이득제어 출력회로{CIRCUIT FOR AUTO GAIN CONTROL OUTPUT OF TUNER}Tuner automatic gain control output circuit {CIRCUIT FOR AUTO GAIN CONTROL OUTPUT OF TUNER}

도 1은 종래 튜너의 자동이득제어 출력회로도1 is an automatic gain control output circuit diagram of a conventional tuner.

도 2는 본 발명의 일 실시예에 따른 튜너의 자동이득제어 출력회로도2 is an automatic gain control output circuit diagram of a tuner according to an embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명*Description of the Related Art [0002]

21; 복조 집적회로 22; 자동이득제어 출력부21; Demodulation integrated circuit 22; Automatic Gain Control Output

221; 전류제어부 222; 버퍼회로221; Current control unit 222; Buffer circuit

23; 고주파 증폭기23; High frequency amplifier

본 발명은 튜너의 자동이득제어 출력회로에 관한 것이다.The present invention relates to an automatic gain control output circuit of a tuner.

일반적으로 입력되는 고주파신호 레벨에 따라 자동이득제어 전압을 출력하게 되는 튜너의 자동이득제어 출력회로는 도 1에 도시한 바와 같이, 중간주파수신호를 복조하는 복조 집적회로(11)와, 상기 복조 집적회로(11)에서 중간주파수의 신호레벨에 따른 전압이득을 자동 제어하는 자동이득제어기(AGC)로부터 검출되는 고주파 자동이득제어 전압을 출력하는 자동이득제어 출력부(12)와; 상기 자동이득제어 출 력부(12)로부터 출력되는 자동이득제어 전압에 의하여 증폭 구동하는 고주파증폭기(13)로 구성되게 된다.In general, an automatic gain control output circuit of a tuner that outputs an automatic gain control voltage according to an input high frequency signal level includes a demodulation integrated circuit 11 that demodulates an intermediate frequency signal, as shown in FIG. An automatic gain control output unit 12 for outputting a high frequency automatic gain control voltage detected from an automatic gain controller AGC for automatically controlling voltage gain according to a signal level of an intermediate frequency in the circuit 11; The automatic gain control output unit 12 is configured to include a high frequency amplifier 13 for amplifying and driving by the automatic gain control voltage output.

상기 자동이득제어 출력부(12)는 복조 집적회로(11)의 자동이득제어기(AGC)의 출력단과 상기 고주파증폭기(13) 사이에 분압저항(R1)(R2)과, 저항(R3),콘덴서(C2)로 구성된 시정수회로 및 바이패스 콘덴서(C2)로 구성되게 된다.The automatic gain control output unit 12 divides the voltage divider R1, R2, resistor R3, and capacitor between the output terminal of the automatic gain controller AGC of the demodulation integrated circuit 11 and the high frequency amplifier 13. It consists of a time constant circuit composed of (C2) and a bypass capacitor (C2).

따라서 상기 복조 집적회로(11)의 자동이득제어기(AGC)에서 검출되는 자동이득제어 전압은 상기 자동이득제어 출력부(12)의 분압저항(R1)(R2)과, 저항(R3),콘덴서(C2)로 구성된 시정수회로 및 바이패스 콘덴서(C2)를 통해서 상기 고주파증폭기(13)에 출력하게 된다.Therefore, the automatic gain control voltage detected by the automatic gain controller AGC of the demodulation integrated circuit 11 includes the divided resistors R1 and R2 of the automatic gain control output unit 12, the resistor R3, and the capacitors. It outputs to the high frequency amplifier 13 through a time constant circuit composed of C2) and a bypass capacitor C2.

이때 상기 자동이득제어 출력부(12)에는 입력신호의 세기에 따라 자동이득제어 전압이 변하면서 전류가 상기 고주파증폭기(13) 또는 복조 집적회로(11) 방향으로 흐르게 되며, 신호 수신방식이 엔티에스씨(NTSC)나 팔(PAL) 방식의 경우 시정수회로의 저항(R3)을 통해서 복조 집적회로(11) 방향으로 들어오는 전류에 의해서 문제가 되고, 세캄(SECAM) 방식의 경우에는 시정수회로의 저항(R3)을 통해서 고주파증폭기(13)로 나가는 방향과 상기 복조 집적회로(11) 방향으로 들어오는 전류 모두에 의해서 문제가 되어 리플이 발생하게 된다.At this time, the automatic gain control output unit 12 changes the automatic gain control voltage according to the intensity of the input signal, and a current flows in the direction of the high frequency amplifier 13 or the demodulation integrated circuit 11, and the signal receiving method is ENT. In case of NTSC or PAL, it is a problem due to the current coming into the demodulation integrated circuit 11 through the resistance R3 of the time constant circuit, and in the case of the SECAM method, Ripple occurs due to both the current flowing into the high frequency amplifier 13 through the resistor R3 and the current flowing into the demodulation integrated circuit 11.

그래서 상기 전류에 의한 문제를 최소화하기 위하여 상기 자동이득제어 출력부(12)에 최대한 작은 전류가 흐르도록 상기 시정수회로의 저항(R3)의 값을 크게 하면, 전압 강하가 크게 되어 상기 고주파증폭기(13)에 전원 공급이 되지 않는 문제점이 있다.Therefore, in order to minimize the problem caused by the current, when the value of the resistance R3 of the time constant circuit is increased so that the smallest current flows through the automatic gain control output unit 12, the voltage drop becomes large and the high frequency amplifier ( 13) there is a problem that the power supply is not.

본 발명은 자동이득제어 출력회로에 리플을 제거한다.The present invention eliminates ripple in the automatic gain control output circuit.

본 발명은 복조회로와; 상기 복조회로로부터 자동이득제어 전압을 고주파증폭기에 출력하는 자동이득제어 출력부를 포함하는 튜너의 자동이득제어 출력회로가 자동이득제어 전압에 따라 전류 흐름을 제어하는 전류제어부와, 상기 전류제어부를 통해서 입력되는 자동이득제어 전압을 완충하여 상기 고주파증폭기에 출력하는 버퍼회로를 포함한다.The present invention provides a demodulation circuit; A current control unit for controlling the current flow according to the automatic gain control voltage of the tuner's automatic gain control output circuit including an automatic gain control output unit for outputting the automatic gain control voltage from the demodulation circuit to the high frequency amplifier; And a buffer circuit which buffers the input automatic gain control voltage and outputs the same to the high frequency amplifier.

이하 첨부되는 도면에 의거 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일 실시예에 따른 튜너의 자동이득제어 출력회로도이다.2 is an automatic gain control output circuit diagram of a tuner according to an embodiment of the present invention.

복조 집적회로(21)는 입력되는 중간주파수를 원래 방송 채널신호를 복조하여 출력하게 되며, 상기 복조 집적회로(21)에는 입력되는 중간주파수의 강도에 따른 전압 이득을 자동제어하는 자동이득제어기(AGC)가 구비된다.The demodulation integrated circuit 21 demodulates and outputs the original broadcast channel signal at the inputted intermediate frequency, and the automatic gain controller (AGC) automatically controls the voltage gain according to the strength of the inputted intermediate frequency. ) Is provided.

상기 자동이득제어 출력부(22)는 상기 복조 집적회로(21)의 자동이득제어기(AGC)에서 검출되는 자동이득제어 전압을 출력하게 되며, 상기 자동이득제어 출력부(22)는 전류 흐름을 제어하는 전류제어부(221)와 자동이득제어 전압을 완충하는 버퍼회로(222)로 구성된다.The automatic gain control output unit 22 outputs an automatic gain control voltage detected by the automatic gain controller AGC of the demodulation integrated circuit 21, and the automatic gain control output unit 22 controls the current flow. It consists of a current control unit 221 and a buffer circuit 222 for buffering the automatic gain control voltage.

상기 전류제어부(221)는 바이어스 저항(R21), 저항(R22), 바이패스 콘덴서(C21)로 구성된다.The current controller 221 includes a bias resistor R21, a resistor R22, and a bypass capacitor C21.

상기 버퍼회로(222)는 베이스단자에 입력되는 자동이득제어 전압을 콜렉터단 자의 바이어스 전압에 의하여 에미터단자로 출력하는 트랜지스터(Q1)로 구현된다.The buffer circuit 222 is implemented with a transistor Q1 for outputting the automatic gain control voltage input to the base terminal to the emitter terminal by the bias voltage of the collector terminal.

고주파증폭기(23)는 상기 자동이득제어 출력부(22)에서 출력되는 자동이득제어 전압을 증폭하여 출력하게 되며, 상기 고주파증폭기(23)는 전계효과트랜지스터(FET)로 구성된다.The high frequency amplifier 23 amplifies and outputs the automatic gain control voltage output from the automatic gain control output unit 22, and the high frequency amplifier 23 is composed of a field effect transistor (FET).

상기와 같이 구성되는 본 발명은 복조 집적회로(21)에 중간주파수가 입력되게 되면, 상기 입력된 중간주파수는 자동이득제어기(AGC)에 의하여 신호레벨을 검출하여 이 검출된 신호 레벨에 따른 자동이득제어 전압을 자동이득제어 출력부(22)로 출력하게 된다.According to the present invention configured as described above, when an intermediate frequency is input to the demodulation integrated circuit 21, the input intermediate frequency detects a signal level by an automatic gain controller (AGC) to automatically gain according to the detected signal level. The control voltage is output to the automatic gain control output unit 22.

상기 자동이득제어 출력부(22)에서는 입력된 자동이득제어 전압을 전류제어부(221)의 바이어스 저항(R21), 저항(R22) 및 바이패스 콘덴서(C21)를 통해서 버퍼회로(222)의 트랜지스터(Q1)의 베이스단자에 입력하게 된다.The automatic gain control output unit 22 inputs the input automatic gain control voltage to the transistor of the buffer circuit 222 through the bias resistor R21, the resistor R22, and the bypass capacitor C21 of the current controller 221. Input to the base terminal of Q1).

상기 버퍼회로(222)의 트랜지스터(Q1)는 베이스단자로 입력된 자동이득제어 전압을 콜렉터단자의 바이어스 전압에 의하여 에미터단자를 통해서 고주파증폭기(23)에 입력되게 된다.The transistor Q1 of the buffer circuit 222 inputs the automatic gain control voltage input to the base terminal to the high frequency amplifier 23 through the emitter terminal by the bias voltage of the collector terminal.

이때 상기 버퍼회로(222)의 트랜지스터(Q1)의 베이스단자에 걸리는 전압은 콜렉터단자의 바이어스 전압에 의해 에미터단자에 걸리는 전압과 동일 전위를 유지하게 되므로, 상기 트랜지스터(Q1)의 베이스단자에 입력되는 자동이득제어 전압은 에미터단자를 통해서 고주파증폭기(23)에 정상적으로 입력되게 된다.At this time, since the voltage applied to the base terminal of the transistor Q1 of the buffer circuit 222 maintains the same potential as the voltage applied to the emitter terminal by the bias voltage of the collector terminal, it is input to the base terminal of the transistor Q1. The automatic gain control voltage is normally input to the high frequency amplifier 23 through the emitter terminal.

그리고 상기 자동이득제어 출력부(22)에서는 입력신호의 세기에 따라 변화하는 자동이득제어 전압에 의한 전류 흐름을 상기 전류제어부(221)의 바이어스저 항(R21)과 저항(R22)으로 각각 제어되게 되므로 리플을 제거할 수 있게 된다.The automatic gain control output unit 22 controls the current flow due to the automatic gain control voltage which is changed according to the strength of the input signal by the bias resistor R21 and the resistor R22 of the current control unit 221, respectively. This eliminates ripple.

이상에서 설명한 바와 같이 본 발명은 복조 집적회로에서 검출된 자동이득제어 전압을 고주파증폭기에 공급하는 자동이득제어 출력부에 전류제어부와 버퍼회로를 구비하여 상기 전류제어부와 버퍼회로를 통해서 상기 복조 집적회로의 자동이득제어 전압을 상기 고주파증폭기에 입력함으로써, 상기 자동이득제어 출력부는 자동이득제어 전압 변화에 의한 전류 흐름이 제어되게 되어 리플을 제거할 수 있게 되는 것이다.As described above, the present invention includes a current control unit and a buffer circuit in an automatic gain control output unit for supplying an automatic gain control voltage detected by a demodulation integrated circuit to a high frequency amplifier, and provides the demodulation integrated circuit through the current control unit and the buffer circuit. By inputting the automatic gain control voltage of the high frequency amplifier, the automatic gain control output unit is to control the current flow due to the automatic gain control voltage change to eliminate the ripple.

Claims (3)

복조회로와; 상기 복조회로로부터 자동이득제어 전압을 고주파증폭기에 출력하는 자동이득제어 출력부를 포함하는 튜너의 자동이득제어 출력회로가 자동이득제어 전압에 따라 전류 흐름을 제어하는 전류제어부와, 상기 전류제어부를 통해서 입력되는 자동이득제어 전압을 완충하여 상기 고주파증폭기에 출력하는 버퍼회로를 포함하는 튜너의 자동이득제어 출력회로.A demodulation circuit; A current control unit for controlling the current flow according to the automatic gain control voltage of the tuner's automatic gain control output circuit including an automatic gain control output unit for outputting the automatic gain control voltage from the demodulation circuit to the high frequency amplifier; A tuner automatic gain control output circuit comprising a buffer circuit for buffering an inputted automatic gain control voltage and outputting the same to the high frequency amplifier. 제 1 항에 있어서, 상기 전류제어부는 바이어스 저항, 저항 및 바이패스 콘덴서로 포함한 것을 특징으로 하는 튜너의 자동이득제어 출력회로.The tuner's automatic gain control output circuit of claim 1, wherein the current control unit comprises a bias resistor, a resistor, and a bypass capacitor. 제 1 항에 있어서, 상기 버퍼회로는 베이스단자에 입력되는 자동이득제어 전압을 콜렉터단자의 바이어스 전압에 의하여 에미터단자로 출력하는 트랜지스터로 구성한 것을 특징으로 하는 튜너의 자동이득제어 출력회로.The tuner automatic gain control output circuit according to claim 1, wherein the buffer circuit comprises a transistor for outputting the automatic gain control voltage input to the base terminal to the emitter terminal according to the bias voltage of the collector terminal.
KR1020070101394A 2007-10-09 2007-10-09 Circuit for auto gain control output of tuner KR101315859B1 (en)

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Publication number Priority date Publication date Assignee Title
CN108718208A (en) * 2018-06-29 2018-10-30 河南中多科技发展有限公司 Communicating circuit under a kind of rolling lands D

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KR19990002512A (en) * 1997-06-20 1999-01-15 윤종용 Gain control method and apparatus for broadcast reception signal
KR0177676B1 (en) * 1996-04-04 1999-04-01 이형도 Agc delay time tuning circuit
JP2006516866A (en) 2003-01-31 2006-07-06 ノキア コーポレイション Apparatus and related method for increasing reception sensitivity of direct conversion receiver
KR20070077572A (en) * 2006-01-24 2007-07-27 엘지이노텍 주식회사 Lna controlling circuit of tuner

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0177676B1 (en) * 1996-04-04 1999-04-01 이형도 Agc delay time tuning circuit
KR19990002512A (en) * 1997-06-20 1999-01-15 윤종용 Gain control method and apparatus for broadcast reception signal
JP2006516866A (en) 2003-01-31 2006-07-06 ノキア コーポレイション Apparatus and related method for increasing reception sensitivity of direct conversion receiver
KR20070077572A (en) * 2006-01-24 2007-07-27 엘지이노텍 주식회사 Lna controlling circuit of tuner

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108718208A (en) * 2018-06-29 2018-10-30 河南中多科技发展有限公司 Communicating circuit under a kind of rolling lands D
CN108718208B (en) * 2018-06-29 2024-04-09 河南中多科技发展有限公司 D wave underground communication circuit

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