KR101308459B1 - Thin film transistor substrate and method of fabricating the same - Google Patents

Thin film transistor substrate and method of fabricating the same Download PDF

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KR101308459B1
KR101308459B1 KR1020070038302A KR20070038302A KR101308459B1 KR 101308459 B1 KR101308459 B1 KR 101308459B1 KR 1020070038302 A KR1020070038302 A KR 1020070038302A KR 20070038302 A KR20070038302 A KR 20070038302A KR 101308459 B1 KR101308459 B1 KR 101308459B1
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thin film
film transistor
electrode
data line
active layer
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KR20080094188A (en
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이정우
채기성
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엘지디스플레이 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Thin Film Transistor (AREA)

Abstract

본 발명은 전류 제어를 용이하게 할 수 있는 박막트랜지스터기판 및 그 제조방법에 관한 것이다.The present invention relates to a thin film transistor substrate capable of facilitating current control and a method of manufacturing the same.

본 발명에 따른 박막트랜지스터기판은 서로 교차되는 게이트라인 및 데이터라인과; 상기 게이트라인 및 데이터라인의 교차영역에 형성되는 박막트랜지스터와; 상기 박막트랜지스터의 드레인전극과 접속되도록 형성되는 화소전극과; 상기 데이터라인과 연결되며 상기 박막트랜지스터의 채널부와 중첩되도록 형성되는 전류제어전극을 포함하는 것을 특징으로 한다.The thin film transistor substrate according to the present invention includes a gate line and a data line crossing each other; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode formed to be connected to the drain electrode of the thin film transistor; And a current control electrode connected to the data line and overlapping the channel portion of the thin film transistor.

액정표시장치, 화소전극, 전류제어전극 LCD, pixel electrode, current control electrode

Description

박막트랜지스터기판 및 그 제조방법{THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME}Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME}

도 1은 종래의 박막트랜지스터의 전류-전압 동작 특성을 나타낸 도면.1 is a view showing the current-voltage operating characteristics of a conventional thin film transistor.

도 2는 본 발명에 따른 박막트랜지스터기판을 나타내는 평면도.2 is a plan view showing a thin film transistor substrate according to the present invention.

도 3은 도 2에 도시된 박막트랜지스터기판의 Ⅰ-Ⅰ' 선을 따라 절취한 단면도.3 is a cross-sectional view taken along line II ′ of the thin film transistor substrate illustrated in FIG. 2.

도 4는 도 2에 도시된 박막트랜지스터기판의 Ⅱ-Ⅱ'선을 따라 절취한 단면도.4 is a cross-sectional view taken along the line II-II 'of the thin film transistor substrate shown in FIG.

도 5는 본 발명에 따른 박막트랜지스터기판을 나타내는 회로도.5 is a circuit diagram showing a thin film transistor substrate according to the present invention.

도 6은 본 발명에 따른 박막트랜지스터의 전류-전압 동작 특성을 나타낸 도면.6 is a view showing the current-voltage operating characteristics of the thin film transistor according to the present invention.

도 7a 내지 도 7g는 본 발명에 따른 박막트랜지스터기판을 제조하는 방법을 나타낸 도면. 7A to 7G illustrate a method of manufacturing a thin film transistor substrate according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 * Explanation of symbols on the main parts of the drawings

2: 게이트 라인 4: 데이터 라인2: gate line 4: data line

6: 박막트랜지스터 8: 게이트 전극6: thin film transistor 8: gate electrode

10: 소스전극 12: 드레인전극10: source electrode 12: drain electrode

14: 활성층 18: 화소전극14: active layer 18: pixel electrode

20: 전류전극 42: 하부기판20: current electrode 42: lower substrate

44: 게이트 절연막 48: 오믹접촉층44: gate insulating film 48: ohmic contact layer

본 발명은 박막트랜지스터기판에 관한 것으로, 특히 전류 제어를 용이하게 할 수 있는 박막트랜지스터기판 및 그 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate capable of facilitating current control and a method of manufacturing the same.

초박형의 평판표시소자(Flat Pane Display), 그 중에서도 액정표시장치는 동작 전압이 낮아 소비 전력이 적고 휴대용으로 쓰일 수 있는 등의 이점으로 TV, 노트북 컴퓨터, 모니터, 우주선, 항공기 등에 이르기까지 응용분야가 넓고 다양하다.Ultra-thin flat panel display, especially liquid crystal display, has low operating voltage and low power consumption, so it can be used as a portable device.It can be applied to TV, notebook computer, monitor, spacecraft, aircraft, etc. Wide and diverse

일반적으로 액정표시장치는 게이트 신호를 전달하는 다수의 게이트 라인과, 이 게이트 라인에 교차하며 데이터 신호를 전달하는 다수의 데이터 라인을 포함하며, 이들 게이트 라인과 데이터 라인의 교차부마다 형성되는 박막트랜지스터(Thin Film Transistor)와, 게이트 라인과 데이터 라인에 의해 둘러싸인 화소영역에 박막트랜지스터를 통해 연결되는 행렬 형태의 다수의 화소전극을 포함한다.In general, a liquid crystal display device includes a plurality of gate lines for transmitting a gate signal and a plurality of data lines crossing the gate lines and for transmitting a data signal, and a thin film transistor formed at each intersection of the gate lines and the data lines. (Thin Film Transistor) and a plurality of pixel electrodes in a matrix form connected to the pixel region surrounded by the gate line and the data line through a thin film transistor.

이러한 액정표시장치의 박막트랜지스터는 게이트 라인에 공급되는 게이트 신호에 응답하여 데이터 라인에 공급되는 데이터 신호를 화소전극에 공급한다. 이 때, 박막트랜지스터의 전류-전압 동작 특성을 살펴보면 도 1에 도시된 바와 같이, 턴-온된 박막트랜지스터에 인가되는 데이터 전압이 증가하면 할수록 화소전극에 공 급되는 데이터 전류가 증가하나, 일정수준의 데이터 전압 이상부터는 데이터 전압이 어느 정도 이상 증가하여도 데이터 전류가 그다지 증가하지 않게 되는 포화곡선(saturation curve) 특성을 보인다.The thin film transistor of the liquid crystal display supplies a data signal supplied to the data line to the pixel electrode in response to the gate signal supplied to the gate line. In this case, the current-voltage operation characteristics of the thin film transistor are shown in FIG. 1, as the data voltage applied to the turned-on thin film transistor increases, the data current supplied to the pixel electrode increases. Above the data voltage, a saturation curve characteristic shows that the data current does not increase much even if the data voltage increases to some extent.

따라서, 이와 같은 포화곡선 특성을 개선하기 위하여 박막트랜지스터의 데이터 전류특성이 선형에 가깝게 나타나도록 하여 데이터 전류제어를 용이하게 할 수 있는 박막트랜지스터 기판이 요구되고 있다.Accordingly, in order to improve such saturation curve characteristics, a thin film transistor substrate is required which allows data current characteristics of the thin film transistor to be nearly linear, thereby facilitating data current control.

따라서, 상기와 같은 문제점을 해결하기 위하여, 본 발명은 전류 제어를 용이하게 할 수 있는 박막트랜지스터기판 및 그 제조방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a thin film transistor substrate and a method of manufacturing the same that can facilitate current control.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 박막트랜지스터기판은 서로 교차되는 게이트라인 및 데이터라인과; 상기 게이트라인 및 데이터라인의 교차영역에 형성되는 박막트랜지스터와; 상기 박막트랜지스터의 드레인전극과 접속되도록 형성되는 화소전극과; 상기 데이터라인과 연결되며 상기 박막트랜지스터의 채널부와 중첩되도록 형성되는 전류제어전극을 포함하는 것을 특징으로 한다.In order to achieve the above technical problem, the thin film transistor substrate according to the present invention comprises a gate line and a data line crossing each other; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode formed to be connected to the drain electrode of the thin film transistor; And a current control electrode connected to the data line and overlapping the channel portion of the thin film transistor.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 박막트랜지스터기판의 제조방법은 게이트라인 및 데이터라인의 교차영역에 박막트랜지스터를 형성하는 단계와; 상기 박막트랜지스터의 드레인전극과 접속되도록 화소전극을 형성하는 단계와; 상기 데이터라인과 연결되며 상기 박막트랜지스터의 채널부와 중첩되도록 전류 제어전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above technical problem, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a thin film transistor in the intersection region of the gate line and the data line; Forming a pixel electrode to be connected to the drain electrode of the thin film transistor; And forming a current control electrode connected to the data line and overlapping the channel portion of the thin film transistor.

이하, 첨부된 도면을 참조하여 본 발명에 따른 박막트랜지스터기판을 상세히 설명하면 다음과 같다.Hereinafter, a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 박막트랜지스터기판을 나타내는 평면도이고, 도 3은 도 2에 도시된 박막트랜지스터기판의 Ⅰ-Ⅰ' 선을 따라 절취한 단면도이고, 도 4는 도 2에 도시된 박막트랜지스터의 Ⅱ-Ⅱ'선을 따라 절취한 단면도이다.2 is a plan view showing a thin film transistor substrate according to the present invention, FIG. 3 is a cross-sectional view taken along the line II ′ of the thin film transistor substrate illustrated in FIG. 2, and FIG. 4 is a cross-sectional view of the thin film transistor illustrated in FIG. 2. Sectional drawing cut along the line II-II '.

도 2 내지 도 4에 도시된 바와 같이, 본 발명에 따른 박막트랜지스터기판은 하부기판(42) 위에 게이트 절연막(44)을 사이에 두고 교차하게 형성된 게이트라인(2) 및 데이터 라인(4)과, 그 교차부마다 형성된 박막트랜지스터(Thin Film Transistor)(6)와, 그 교차 구조로 마련된 화소영역에 형성된 화소전극(18)과, 박막트랜지스터(6) 상부에 형성된 전류제어전극(20)을 구비한다.2 to 4, the thin film transistor substrate according to the present invention includes a gate line 2 and a data line 4 formed on the lower substrate 42 to intersect with the gate insulating film 44 interposed therebetween, A thin film transistor 6 formed at each intersection thereof, a pixel electrode 18 formed in the pixel region provided in the crossing structure, and a current control electrode 20 formed on the thin film transistor 6; .

게이트 라인(2)은 접속된 박막트랜지스터(6)의 게이트 전극(8)에 게이트 신호를 공급한다.The gate line 2 supplies a gate signal to the gate electrode 8 of the connected thin film transistor 6.

데이터 라인(4)은 게이트 라인(2)과 교차하여 화소 영역을 마련한다. 이러한 데이터 라인(4)은 박막트랜지스터(6)의 드레인 전극(12)에 데이터 신호를 공급한다.The data line 4 intersects the gate line 2 to form a pixel region. The data line 4 supplies a data signal to the drain electrode 12 of the thin film transistor 6.

박막트랜지스터(6)는 게이트 라인(2)의 게이트 신호에 응답하여 데이터 라인(4) 상의 데이터 신호가 화소영역의 화소 전극(18)에 충전되어 유지되게 한다. 이를 위해, 박막트랜지스터(6)는 게이트라인(2)에 접속된 게이트전극(8)과, 데이터라인(4)과 접속된 소스전극(12)과, 화소전극(18)과 접속된 드레인전극(10)과, 게이 트전극(8)과 중첩되고 소스전극(12)과 드레인전극(10) 사이에 채널을 형성하는 활성층(14)을 구비한다. 활성층(14) 위에는 데이터라인(4), 소스전극(10) 및 드레인전극(12)과 오믹 접촉을 위한 오믹접촉층(21)이 더 형성된다.The thin film transistor 6 keeps the data signal on the data line 4 charged and held in the pixel electrode 18 in the pixel region in response to the gate signal of the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 12 connected to the data line 4, and a drain electrode connected to the pixel electrode 18. 10 and an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 12 and the drain electrode 10. An ohmic contact layer 21 for ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14.

화소전극(18)은 데이터라인(4)과 게이트라인(2)에 의해 형성된 화소 영역에 위치하며 인듐-틴-옥사이드(indium-tin-oxide : ITO)와 같이 광투과율이 높은 투명전도성 물질로 이루어진다. 화소전극(18)은 하부기판(42) 전면에 도포되는 보호막(50) 상에 형성되며, 보호막(50)을 관통하는 드레인콘택홀(16)을 통해 박막트랜지스터(6)의 드레인전극(10)과 접속된다. 이러한 화소전극(18)은 박막트랜지스터(TFT)를 통해 공급된 화소전압에 의해 도시되지 않은 상부기판에 형성되는 공통전극과 전위차를 발생시키게 된다.The pixel electrode 18 is positioned in the pixel region formed by the data line 4 and the gate line 2 and is made of a transparent conductive material having high light transmittance, such as indium-tin-oxide (ITO). . The pixel electrode 18 is formed on the passivation layer 50 coated on the entire surface of the lower substrate 42, and the drain electrode 10 of the thin film transistor 6 is formed through the drain contact hole 16 penetrating the passivation layer 50. Connected with. The pixel electrode 18 generates a potential difference from a common electrode formed on the upper substrate (not shown) by the pixel voltage supplied through the thin film transistor TFT.

전류제어전극(20)은 보호막(50)을 관통하는 소스콘택홀(15)을 통해 박막트랜지스터(6)의 소스전극(12)과 접속된다. 이러한 전류제어전극(20)은 게이트절연막(44), 활성층(14) 및 보호막(50)을 사이에 두고 게이트전극(8)과 중첩되도록 형성된다. 이에 따라, 전류제어전극(20)은 도 5에 도시된 바와 같이, 박막트랜지스터(6)와 병렬로 연결된 전류제어트랜지스터(22)의 게이트전극 및 소스전극으로 이용된다. 이러한 전류제어전극(20)은 데이터라인(4)으로부터 데이터신호가 공급되면, 활성층(14)의 상부에 전하를 유도시킨다. 따라서, 게이트전극(8)에 게이트온전압이 공급되면, 전계효과에 의하여 활성층(14)의 하부에 전하가 유도됨과 동시에 전류제어전극(20)에 데이터전압이 공급되면, 활성층(14) 상부에 전하가 유도된다. 이와 같이, 활성층(14) 하부 및 상부에 유도된 전하로 인해 소스-드레인 전 극(10,12) 사이의 바이어스 전압에 의해 이동하게 되는 전하가 많아지게 됨으로써 보다 강한 데이터 전류가 흐르게 된다. 이와 같이, 전류제어전극(20)으로 인해 보다 많은 전하가 이동하게 되기 때문에 같은 데이터 전압을 인가하여도 화소전극(18)에 공급되는 데이터 전류가 증가하게 됨으로써 박막트랜지스터(6)의 전류-전압 동작 특성이 도 6에 도시된 바와 같이, 선형에 가깝게 나타나게 된다. 이렇게 박막트랜지스터(6)의 전류-전압 동작 특성이 선형에 가깝게 나타나게 되면 일정수준의 데이터 전압 이상부터는 데이터 전압이 어느 정도 이상 증가하여도 데이터 전류가 그다지 증가하지 않게 되는 포화곡선(saturation curve) 특성의 단점을 보완하게 된다. 즉, 데이터 전압이 어느 정도 이상 증가하여도 데이터 전류가 그에 비례해서 증가하게 되기 때문에 데이터 전류의 제어가 보다 용이하게 된다.The current control electrode 20 is connected to the source electrode 12 of the thin film transistor 6 through the source contact hole 15 penetrating the protective film 50. The current control electrode 20 is formed to overlap the gate electrode 8 with the gate insulating film 44, the active layer 14, and the passivation film 50 interposed therebetween. Accordingly, the current control electrode 20 is used as a gate electrode and a source electrode of the current control transistor 22 connected in parallel with the thin film transistor 6, as shown in FIG. When the data signal is supplied from the data line 4, the current control electrode 20 induces charge on the active layer 14. Therefore, when the gate-on voltage is supplied to the gate electrode 8, charge is induced to the lower portion of the active layer 14 by the electric field effect and at the same time the data voltage is supplied to the current control electrode 20, the upper portion of the active layer 14 is applied. Charge is induced. As such, the charges induced in the lower and upper portions of the active layer 14 cause the charges to be moved by the bias voltage between the source-drain electrodes 10 and 12 to be increased, so that a stronger data current flows. As such, since more electric charges are moved by the current control electrode 20, the data current supplied to the pixel electrode 18 increases even when the same data voltage is applied, thereby making the current-voltage operation of the thin film transistor 6. As shown in FIG. 6, the characteristics appear close to linear. When the current-voltage operating characteristic of the thin film transistor 6 is almost linear, the saturation curve characteristic of the data current does not increase much even if the data voltage increases to a certain level from above the data voltage of a certain level. It will make up for the shortcomings. That is, even if the data voltage increases to some extent or more, the data current increases in proportion, thereby making it easier to control the data current.

여기서 활성층(14)은 활성층(14)의 상부에 유도된 전하와 활성층(14)의 하부에 유도된 전하가 서로 합류가 잘 되게 하기 위해 800~1000Å두께로 형성된다. 이때, 활성층(14)의 두께가 800Å미만이면, 활성층(14)이 단선될 위험이 있으며, 활성층(14)의 두께가 1000Å보다 크면, 활성층(14) 상부에 유도된 전하와 활성층(14) 하부에 유도된 전하가 제대로 합류되지 못하게 된다. 또한, 유도된 전하가 서로 합류가 잘 되게 하기 위해 활성층(14)의 게이트절연막(44)을 사이에 두고 게이트전극(8)과 중첩된 부분이 활성층(14)의 나머지 부분보다 얇게 형성되는 것이 바람직하다. In this case, the active layer 14 is formed to have a thickness of 800 to 1000 mW so that the charge induced in the upper portion of the active layer 14 and the charge induced in the lower portion of the active layer 14 are well joined to each other. At this time, if the thickness of the active layer 14 is less than 800 μs, there is a risk that the active layer 14 is disconnected. If the thickness of the active layer 14 is greater than 1000 μs, the charge induced on the active layer 14 and the lower portion of the active layer 14 are lower. The electric charges induced by the ions do not merge properly. In addition, in order for the induced charges to merge with each other, it is preferable that a portion overlapping the gate electrode 8 is formed to be thinner than the rest of the active layer 14 with the gate insulating film 44 of the active layer 14 interposed therebetween. Do.

이하, 7a 내지 7g를 참조하여 본 발명에 따른 박막트랜지스터기판의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described with reference to 7a to 7g.

도 7a에 도시된 바와 같이, 먼저 하부기판(42) 상에 게이트 금속층이 증착공정을 통해 형성된다. 이 후, 그 게이트 금속층이 포토리소그래피공정과 식각공정에 의해 패터닝됨으로써 게이트 전극(8)이 형성된다. As shown in FIG. 7A, a gate metal layer is first formed on the lower substrate 42 through a deposition process. Thereafter, the gate metal layer is patterned by a photolithography process and an etching process to form a gate electrode 8.

이어서, 도 7b에 도시된 바와 같이, 게이트 전극(8)이 형성된 하부기판(42) 상에 SiOx, SiNx 등의 무기절연물질이 도포됨으로써 게이트 절연막(44)이 형성된다. Subsequently, as shown in FIG. 7B, an inorganic insulating material such as SiOx or SiNx is coated on the lower substrate 42 on which the gate electrode 8 is formed, thereby forming the gate insulating film 44.

이 후, 도 7c에 도시된 바와 같이, 게이트 절연막(44) 상에 순수 비정질 실리콘층, 불순물 비정질 실리콘층이 순차적으로 형성된다. 그리고, 순수 비정질 실리콘층, 불순물 비정질 실리콘층이 포토리소그래피 공정과 식각공정에 의해 패터닝됨으로써 활성층(14) 및 오믹접촉층(21)이 형성된다. Thereafter, as shown in FIG. 7C, a pure amorphous silicon layer and an impurity amorphous silicon layer are sequentially formed on the gate insulating film 44. The pure amorphous silicon layer and the impurity amorphous silicon layer are patterned by a photolithography process and an etching process to form the active layer 14 and the ohmic contact layer 21.

다음으로, 도 7d에 도시된 바와 같이, 활성층(14) 및 오믹 접촉층(21)이 형성된 게이트 절연막(44) 상에 소스/드레인 금속층이 증착되다. 이후, 증착된 소스/드레인 금속층이 포토리소그래피공정과 식각공정에 의해 패터닝됨으로써 소스/드레인 전극(12,10)이 형성된다. 그리고, 소스/드레인 전극(12,10)을 마스크로 한 식각공정을 통해 소스/드레인 전극(12,10) 사이의 오믹접촉층(21)이 제거되고, 그 하부층인 활성층(14)이 노출되어 채널이 형성된다. Next, as shown in FIG. 7D, a source / drain metal layer is deposited on the gate insulating film 44 on which the active layer 14 and the ohmic contact layer 21 are formed. Thereafter, the deposited source / drain metal layer is patterned by a photolithography process and an etching process to form source / drain electrodes 12 and 10. Then, the ohmic contact layer 21 between the source / drain electrodes 12 and 10 is removed through an etching process using the source / drain electrodes 12 and 10 as a mask, and the active layer 14, which is a lower layer thereof, is exposed. Channels are formed.

이후, 도 7e에 도시된 바와 같이, 소스/드레인 전극(12,10)이 형성된 하부기판(42) 상에 SiNx, SiOx 등과 같은 무기절연물질 또는 아크릴 수지와 같은 유기절연물질이 도포됨으로써 보호막(50)이 형성된다. Subsequently, as shown in FIG. 7E, an inorganic insulating material such as SiNx, SiOx, or an organic insulating material such as an acrylic resin is coated on the lower substrate 42 on which the source / drain electrodes 12 and 10 are formed, thereby protecting the protective film 50. ) Is formed.

다음으로, 도 7f에 도시된 바와 같이, 형성된 보호물질이 포토리소그래피공 정과 식각공정에 의해 패터닝됨으로써 소스/드레인 전극(12,10)의 일부를 노출시키는 소스콘택홀(15)과 드레인콘택홀(16)이 형성된다.Next, as shown in FIG. 7F, the formed protective material is patterned by a photolithography process and an etching process to expose portions of the source / drain electrodes 12 and 10 and the drain contact hole ( 16) is formed.

이어서, 도 7g에 도시된 바와 같이, 보호막(50) 위로 투명 도전성 물질을 증착하고, 그 증착된 투명 도전성 물질이 포토리소그래피공정과 식각공정에 의해 패터닝됨으로써 화소전극(18)과 전류제어전극(20)이 형성된다. Subsequently, as illustrated in FIG. 7G, a transparent conductive material is deposited on the passivation layer 50, and the deposited transparent conductive material is patterned by a photolithography process and an etching process, thereby forming the pixel electrode 18 and the current control electrode 20. ) Is formed.

상술한 바와 같이, 본 발명에 따른 박막 트랜지스터의 채널부와 중첩되게 형성된 전류제어전극을 데이터 라인과 연결시킴으로써 박막트랜지스터의 전류-전압 동작 특성 곡선이 종래보다 선형에 가까우므로 전류제어가 용이해진다. As described above, by connecting the current control electrode formed to overlap the channel portion of the thin film transistor according to the present invention with a data line, the current-voltage operating characteristic curve of the thin film transistor is closer to linear than in the prior art, thereby making current control easier.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여져야만 할 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

서로 교차되게 형성되는 게이트라인 및 데이터라인과;A gate line and a data line formed to cross each other; 상기 게이트라인 및 데이터라인의 교차영역에 형성되는 박막 트랜지스터와;A thin film transistor formed at an intersection of the gate line and the data line; 상기 박막트랜지스터와 접속되도록 형성되는 화소전극과;A pixel electrode formed to be connected to the thin film transistor; 상기 데이터라인과 연결되며 상기 박막트랜지스터의 채널부와 중첩되도록 형성되는 전류제어전극을 포함하는 것을 특징으로 하는 박막트랜지스터기판.And a current control electrode connected to the data line and overlapping the channel portion of the thin film transistor. 제 1항에 있어서, The method of claim 1, 상기 전류제어전극은 상기 화소전극과 동일 평면 상에 동일한 재질로 이루어지는 것을 특징으로 하는 박막트랜지스터기판.The current control electrode is a thin film transistor substrate, characterized in that made of the same material on the same plane as the pixel electrode. 제 1항에 있어서, The method of claim 1, 상기 박막트랜지스터를 덮도록 형성되는 보호막과;A protective film formed to cover the thin film transistor; 상기 보호막을 관통하여 상기 데이터 라인을 노출시키는 소스콘택홀과;A source contact hole penetrating the passivation layer to expose the data line; 상기 보호막을 관통하여 상기 박막트랜지스터의 드레인전극을 노출시키는 드레인콘택홀을 추가로 구비하는 것을 특징으로 하는 박막트랜지스터기판.And a drain contact hole penetrating through the passivation layer to expose the drain electrode of the thin film transistor. 제 1항에 있어서, The method of claim 1, 상기 박막트랜지스터의 채널부를 포함하는 활성층은 800~1000Å의 두께로 형 성되는 것을 특징으로 하는 박막트랜지스터기판.The active layer including the channel portion of the thin film transistor is a thin film transistor substrate, characterized in that formed to a thickness of 800 ~ 1000Å. 제 1항에 있어서, The method of claim 1, 상기 박막트랜지스터의 활성층의 채널부는 상기 활성층의 나머지 부분보다 얇게 형성되는 것을 특징으로 하는 박막트랜지스터기판.A thin film transistor substrate, characterized in that the channel portion of the active layer of the thin film transistor is formed thinner than the rest of the active layer. 제 5 항에 있어서, 6. The method of claim 5, 상기 활성층의 채널부는 800~1000Å의 두께로 형성되는 것을 특징으로 하는 박막트랜지스터기판.The thin film transistor substrate, characterized in that the channel portion of the active layer is formed to a thickness of 800 ~ 1000Å. 게이트라인 및 데이터라인의 교차영역에 박막트랜지스터를 형성하는 단계와;Forming a thin film transistor at an intersection of the gate line and the data line; 상기 박막트랜지스터의 드레인전극과 접속되도록 화소전극을 형성하는 단계와;Forming a pixel electrode to be connected to the drain electrode of the thin film transistor; 상기 데이터라인과 연결되며 상기 박막트랜지스터의 채널부와 중첩되도록 전류제어전극을 형성하는 단계를 포함하는 것을 특징으로 하는 박막트랜지스터기판의 제조방법.And forming a current control electrode connected to the data line and overlapping the channel portion of the thin film transistor. 제 7항에 있어서, 8. The method of claim 7, 상기 화소전극 및 전류제어전극은 동시에 형성되는 것을 특징으로 하는 박막트랜지스터기판의 제조방법.The pixel electrode and the current control electrode is a method of manufacturing a thin film transistor substrate, characterized in that formed at the same time. 제 7항에 있어서,8. The method of claim 7, 상기 박막트랜지스터를 덮도록 보호막을 형성하는 단계와;Forming a protective film to cover the thin film transistor; 상기 보호막을 관통하여 상기 데이터 라인을 노출시키도록 소스콘택홀을 형성하는 단계와;Forming a source contact hole through the passivation layer to expose the data line; 상기 보호막을 관통하여 상기 박막트랜지스터의 드레인전극을 노출시키도록 드레인콘택홀을 형성하는 단계를 추가로 구비하는 것을 특징으로 하는 박막트랜지스터기판의 제조방법.And forming a drain contact hole through the passivation layer to expose the drain electrode of the thin film transistor. 제 7항에 있어서,8. The method of claim 7, 상기 박막트랜지스터의 활성층의 채널부를 상기 활성층의 나머지 부분보다 얇게 형성하는 단계를 포함하는 것을 특징으로 하는 박막트랜지스터기판의 제조방법.And forming a channel portion of the active layer of the thin film transistor thinner than the rest of the active layer.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040022938A (en) * 2002-09-10 2004-03-18 엘지.필립스 엘시디 주식회사 Method Of Fabricating Liquid Crystal Display Device
JP2005062889A (en) 2003-08-19 2005-03-10 Samsung Electronics Co Ltd Thin film transistor display plate and method for manufacturing same
JP2007011261A (en) 2005-06-30 2007-01-18 Lg Philips Lcd Co Ltd Thin film transistor liquid crystal display panel and method of fabricating same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040022938A (en) * 2002-09-10 2004-03-18 엘지.필립스 엘시디 주식회사 Method Of Fabricating Liquid Crystal Display Device
JP2005062889A (en) 2003-08-19 2005-03-10 Samsung Electronics Co Ltd Thin film transistor display plate and method for manufacturing same
JP2007011261A (en) 2005-06-30 2007-01-18 Lg Philips Lcd Co Ltd Thin film transistor liquid crystal display panel and method of fabricating same

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