KR101296347B1 - Variable Impulse Signal Generating Apparatus and Method Using FPGA - Google Patents

Abstract

The present invention relates to an apparatus and method for generating a variable impulse signal using FPA, the apparatus for generating a variable impulse signal according to the present invention includes a trigger signal generator that generates a trigger signal when a system clock signal is input, and when the trigger signal is generated, A clock phase delay unit for delaying and outputting a system clock signal by a time set by a user, a mask signal generation unit generating a mask signal having a predetermined pulse width when the trigger signal is generated, and the system clock signal and the delayed system clock signal And a logic operation unit configured to receive the inverted signal and the mask signal and perform a logic operation to output the mask signal. According to the present invention, an FPGA using a relatively low voltage generates an impulse of 3.3V or less and may vary from several hundred picoseconds to several nanoseconds depending on a user's request. Therefore, when exploration using various impulses generated in the impulse generating device according to the present invention in the underground buried material detecting device using a GPR (Ground Penetration Radar) system, more data can be obtained, and thus more accurate buried material can be confirmed.

Description

Variable Impulse Signal Generating Apparatus and Method Using FPGA

The present invention relates to an apparatus and method for generating an impulse signal, and more particularly, to an apparatus and method for generating a variable impulse signal using a field programmable gate array (FPGA).

In general, GPR (Ground Penetration Radar) detection, ie, surface radar detection, transmits electromagnetic waves to the ground surface and measures the time when the reflected electromagnetic waves arrive at the interface where the physical properties of the medium change. Figure out the shape. For example, it can be used to obtain accurate location and depth information by acquiring 2D image cross section of underground buried in the area where roads and railroads pass and provisional section.

An impulse generator is used in the underground buried equipment detecting device using the GPR exploration system. The conventional impulse generator uses a circuit using a diode as illustrated in FIG. 1 (a) or an avalanche as illustrated in FIG. 1 (b). An impulse signal was generated using the (AVALANCHE) bias circuit.

However, the circuit according to the conventional method has a disadvantage of using a high voltage of 140V or more. In particular, unless the purpose is to explore a depth of more than 10 meters underground, the risk is too great to use a voltage equivalent to 140V. In addition, the amplitude of the impulse should be variable according to the type of underground buried material. In the above-described conventional circuit, since only a fixed impulse is generated, it is difficult to determine various underground buried materials.

Accordingly, an aspect of the present invention is to provide an apparatus and method for generating a variable impulse signal using a field programmable gate array (FPGA).

According to one or more embodiments of the present invention, a variable impulse signal generator includes a trigger signal generator that generates a trigger signal when a system clock signal is input, and uses the system clock signal when the trigger signal is generated. A clock phase delay unit for delaying and outputting a delayed time by a predetermined time, a mask signal generator for generating a mask signal having a predetermined pulse width when the trigger signal is generated, and the system clock signal, an inverted signal of the delayed system clock signal, and the And a logic operation unit which receives a mask signal and performs a logic operation to output the mask signal.

The apparatus may further include a clock phase delay controller configured to control the clock phase delay unit to delay and output the system clock signal according to a delay time set by a user.

The logic operation unit may perform an AND operation on the inverted signal of the delayed system clock signal and the system clock signal, and perform an AND operation on the result of the AND product and the mask signal.

The delay time may vary according to the user's setting.

According to one or more exemplary embodiments, a method of generating a variable impulse signal may include: generating a trigger signal when a system clock signal is input, delaying and outputting the system clock signal by a user set time when the trigger signal is generated; Generating a mask signal having a predetermined pulse width when a trigger signal is generated, and receiving and outputting the system clock signal, an inverted signal of the delayed system clock signal, and the mask signal, and performing a logic operation to output the mask signal.

The outputting may be performed by performing an AND operation on the inverted signal of the delayed system clock signal and the system clock signal, and performing an AND operation on the result of the AND and the mask signal.

A computer-readable medium according to another embodiment of the present invention records a program for causing a computer to execute any one of the above methods.

According to the present invention, an impulse signal may be generated at a relatively low voltage, and an impulse signal having an appropriate amplitude and width may be variously generated according to the type of underground buried material.

In particular, according to the present invention, an FPGA using a relatively low voltage generates an impulse of 3.3V or less, and may vary from several hundred picoseconds to several nanoseconds depending on a user's request.

Therefore, if the exploration by adjusting the width of the impulse signal generated by the impulse generating device according to the present invention in the underground buried material detecting device using the GPR (Ground Penetration Radar) system, it is possible to obtain more data, thereby enabling accurate confirmation of the buried material Do.

1 is a view showing a conventional impulse generating circuit.
FIG. 2 is a block diagram illustrating a configuration of a variable impulse signal generator using a field programmable gate array (FPGA) according to an embodiment of the present invention.
3 is a diagram illustrating a signal waveform used in the variable impulse signal generator of FIG. 2.
4 is a diagram illustrating an impulse signal generated in the apparatus for generating a variable impulse signal according to an embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

FIG. 2 is a block diagram illustrating a configuration of a variable impulse signal generator using a field programmable gate array (FPGA) according to an embodiment of the present invention.

Referring to FIG. 2, the variable impulse signal generator 100 according to the present invention may include a trigger signal generator 110, a clock phase delay unit 120, a clock phase delay controller 130, and a mask signal generator 140. And a logic operator 150. The variable impulse signal generator 100 may be implemented by using a field programmable gate array (FPGA), and may generate an impulse signal having a variable pulse width according to a user setting input.

The trigger signal generator 110 receives a system clock generated from a commonly used oscillator (not shown) and performs a function of generating a trigger signal.

When the trigger signal generated by the trigger signal generator 110 is input, the mask signal generator 140 generates and outputs a mask signal having a preset pulse width. The pulse width of the mask signal may be set longer than one half period of the system clock signal and shorter than one period of the system clock signal.

The clock phase delay unit 120 may be implemented by using a digital clock manager (DCM) existing in the FPGA, and performs a function of delaying and outputting a system clock signal by a user set time when a trigger signal is generated.

The clock phase delay control unit 130 controls the clock phase delay unit 120 to delay and output the system clock signal according to a delay time set by a user. For example, to generate an impulse signal having a pulse width of 3000 picoseconds, the user may set the clock phase delay time to 3000 picoseconds. That is, the pulse width of the desired impulse signal may be set as the clock phase delay time.

The logic calculator 150 receives a system clock signal, an inverted signal of the system clock signal delayed by the clock phase delay unit 120, and a mask signal generated by the mask signal generator 140 to perform a logic operation to generate an impulse signal. Perform the function. In more detail, the system clock signal generated by the oscillator may be input, and the system clock signal delayed by the clock phase delay unit 120 may be inverted to perform a logical product. When the result of performing the AND operation on the result of the AND operation is to perform an AND operation on the mask signal, an impulse signal having a pulse width equal to the clock phase delay time is generated.

3 is a diagram illustrating a signal waveform used in the variable impulse signal generator of FIG. 2.

Referring to FIG. 3, when the system clock signal clock1 generated by the oscillator is input, the trigger signal generator 110 generates a trigger signal.

The mask signal generation unit 140 generates a mask signal having a pulse width equal to a system clock signal period according to the trigger signal generation. The clock phase delay unit 120 delays and outputs the system clock signal by a predetermined clock phase delay time Δt from the user.

The system clock signal clock2 delayed and output from the clock phase delay unit 120 may be inverted through an inverter (not shown) and then input to the logic operation unit 150, or input to the logic operation unit 150 and then inverted. It may be.

Subsequently, if the logical operator 150 performs a logical product on the result of the logical product of the system clock signal clock1 and the inverted signal clock2 ′ of the delayed system clock signal, the impulse signal having a pulse width Δt. (I) is generated. That is, the impulse signal I is generated in the high section of the system clock signal clock1, the low section of the delay system clock signal clock2, and the high section of the mask signal. Thus, the user can vary the pulse width of the impulse signal as desired by changing the clock phase delay time [Delta] t.

4 is a diagram illustrating an impulse signal generated in the apparatus for generating a variable impulse signal according to an embodiment of the present invention.

FIG. 4A illustrates a case where the user sets the clock phase delay time Δt to 3000 picoseconds, and FIG. 4B illustrates a case where the user sets the clock phase delay time Δt to 1000 picoseconds. (c) illustrates a case where the user sets the clock phase delay time Δt to 600 picoseconds. As the set phase delay time becomes narrower, the pulse width of the generated impulse signal may be narrowed. As described above, it was confirmed that the impulse signal can be generated to have various pulse widths by using the variable impulse signal generator according to the embodiment of the present invention.

Embodiments of the present invention include a computer-readable medium having program instructions for performing various computer-implemented operations. This medium records a program for executing the variable impulse signal generation method using the field programmable gate array (FPGA) described above. The medium may include program instructions, data files, data structures, etc., alone or in combination. Examples of such media include magnetic media such as hard disks, floppy disks and magnetic tape, optical recording media such as CD and DVD, programmed instructions such as floptical disk and magneto-optical media, ROM, RAM, And a hardware device configured to store and execute the program. Or such medium may be a transmission medium, such as optical or metal lines, waveguides, etc., including a carrier wave that transmits a signal specifying a program command, data structure, or the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of right.

100: variable impulse signal generator 110: trigger signal generator
120: clock phase delay control unit 130: clock phase delay control unit
140: mask signal generation unit 150: logic operation unit

Claims (8)

In the impulse signal generating apparatus using a field programmable gate array (FPGA),
A trigger signal generator for generating a trigger signal when a system clock signal is input;
A clock phase delay unit for delaying and outputting the system clock signal by a time set by a user when the trigger signal is generated;
A mask signal generation unit generating a mask signal having a predetermined pulse width when the trigger signal is generated;
A logic calculator which receives the system clock signal, the inverted signal of the delayed system clock signal, and the mask signal, and performs a logic operation to output the logic signal;
A clock phase delay control unit controlling the clock phase delay unit to delay and output the system clock signal according to a delay time set by a user
Lt; / RTI >
The clock phase delay unit is implemented using a digital clock manager (DCM) of the FPGA,
The delay time is an impulse signal generating device that varies according to the user's setting. delete The method of claim 1,
Wherein the logical operation unit comprises:
And performing an AND operation on the inverted signal of the delayed system clock signal and the system clock signal, and performing an AND operation on the result of the AND product and the mask signal. delete In the impulse signal generation method using a field programmable gate array (FPGA),
Generating a trigger signal when a system clock signal is input;
Delaying and outputting the system clock signal by a time set by a user when the trigger signal is generated;
Generating a mask signal having a predetermined pulse width when the trigger signal is generated; and
Receiving the system clock signal, an inverted signal of the delayed system clock signal, and the mask signal, and performing a logic operation to output the mask signal
Lt; / RTI >
Delaying and outputting the system clock signal by a time set by a user is implemented using a digital clock manager (DCM) of the FPGA.
The delay time is variable according to the user's setting method of generating an impulse signal. The method of claim 5,
The outputting by performing the logical operation,
And performing an AND operation on the inverted signal of the delayed system clock signal and the system clock signal, and performing an AND operation on the result of the AND and the mask signal to output the impulse signal. delete A computer readable medium having recorded thereon a program for causing a computer to execute the method of any one of claims 5 to 6.

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