KR101291040B1 - cache line locking method of cache memory - Google Patents

Abstract

In the cache line locking method of the cache memory of the present invention, a processor processes a single instruction or two instructions to lock a cache line for locking a specific cache line, thereby reducing the instruction access time of the processor, thereby reducing the processor line during the cache line locking operation. And it is possible to reduce the power consumed in the cache, it is possible to speed up the performance when performing cache line locking.

Description

Cache line locking method of cache memory

The present invention relates to a cache line locking method of a cache memory. To lock a specific cache line of a cache memory, a processor processes one instruction or two instructions to lock a cache line, thereby reducing the instruction access time of the processor. The present invention relates to a cache line locking method of a cache memory capable of reducing power consumed by a processor and a cache during a cache line locking operation, and speeding up execution when performing cache line locking.

Generally, a cache memory is a high speed memory device that temporarily stores information between a processor having a relatively high processing speed and a main memory having a relatively low speed. Such a cache memory may speed up a computer by using a locality of reference when executing a shared program. In other words, when the computer program is executed, when observing an address in the main memory accessed by the processor, only one or two areas of the main memory can be observed intensively at any given time, which is called space density. By using this property, by placing a high speed cache memory between the main memory and the processor, and storing some areas of the main memory that are frequently used, the time required for the processor to access the main memory can be greatly reduced.

1 is a block diagram of a cache structure having a cache memory composed of four general 32-bit words.

The cache includes a cache tag storage unit 1 storing cache tag data (CTAG), a cache data storage unit 3 storing cache data, a lock bit (L), a valid bit (Valid Bit: V), and a dirty bit. It consists of a cache memory 10 and a cache controller 20 composed of a cache state storage unit 5 storing state information composed of (Dirty Bit: D).

The cache memory 10 needs to know which area of the main memory the information stored in the cache line corresponds to. The information stored in the cache line is stored through the cache tag data CTAG of the cache tag storage unit 1. It can be seen that the address of which area, the cache memory 10 stores the data read from the main memory, which is the cache data stored in the cache data storage (3).

The cache controller 20 intercepts memory requests for read and write before sending them to the memory controller, where the memory request address (MA) is a tag, an index, and an offset. The process is divided into three parts. The cache controller 20 uses the index of the memory request address MA to find the cache line of the cache memory 10, and the cache line selected by the index is stored in the cache tag data of the cache tag storage 1. CTAG) and the valid bit V of the cache state storage unit 5, the dirty bit D, and the lock bit L are used to determine whether the cache data can be used. If cache data is available, it is called a cache hit, otherwise it is called a cache miss.

If the cache misses, the cache controller 20 copies all the information of the missed cache line from the main memory to the cache memory 10 and transmits the requested data from the processor to the processor. In the case of a cache hit, the cache controller 20 The cache data stored in the cache memory 10 is transmitted to the processor.

If the valid bit (V) stored in the cache state storage unit 5 is activated, the cache data stored in the cache data storage unit 3 is valid data, and the dirty bit (D) corresponds to the cache data stored in the cache line. This bit determines whether the data stored in the main memory is matched, and the lock bit L indicates whether the cache data of the corresponding cache line can be replaced. That is, when the lock bit L is activated, the cache data stored in the corresponding cache line is exempted from replacing the cache data.

When a specific cache line is locked in this way, the size of the available cache is reduced because the area of the cache is reduced, but by locking the specific cache line, it is possible to avoid unexpected runtime problems due to miss penalty. .

2 is a flowchart of a cache line locking method of a conventional cache memory, FIG. 3 is a flowchart of a cache initialization command performing step of FIG. 2, FIG. 4 is a flowchart of a locking data write command performing step of FIG. 2, and FIG. 5 is FIG. 2 is a flowchart illustrating a lock bit update command execution step shown in FIG. 2.

As shown in FIG. 2, the cache line locking method of the conventional cache memory stores the state information of the valid bit V and the lock bit L of a specific cache line selected by an index of the memory request address MA. Status information reading step S10 for reading, and status information detecting step S20 for detecting whether both the valid bit V and the lock bit L read in the status information reading step S10 are activated; If both the valid bit V and the lock bit L are not activated in the information detecting step S20, a cache initialization instruction is performed by a processor to initialize the selected cache line and the valid bit V of the selected cache line. If all of the dirty bits (D) are enabled, the cache data of the selected cache line is stored in the main memory according to the memory request address (MA), and then the valid bit (V) is deactivated. Dirty bit (D) If the two are not activated, the cache initialization instruction execution step (S30) of deactivating the valid bit (V) and the locking data write command by the processor to perform the locking data stored in the main memory selected by the memory request address (MA) selected Locking data write command execution step (S40) for storing in the cache data storage unit 3 of the cache line and activating the valid bit (V), and the lock bit (L) of the selected cache line by performing a lock bit update command by the processor ), Performing a lock bit update command (S50).

As shown in FIG. 3, the cache initialization instruction performing step S30 includes an initialization instruction patch step S31 for patching a cache initialization instruction for accessing a processor to initialize a cache, and an initialization for decoding the patched initialization instruction by a decoder. Instruction decoding step S32, an initialization command transmission step S33 for transmitting the decoded initialization command to the cache controller 20, and a valid bit V of the cache line selected according to the initialization command transmitted to the cache controller 20. ) And the valid bit and dirty bit reading step (S34) and the valid bit and dirty bit reading step (S34) for reading the dirty bit (D) and the presence or absence of the activation of the valid bit (V) and dirty bit (D) is determined. The main memory according to the memory request address (MA) when both the valid bit and the dirty bit determination step (S35) and the valid bit and the dirty bit (D) are activated in the valid bit and dirty bit determination step (S35). Select on A copyback step (S36) for storing the cache data of the cache line and deactivating the dirty bit (D), and both the valid bit (V) and the dirty bit (D) are activated in the valid bit and dirty bit determination step (S35) Or a cache initialization step S37 for deactivating the valid bit V of the selected cache line after the copyback step S36 is completed.

As shown in FIG. 4, the performing of the locking data recording command (S40) includes a locking data recording command patch step (S41) of accessing the processor to patch the locking data recording command, and decoding the patched locking data recording command by the decoder. Locking data recording command decoding step (S42), the locking data recording command transmission step (S43) for transmitting the decoded locking data recording command to the cache controller 20, and the locking data recording command transmitted to the cache controller 20 The valid bit and the dirty bit reading step (S44) and the valid bit and dirty bit reading step (S44) for reading the valid bit (V) and the dirty bit (D) of the selected cache line according to The valid bit and the dirty bit determination step (S45) for determining whether the dirty bit (D) is activated or not, and the valid bit (V) and the dirty bit (D) are both activated in the valid bit and the dirty bit determination step (S45). A copyback step (S46) for storing the cache data of the selected cache line in the main memory according to the memory request address (MA) and deactivating the dirty bit (D), and the valid bit in the valid bit and dirty bit determination step (S45). Both V) and the dirty bit D are not activated or the locking data stored in the main memory selected by the memory request address MA after completion of the copyback step S46 is transferred to the cache data storage unit 3 of the selected cache line. Locking data recording step (S47) for storing and activating the valid bit (V).

As shown in FIG. 5, in operation S50, a lock bit update instruction patch step S51 for accessing a processor to patch a lock bit update instruction, and decoding the patched lock bit update instruction by a decoder A lock bit update command decoding step (S52), a lock bit update command sending step (S53) of transmitting the decoded lock bit update command to the cache controller 20, and a lock bit update command word transmitted to the cache controller 20 And a lock bit update step 54 for activating the lock bit L of the selected cache line.

As described above, in the cache line locking method of the conventional cache memory, in order to lock the selected cache line by activating the lock bit (L) of the selected cache line, a specific program for executing the initialization command is performed in step S30. Patching the initialization instruction from the stored memory, decoding the patched instruction by the decoder, accessing the processor to execute the instruction interpreted by the decoder, and performing this by the processor, and performing the locking data recording instruction as above. In step S40 and the step of performing a lock bit update instruction (S50), the processor must access the processor to perform the patch, decode the patched instruction, and execute the instruction, so that the processor can execute the instruction three times to lock the selected cache line. Access and patch instructions, decode instructions by processor And since the instructions are executed, the power consumed by the processor and the cache for the selected cache line locking operation is increased according to frequent processor access, and the execution speed is slowed when performing the cache line locking.

An object of the present invention is to lock a cache line by processing a single instruction or two instructions for locking a specific cache line of the cache memory, thereby reducing the instruction access time of the processor in the cache and the cache during the cache line locking operation. The present invention provides a cache line locking method of a cache memory capable of reducing power consumption and speeding up execution when performing cache line locking.

In order to achieve the above object, the cache line locking method of the cache memory of the present invention includes a cache tag storage unit storing cache tag data, a cache state storage unit storing valid bits, dirty bits, and lock bits, and cache data storing cache data. A cache line locking method of a cache memory for locking a specific cache line selected by an index of a memory request address with respect to a negatively configured cache memory, the cache line locking method comprising: a state of valid bits and lock bits of a cache line selected by an index of the memory request address Reading status information for reading information; A status information determining step of determining whether the valid bit and the lock bit read in the status information reading step are activated; And in the state information determining step, if both the valid bit and the lock bit are not activated, perform a locking instruction for locking the selected cache line by a processor, and by the cache controller 20 according to the performed locking instruction. A cache locking step of locking the selected cache line;
The cache locking step may include: a locking instruction word patching step of fetching a locking instruction word for locking the selected cache line by a processor when both the valid bit and the lock bit are not activated in the state information determining step; A locking command decoding step of decoding the locking command patched in the locking command patch step by a decoder; A locking command transmitting step of transmitting the locking command decoded in the locking command decoding step to a cache controller; A valid bit and dirty bit reading step of reading a valid bit and a dirty bit of the selected cache line according to a locking command sent to the cache controller; A valid bit and dirty bit determination step of determining whether the valid bit and the dirty bit read in the valid bit and dirty bit reading step are activated; A copyback step of storing cache data of the selected cache line in the main memory and deactivating the dirty bit when both the valid bit and the dirty bit are activated in the valid bit and dirty bit determination step; And locking data stored in the main memory selected by the memory request address after the valid bit and the dirty bit are not activated in the valid bit and dirty bit determination step or after the copyback step is completed, to the cache data storage unit of the selected cache line. And a cache line locking step of activating a valid bit and a lock bit of a cache state storage unit of the selected cache line.

delete

In the cache line locking method of the cache memory of the present invention, a processor processes a single instruction or two instructions to lock a cache line for locking a specific cache line, thereby reducing the instruction access time of the processor, thereby reducing the processor line during the cache line locking operation. And it is possible to reduce the power consumed in the cache, it is possible to speed up the performance when performing cache line locking.

1 is a block diagram of a cache structure having a cache memory composed of four general 32-bit words.
2 is a flowchart of a cache line locking method of a conventional cache memory.
3 is a flowchart of a cache initialization command execution step of FIG.
4 is a flowchart of a locking data write command execution step of FIG. 2;
5 is a flowchart of a lock bit update command execution step of FIG. 2;
6 is a flowchart of a cache line locking method of a cache memory of the present invention;
7 is a flowchart illustrating a cache line locking method of a cache memory according to another embodiment of the present invention.
8 is a flowchart illustrating a cache initialization command execution step of FIG. 7.
9 is a flowchart of the locking data recording and lock bit updating step of FIG. 7.

Hereinafter, a cache line locking method of a cache memory of the present invention will be described in detail with reference to the accompanying drawings.

6 is a flowchart of a cache line locking method of a cache memory of the present invention, FIG. 7 is a flowchart of a cache line locking method of a cache memory according to another embodiment of the present invention, and FIG. 8 is a flowchart of a step of performing a cache initialization command of FIG. 7. 9 is a flowchart of the locking data recording and lock bit updating step of FIG.

As shown in FIG. 6, the cache line locking method of the cache memory of the present invention stores the state information of the valid bit V and the lock bit L of the cache line selected by the index of the memory request address MA. Status information reading step (S100) for reading, status information determining step (S110) for determining whether activation bit (V) and lock bit (L) are activated in the status information reading step (S100), and the status information If neither the valid bit V nor the lock bit L is activated in the determining step S110, a locking command for locking the selected cache line is performed by a processor and a cache controller according to the locking command performed. A cache locking step (S190) for locking the cache line selected by 20).

In the cache locking step S190, when neither the valid bit V nor the lock bit L is activated in the status information determining step S110, a locking instruction word for patching a locking instruction for locking the cache line selected by the processor. The locking command decode step (S130), the locking command decoded in the locking command patch step (S120) by the decoder (S130) and the locking command decoded in the lock command decoding step (S130) to the cache controller A locking command transmission step (S140) to be transmitted, a valid bit and a dirty bit reading step (S150) of reading the valid bit (V) and the dirty bit (D) of the selected cache line according to the locking command transmitted to the cache controller, Valid bit and dirty bit determining step (S160) for determining whether the valid bit (V) and dirty bit (D) is activated in the valid bit and dirty bit reading step (S150) and the valid bit and dirty bit determining step ( To S160) If both the valid bit (V) and the dirty bit (D) are enabled, a copyback step (S170) for storing the cache data of the selected cache line in the main memory and deactivating the dirty bit (D), and the valid bit and the dirty bit In the determining step (S160), both the valid bit (V) and the dirty bit (D) are not activated, or after the completion of the copy back step (S170), the cache data selected in the memory selected by the memory request address (MA) selected cache line The cache line locking step (S180) stores the cache data storage unit 3 and activates the valid bit V and the lock bit L of the cache state storage unit 5 of the selected cache line.

As shown in FIG. 7, the cache line locking method of the cache memory, according to another embodiment of the present invention, includes the valid bit V and the lock bit L of the cache line selected by the index of the memory request address MA. A status information reading step (S200) for reading the status information, a status information determining step (S210) for determining whether the valid bit V and the lock bit L are activated in the status information reading step (S200); If neither the valid bit V nor the lock bit L is activated in the state information determining step S210, an initialization instruction for initializing the cache line selected by the processor is performed, and the initialization performed by the processor is performed. Cache initialization command execution step (S220) for performing the initialization of the cache line selected by the cache controller 20 according to the command, and recording the locking data of the cache line selected by the processor after the cache initialization command execution step (S220) And performing a lock command for updating the lock bit, and recording the locking data stored in the main memory by the cache controller 20 in the cache data storage unit 3 of the selected cache line according to the lock command performed by the processor. Locking data recording and locking bit updating step (S230) for activating the lock bit of the selected cache line.

As shown in FIG. 8, if both the valid bit V and the lock bit L are not activated in the state information determining step S210, the cache initialization command performing step S220 initializes the cache line selected by the processor. Initialization command patch step (S221) for patching the initialization command to make, initialization command decoding step (S222) for decoding the initialization command patched in the initialization command patch step (S221) by the decoder (S222), initialization command decoding step (S222) In the initialization command transmission step (S223) for transmitting the decoded initialization command to the cache controller, and the first validity to read the valid bit (V) and dirty bit (D) of the selected cache line according to the initialization command sent to the cache controller The first presence or absence of the bit and dirty bit read step (S224), and whether the valid bit (V) and the dirty bit (D) read in the first valid bit and dirty bit read step (S224) is activated When both the valid bit and the dirty bit determination step (S225) and the first valid bit and the dirty bit determination step (S225) are both enabled, the cache data of the cache line selected in the main memory The valid bit (V) and the dirty bit (D) are not activated in the first copyback step (S226) and the first valid bit and the dirty bit determination step (S225) for storing the data and deactivating the dirty bit (D). Or after the completion of the first copyback step S226, a cache initialization step S227 for inactivating the valid bit V of the selected cache line to initialize the selected cache line.

In addition, as illustrated in FIG. 9, the locking data recording and locking bit updating step (S230) includes a lock instruction patch step (S231) of patching a lock instruction for locking data recording and updating the lock bit by a processor, and a lock instruction patch. A lock command decoding step S232 for decoding the lock command patched in step S231 by a decoder; a lock command transmission step S233 for transmitting the lock command decoded in the lock command decoding step S232 to a cache controller; A second valid bit and dirty bit reading step (S234) for reading the valid bit (V) and the dirty bit (D) of the selected cache line according to the lock instruction transmitted to the cache controller, and reading the second valid bit and the dirty bit. A second valid bit and dirty bit determination step (S235) for determining whether the valid bit (V) and the dirty bit (D) is read in step S234, and the second valid bit and dirty bit determination step (S235) Valid bit (V) and dirty bit (D) If both are enabled, the second copyback step (S236) stores the cache data of the selected cache line in the main memory and deactivates the dirty bit (D), and the valid bit (in the second valid bit and dirty bit determination step (S235)). After both V) and the dirty bit D are not activated or after the second copyback step S236 is completed, the locking data stored in the main memory is stored in the cache data storage unit 3 of the selected cache line, and Locking data processing step (S237) for activating the valid bit (V) and the lock bit (L) stored in the cache state storage unit (5).

Operation of the cache line locking method of the cache memory of the present invention according to the above configuration is as follows.

As shown in FIG. 6, the operation of the cache line locking method of the cache memory according to the embodiment of the present invention is as follows.

The status information reading step S100 reads the status information of the valid bit V and the lock bit L of the cache line selected by the index of the memory request address MA.

 The status information determining step S110 determines whether the valid bit V and the lock bit L are activated in the status information reading step S100, and the valid bit V and the valid bit V in the status information determining step S110. If all of the lock bits (L) are active, that is, the valid bit (V) has a valid logical value, and at the same time the lock bit (L) has a valid logical value, then the selected cache line is already locked. Since there is no need to set the cache lock again, the status information reading step (S100) is performed.

If neither the valid bit V nor the lock bit L is activated in the state information determining step S110, that is, the valid bit V has an invalid logical value, and the lock bit L has an invalid logical value. Valid bit (V) has a valid logical value, lock bit (L) has an invalid logical value, valid bit (V) has an invalid logical value, and lock bit (L) has a valid logical value If the cache line is set to the cache line, the locking instruction patch step S120 may patch the locking instruction from a memory in which a plurality of instructions are stored to set the cache lock by the user, and decode the locking instruction step S130. In order to decode the locking command, which is patched in the locking command command step (S120) by the decoder, and to execute the decoded locking command, the locking command transmission step (S140) caches the locking command decoded in the locking command decoding step (S130). Send to controller, cache By the locking command transmitted by the controller, the cache controller reads the valid bit and the dirty bit (S150), determines the valid bit and the dirty bit (S160), the copy back step (S170), and the cache line locking step (S180). Will be performed.

Valid bit and dirty bit read step (S150) reads the valid bit (V) and dirty bit (D) stored in the cache state storage unit 5 of the selected cache line in accordance with the locking command transmitted to the cache controller, In the dirty bit determining step S160, the valid bit and the dirty bit reading step S150 determine whether the valid bit V and the dirty bit D are activated.

In the case of using write back cache memory, the cache data is stored in the cache data storage unit 3 of the cache memory to store the most recent data. However, the cache data is not stored in the main memory. Updates should be made to maintain consistency between cache memory and main memory. Therefore, if both the valid bit (V) and the dirty bit (D) are activated in the valid bit and dirty bit determination step (S160), the data stored in the main memory is not valid data, and thus the cache currently selected by the copy back step (S170). The cache data stored in the cache data storage unit 3 of the line is stored in the main memory selected by the memory request address MA to update the data of the main memory, and the dirty bit D is deactivated to have an invalid logical value. give.

In the valid bit and dirty bit determination step (S160), both the valid bit (V) and the dirty bit (D) are not activated, or after the copyback step (S170) is completed, the cache line locking step (S180) is a memory request address (MA). The lock data stored in the main memory selected by < RTI ID = 0.0 >) < / RTI > Activate to have all valid logic values.

As described above, in the cache line locking method of the cache memory of the present invention, when the cache lock can be set in the cache line currently selected in the state information determining step S110, the processor sets one cache lock after the state information determining step S110. It is possible to set a lock on one cache line by one processor's access by patching a locking instruction for the processor, decoding the patched locking instruction, and transmitting the decoded locking instruction to the cache controller. It is possible to reduce the access time of the processor, and in particular, to set a lock on a plurality of cache lines of the cache memory, the access time of the processor can be considerably reduced compared to the conventional one, and thus the processor and the cache during the cache line locking operation Can reduce power consumption and improve performance when performing cache line locking. Can.

The operation of the cache line locking method of the cache memory according to another embodiment of the present invention shown in FIGS. 7 to 9 is as follows.

The status information reading step S200 and the status information determining step S210 are the same as the status information reading step S100 and the status information determining step S110 of FIG. 6.

In FIG. 6, the processor sets a cache lock for a selected cache line by patching one locking instruction, whereas in FIG. 7, the processor sets a cache lock by patching two instructions.

That is, the processor may perform an initialization command patch step (S221) for patching an initialization command for initializing the selected cache line, and an initialization command decoding step (S222) for decoding the initialization command patched in the initialization command patch step (S221) by a decoder. And an initialization command transmission step (S223) for transmitting the initialization command decoded in the initialization command decoding step (S222) to the cache controller, and a valid bit (V) and a dirty bit of the cache line selected according to the initialization command sent to the cache controller. (D) whether the first valid bit and dirty bit read step (S224) and the valid bit (V) and dirty bit (D) read in the first valid bit and dirty bit read step (S224) are activated or not. If both the valid bit (V) and the dirty bit (D) are activated in the first valid bit and dirty bit determination step (S225) and the first valid bit and dirty bit determination step (S225), the main memory is stored in the main memory. The first copyback step (S226) for storing the cache data of the selected cache line and deactivating the dirty bit (D), and the valid bit (V) and the dirty bit (D) in the first valid bit and dirty bit determination step (S225). ) Is not activated or the cache initialization command performing step (S227) configured to initialize the selected cache line by deactivating the valid bit (V) of the selected cache line after the first copyback step (S226) (S220) ).

As described above, if the valid bit V and the lock bit L are not activated in the state information determining step S210, the cache initialization command execution step S220 may include an initialization command for initializing the cache line selected by the processor. And the initialization of the cache line selected by the cache controller 20 according to the initialization instruction performed by the processor, so that the processor executes the initialization instruction once, and the cache controller 20 is executed by the processor. Initialize the selected cache line according to the initialization command.

In addition, a lock instruction patch step (S231) for patching a lock instruction for recording locking data and updating the lock bit by the processor, and a lock instruction decoding step for decoding the lock instruction patched in the lock instruction patch step (S231) by a decoder. (S232), the lock command transmission step (S233) for transmitting the lock command decoded in the lock command decoding step (S232) to the cache controller, and the valid bit (V) of the cache line selected in accordance with the lock command sent to the cache controller And the second valid bit and dirty bit reading step S234 for reading the dirty bit D, and the valid bit V and the dirty bit D read in the second valid bit and dirty bit reading step S234. Main memory if both of the valid bit (V) and the dirty bit (D) are activated in the second valid bit and dirty bit determination step (S235) and the second valid bit and dirty bit determination step (S235) for determining whether to activate. Cache data of the cache line selected in The valid bit (V) and the dirty bit (D) are not activated in the second copyback step (S236) and the second valid bit and the dirty bit determination step (S235) for storing and deactivating the dirty bit (D). After completion of the second copyback step S236, the locking data stored in the main memory is stored in the cache data storage unit 3 of the selected cache line, and the valid bit V stored in the cache state storage unit 5 of the selected cache line is stored. And a locking data processing step (S237) for activating the lock bit (L), and performing a locking data recording and locking bit update step (S230).

As described above, in the cache locking data recording and lock bit updating step S230, after the cache initialization command performing step S220, a lock instruction for writing the locking data and updating the lock bit of the cache line selected by the processor is performed by the processor. The locking data stored in the main memory by the cache controller 20 is written to the cache data storage unit 3 of the selected cache line according to the received lock command, and the processor is configured to activate the lock bit of the selected cache line. After the instruction is executed once, the cache controller 20 ends the locking operation of the selected cache line according to the lock instruction performed by the processor.

Therefore, in the cache memory locking method according to another embodiment of the present invention, the step of performing the cache initialization command (S220) is the same as that of the conventional cache initialization command, but in the present invention, the locking is performed by accessing two conventional processors. The processor access time can be reduced by performing the data write command execution step and the lock bit update command execution step by one processor access by the locking data recording and lock bit update step (S240).

Claims (5)

Cache tag storage unit 1 storing cache tag data CTAG, cache state storage unit 5 storing valid bits V, dirty bits D, and lock bits L, and cache data storing cache data In the cache line locking method of the cache memory for locking the specific cache line selected by the index of the memory request address MA with respect to the cache memory constituted by the section (3),
A status information reading step (S100) of reading status information of a valid bit (V) and a lock bit (L) of a cache line selected by an index of the memory request address (MA);
A status information determination step (S110) of determining whether the valid bit (V) and the lock bit (L) are activated in the status information reading step (S100); And
If neither the valid bit V nor the lock bit L is activated in the state information determining step S110, a locking instruction for locking the selected cache line is performed by a processor and according to the performed locking instruction It has a cache locking step (S190) for locking the cache line selected by the cache controller 20,
In the cache locking step S190, when neither the valid bit V nor the lock bit L is activated in the state information determining step S110, a locking instruction word for locking the selected cache line by a processor Locking command patch step (S120) for patching, Locking command decoding step (S130) to decode the locking command patched in the locking command patch step (S120) by the decoder (S130), Decoding in the locking command decoding step (S130) A locking instruction transmission step (S140) for transmitting the locked locking instruction to the cache controller, a valid bit for reading the valid bit (V) and the dirty bit (D) of the selected cache line according to the locking instruction transmitted to the cache controller; Valid bit and dirty bit determination stage for determining whether to activate the valid bit (V) and the dirty bit (D) read in the dirty bit read step (S150) and the valid bit and dirty bit read step (S150) If the valid bit (V) and the dirty bit (D) are activated in the system (S160) and the valid bit and the dirty bit determination step (S160), the cache data of the selected cache line is stored in a main memory and the dirty bit ( D) Deactivation of the copy back step (S170) and the valid bit and the dirty bit determination step (S160), both the valid bit (V) and the dirty bit (D) is not activated or the copy back step (S170) is completed Then, the locking data stored in the main memory selected by the memory request address MA is stored in the cache data storage unit 3 of the selected cache line, and the valid bit V of the cache state storage unit 5 of the selected cache line is stored. And a cache line locking step (S180) for activating the lock bit (L).
delete Cache tag storage unit 1 storing cache tag data CTAG, cache state storage unit 5 storing valid bits V, dirty bits D, and lock bits L, and cache data storing cache data In the cache line locking method of the cache memory for locking the specific cache line selected by the index of the memory request address MA with respect to the cache memory constituted by the section (3),
A status information reading step (S200) of reading status information of a valid bit (V) and a lock bit (L) of a cache line selected by an index of the memory request address (MA);
A state information determination step (S210) of determining whether the valid bit (V) and the lock bit (L) are activated in the state information reading step (S200);
If neither the valid bit V nor the lock bit L is activated in the state information determining step S210, an initialization instruction for initializing the cache line selected by the processor is performed, and the initialization performed by the processor is performed. Performing a cache initialization command (S220) for performing initialization on the cache line selected by the cache controller 20 according to the command; And
After performing the cache initialization command (S220), a lock command for recording and locking the lock data of the cache line selected by the processor is executed, and the main memory is executed by the cache controller 20 according to the lock command performed by the processor. And a locking data recording and lock bit updating step (S230) for recording the locking data stored in the cache data storage unit 3 of the selected cache line and activating the lock bit of the selected cache line. Cache line locking method.
The method of claim 3, wherein performing the cache initialization command (S220),
If neither the valid bit V nor the lock bit L is activated in the state information determining step S210, an initialization command patch step of patching an initialization command for initializing the selected cache line by a processor (S221). );
An initialization command decoding step (S222) of decoding an initialization command patched in the initialization command patch step (S221) by a decoder;
An initialization command transmission step (S223) of transmitting the initialization command decoded in the initialization command decoding step (S222) to a cache controller;
A first valid bit and dirty bit reading step (S224) of reading a valid bit (V) and a dirty bit (D) of the selected cache line according to an initialization command sent to the cache controller;
A first valid bit and dirty bit determination step (S225) for determining whether the valid bit (V) and the dirty bit (D) read in the first valid bit and dirty bit reading step (S224) are activated;
If both the valid bit V and the dirty bit D are activated in the first valid bit and the dirty bit determination step S225, cache data of the selected cache line is stored in a main memory and the dirty bit D is deactivated. To make a first copyback step (S226); And
In the first valid bit and dirty bit determination step (S225), both the valid bit (V) and the dirty bit (D) are not activated, or after the first copyback step (S226) is completed, the valid bit of the selected cache line ( And a cache initialization step (S227) for deactivating V) to initialize the selected cache line.
The method of claim 3, wherein the locking data recording and updating lock bit step (S230),
A lock instruction patch step (S231) of patching a lock instruction for recording locking data and updating the lock bit by a processor;
A lock command decoding step (S232) of decoding the lock command patched in the lock command patch step (S231) by a decoder;
A lock command transmission step (S233) of transmitting the lock command decoded in the lock command decoding step (S232) to a cache controller;
A second valid bit and dirty bit reading step (S234) of reading a valid bit (V) and a dirty bit (D) of the selected cache line according to the lock command transmitted to the cache controller;
A second valid bit and dirty bit determination step (S235) of determining whether the valid bit (V) and the dirty bit (D) are read in the second valid bit and dirty bit reading step (S234);
If both the valid bit (V) and the dirty bit (D) are activated in the second valid bit and dirty bit determination step (S235), cache data of the selected cache line is stored in main memory and the dirty bit (D) is deactivated. A second copyback step (S236); And
In the second valid bit and dirty bit determination step (S235), both the valid bit (V) and the dirty bit (D) are not activated, or after the second copyback step (S236) is completed, the locking data stored in the main memory is read. Locking data processing step (S237) for storing in the cache data storage unit 3 of the selected cache line, and activates the valid bit (V) and lock bit (L) stored in the cache state storage unit 5 of the selected cache line Cache line locking method of the cache memory, characterized in that it comprises a.

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