KR101277052B1 - Photo-induced flash memory element and manufacturing method thereof and photodetector - Google Patents

Abstract

A method for manufacturing a photoorganic flash memory device of the present invention includes forming an insulating layer on a substrate having a channel region; Forming a gate on the insulating layer; Etching the insulating layer and the gate to have a length of the channel region;
Forming a source and a drain in the substrate spaced apart from each other with the channel region interposed therebetween; Removing a portion of the insulating layer to form a nanogap in a horizontal direction; Forming a tunneling insulation layer and a control insulation layer in the nanogap; And inserting a photoactive material into a portion where the tunneling insulating layer and the control insulating layer are not formed in the nanogap.

Description

Photo-induced flash memory element and manufacturing method, etc. and photodetector

The present invention relates to a photoorganic flash memory device, a manufacturing method thereof, and a photo detector.

Conventional flash memory devices leading the nonvolatile memory market define data states of '0' and '1' by injecting or tunneling electrons from a channel into a floating gate, which is a charge store. Chung-Jin Kim, Sung-Jin Choi, Sungho Kim, Jin-Woo Han, Hoyeon Kim, Seunghyup Yoo, and Yang-Kyu Choi *, "Photoinduced Memory with Hybrid Integration of an Organic Fullerene Derivative and an Inorganic Nanogap-Embedded Field-Effect Transistor for Low-Voltage Operation ", Adv. Mater. As described in 2011, XX, 1-6, high driving voltages (write voltages and erase voltages) are required to implement the operation of such memory devices, and these high driving voltages require a lot of power consumption and a tunneling insulating layer. Degradation

According to such necessity, technology development for lowering the driving voltage is being made, but the power supply voltage provided to the chip itself is continuously lowered according to the development of semiconductor technology, while the scaling of the driving voltage of the memory device is hardly achieved. to be.

In addition, the thickness of the tunneling insulating layer must be reduced in order to lower the driving voltage, but this has a problem of reducing data retention time, which is one of important values of the nonvolatile memory.

Chung-Jin Kim, Sung-Jin Choi, Sungho Kim, Jin-Woo Han, Hoyeon Kim, Seunghyup Yoo, and Yang-Kyu Choi *, "Photoinduced Memory with Hybrid Integration of an Organic Fullerene Derivative and an Inorganic Nanogap-Embedded Field-Effect Transistor for Low-Voltage Operation ", Adv. Mater. 2011, XX, 1-6 』

The present invention provides a photo-organic flash memory device capable of high performance memory operation at a lower write voltage and erase voltage than a conventional flash memory device, and a manufacturing method thereof, and a photo detector for detecting light applied to the photo-organic flash memory device. For the purpose of

One aspect of the invention, forming an insulating layer on a substrate having a channel region; forming a gate on the insulating layer; Etching the insulating layer and the gate to have a length of the channel region; forming a source and a drain in the substrate spaced apart from each other with the channel region therebetween; Removing a portion of the insulating layer to form a nanogap in a horizontal direction; Forming a tunneling insulation layer and a control insulation layer in the nanogap; And inserting a photoactive material into a portion where the tunneling insulating layer and the control insulating layer are not formed in the nanogap.

An embodiment of the present invention provides a method of manufacturing a photoorganic flash memory device, wherein a portion not removed from the insulating layer supports the gate and is a silicon oxide layer.

According to another embodiment of the present invention, the tunneling insulating layer and the control insulating layer are respectively provided on the lower portion, the upper portion in the nanogap, provides a method for manufacturing an organic light-flash memory device.

According to another embodiment of the present invention, the channel region is formed of any one of silicon, germanium, silicon germanium, tensile silicon, tensile silicon germanium, or silicon carbide.

Yet another embodiment of the present invention provides a method of fabricating an optical organic flash memory device, wherein the tunneling insulating layer and the control insulating layer are silicon oxide layers or high dielectric layers.

In another embodiment of the present invention, the photoactive material is fullerene (Fullerene), Phenyl-C61-Butyric Acid Methyl Ester (PCBM), P3HT (poly (3-hexylthiophene)) or any one of their derivatives, mineral organic A flash memory device manufacturing method is provided.

Another aspect of the invention, forming an insulating layer on the substrate; Forming a thin film on the insulating layer; Forming a hard mask with a nitride film on the thin film, and forming a fin-shaped channel region from the thin film and the hard mask; sequentially forming a sacrificial insulating layer and a gate on a side of the fin-shaped channel region, and forming the hard mask Flattening using the mask as an etch stop layer; Etching the insulating layer and the gate to have a length of the channel region; Forming a source and a drain in the thin film spaced apart from each other with the channel region interposed therebetween; Etching a sacrificial insulating layer between the gate and the fin-shaped channel region to form a vertical nanogap; Forming a tunneling insulation layer and a control insulation layer in the nanogap; And inserting a photoactive material between the tunneling insulating layer and the control insulating layer in the nanogap.

In one embodiment of the present invention, the channel region is in contact with the insulating layer in a direction facing the surface of the substrate, and provides a method for manufacturing an organic light-flash memory device, forming a nanogap between the gate. .

According to another embodiment of the present invention, the tunneling insulating layer and the control insulating layer are each provided on the channel region side and the gate side in the nanogap, respectively.

According to another embodiment of the present invention, the channel region is formed of any one of silicon, germanium, silicon germanium, tensile silicon, tensile silicon germanium, or silicon carbide.

Yet another embodiment of the present invention provides a method of fabricating an optical organic flash memory device, wherein the tunneling insulating layer and the control insulating layer are silicon oxide layers or high dielectric layers.

In another embodiment of the present invention, the photoactive material is fullerene (Fullerene), Phenyl-C61-Butyric Acid Methyl Ester (PCBM), P3HT (poly (3-hexylthiophene)) or any one of their derivatives, mineral organic A flash memory device manufacturing method is provided.

Another aspect of the invention, the insulating layer formed on the substrate having a channel region; A gate formed on the insulating layer; And a source and a drain formed in the substrate to be spaced apart from each other with the channel region interposed therebetween, wherein the insulating layer is formed under a portion of the gate, and a horizontal direction between the gate and the insulating layer and the substrate. A nanogap is formed in the tunneling insulating layer and the control insulating layer formed in the nanogap; And a photoactive material interposed between the tunneling insulating layer and the control insulating layer in the nanogap.

An embodiment of the present invention provides a photoorganic flash memory device in which a positive threshold voltage change or a write operation is implemented when a negative gate voltage and an optical signal are simultaneously applied to a gate of the photoorganic flash memory device. .

Another embodiment of the present invention provides a photoorganic flash memory device in which a negative threshold voltage change or erase operation is implemented when a positive gate voltage and an optical signal are simultaneously applied to a gate of the photoorganic flash memory device. .

According to another embodiment of the present invention, when a source voltage, a gate voltage, and a drain voltage are simultaneously applied to the photoorganic flash memory device, a 2-bit photoorganic memory operation is performed on each of the source side and the drain side. The present invention provides a photoorganic flash memory device.

Another embodiment of the present invention provides a photo detector for detecting light by using a change in a threshold voltage through a combination of an optical signal and an electrical signal applied to the gate of the photoorganic flash memory device described above.

Another aspect of the invention, the insulating layer formed on the substrate; And a thin film formed on the insulating layer, wherein the thin film is formed with a source and a drain spaced apart from each other with a pin-shaped channel region interposed therebetween, and the gate having the sacrificial insulating layer interposed therebetween. A tunneling insulating layer and a control insulating layer spaced apart from the side of the channel region, wherein a vertical nanogap is formed between the channel region and the gate and formed inside the nanogap; And a photoactive material interposed between the tunneling insulating layer and the control insulating layer.

An embodiment of the present invention provides a photoorganic flash memory device in which a positive threshold voltage change or a write operation is implemented when a negative gate voltage and an optical signal are simultaneously applied to a gate of the photoorganic flash memory device. .

Another embodiment of the present invention provides a photoorganic flash memory device in which a negative threshold voltage change or erase operation is implemented when a positive gate voltage and an optical signal are simultaneously applied to a gate of the photoorganic flash memory device. .

According to another embodiment of the present invention, when the source voltage, the gate voltage, and the drain voltage of the photoorganic flash memory device are applied simultaneously with the optical signal, 2-bit photoorganic memory operation is implemented on each of the source side and the drain side. The present invention provides an optical organic flash memory device.

According to another embodiment of the present invention, when the source voltage, the gate voltage, and the drain voltage of the photoorganic flash memory device are applied simultaneously with the optical signal, each of the source side and the drain side of one side and the other side of the channel is 4 Provided is an organic light flash memory device in which bits of organic light memory operation are implemented.

Another embodiment of the present invention provides a photo detector for detecting light by using a change in a threshold voltage through a combination of an optical signal and an electrical signal applied to the gate of the photoorganic flash memory device described above.

According to the present invention, since the optical organic flash memory device can perform a high performance memory operation at a lower write voltage and erase voltage than a conventional flash memory device, the size of the memory chip can be reduced, and power consumption is not generated. It does not degrade the tunneling insulating layer and does not reduce the data retention time.

In addition, according to the present invention, it is possible to easily manufacture a photo-organic flash memory device using a complementary metal-oxide-semiconductor (CMOS) technology.

1 is a cross-sectional view of an optical organic flash memory device having a planar nanogap according to a first embodiment of the present invention.
2A through 2E are cross-sectional views illustrating a method of manufacturing the photoorganic flash memory device of FIG. 1.
3A to 3G are graphs comparing a driving method of a conventional flash memory and an optical organic flash memory device of the present invention.
4 is a cross-sectional view of an optical organic flash memory device having a three-dimensional structure with a vertical nanogap according to a second embodiment of the present invention.
5A through 5H are cross-sectional views illustrating a method of manufacturing the photoorganic flash memory device of FIG. 4.
FIG. 6 is a plan view illustrating multi-bit implementation in a 3D structured organic-organic flash memory device having a vertical nanogap according to a second embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The shape and the size of the elements in the drawings may be exaggerated for clarity and the same elements are denoted by the same reference numerals in the drawings.

In the embodiment of the present invention, a description will be given of the N-type field effect transistor, and the same may be applied to the P-type field effect transistor. In the present invention, a description will be made mainly of an optical organic flash memory device having a planar structure, and the same principle can be applied to a three-dimensional structure.

1 is a cross-sectional view of an optical organic flash memory device having a planar nanogap according to a first embodiment of the present invention. As shown in FIG. 1, the photoorganic flash memory device having the planar nanogap according to the first embodiment includes an insulating layer 110 and an insulating layer 110 formed on a substrate 100 having a channel region. The gate 120 and the source 100 include a source 130 and a drain 140 formed to be spaced apart from each other with a channel region therebetween. The insulating layer 110 is formed under a portion of the gate 120, and a horizontal nanogap (see 150 in FIG. 2D) is formed between the gate 120, the insulating layer 110, and the substrate 100. . In addition, the photo-organic flash memory device having a planar nanogap includes a tunneling insulating layer 160 and a control insulating layer 170 formed in the nanogap, and a tunneling insulating layer 160 and a control insulating layer 170 within the nanogap. It may further include a photoactive material 180 inserted in.

2A through 2E are cross-sectional views illustrating a method of manufacturing the photoorganic flash memory device of FIG. 1. 2A to 2E, a method of manufacturing the optical organic flash memory device having the planar nanogap according to the first embodiment will be described.

First, as shown in FIG. 2A, an insulating layer 110 is formed on a substrate having a channel region (eg, a single crystal semiconductor substrate 100). In the first embodiment of the present invention, the substrate 100 will be described for convenience P-type silicon substrate, which means a general material of silicon, germanium, silicon germanium, tensile silicon, tensile silicon germanium, or silicon carbide substrate It can be formed of either.

Thereafter, as shown in FIG. 2A, the gate 120 is formed on the insulating layer 110. The gate 120 may be N + polysilicon or P + polysilicon in the case of an N-type field effect transistor.

After that, as shown in FIG. 2B, the insulating layer 110 and the gate 120 are etched to have a length of the channel region.

Subsequently, as shown in FIG. 2B, a source 130 and a drain 140 spaced apart from each other with the channel region interposed therebetween are formed in the substrate 100. When the source 130 and the drain 140 are formed, they are spaced apart by the length of the channel in the substrate 100 through a process such as diffusion or ion implantation and subsequent heat treatment.

Thereafter, as shown in FIG. 2C, a portion of the insulating layer 110 is removed to form a horizontal nanogap 150 (planar nanogap). When forming the nanogap 150 in the horizontal direction, only the insulating layer 110 under the gate 120 is selectively etched through wet etching. Here, the nanogap 150 has a length of several hundred nm from the edge of the gate 120, respectively. The non-etched portion of the insulating layer 110 structurally supports the gate 120 and is a silicon oxide layer (SiO 2).

Thereafter, as shown in FIG. 2D, the tunneling insulating layer 160 and the control insulating layer 170 are formed in the nanogap 150. The tunneling insulating layer 160 and the control insulating layer 170 may be a silicon oxide layer or a high dielectric layer formed within a range that does not fill both the nanogap 150. The tunneling insulating layer 160 electrically insulates the substrate 100 and the photoactive material 180, and the control insulating layer 170 electrically insulates the gate 120 and the photoactive material 180.

Thereafter, as shown in FIG. 2E, a photoactive material 180 is inserted between the tunneling insulating layer 160 and the control insulating layer 170 in the nanogap 150. When inserting the photoactive material 180 into the nanogap 150, a solution process or evaporation process is used. In order to fill the inside of the nanogap 150 without a void, it is preferable to use a solution process. Since the structure of the nanogap 150 fills the photoactive material 180 after all thermal processes based on the CMOS process, the nanogap 150 has an advantage of making organic materials and high dielectric constant vulnerable to thermal processes compatible without limitation in the CMOS process.

3A to 3G are graphs comparing a driving method of a conventional flash memory and an optical organic flash memory device of the present invention.

First, as shown in FIG. 3A, in the case of a conventional flash memory in which the floating gate 190 is inserted between the tunneling insulating layer 160 and the control insulating layer 170, a high amount of gate voltage is required for a write operation. Is applied to the gate. At this time, the band diagram seen in the direction A-A 'in Figure 3a is as shown in Figure 3b.

As shown in FIG. 3B, electrons tunneling the thinned tunneling insulation layer 160 by a common tunneling scheme called Fowler-Nordheim Tunenling (FNT) from the channel of the substrate 100 are electrically insulated. Stored in a floating gate 190, which causes a positive threshold voltage (VT) change through the channel potential change. In the erase operation, when a high negative gate voltage is applied to the gate 120, electrons stored in the floating gate 190 are emitted to lower the threshold voltage.

In the case of the optical organic flash memory device according to the first embodiment of the present invention, unlike the conventional method of driving the flash memory device, only a negative gate voltage lower than the absolute value is required for the write operation together with the optical signal. For the erase operation, only a lower positive gate voltage is needed in absolute terms with the optical signal. The driving principle of the optical organic flash memory device by the combination of the optical signal and the electrical signal is as follows.

As shown in FIG. 3C, the photoactive material is a direct bandgap material, and an electron major bound by coulomb-force by excitation when light having energy above the bandgap is irradiated. Electron-hole pairs or excitons occur. These electron pairs or excitons are dissociated when an electric field above binding energy is applied, and free electrons and free holes are released when an electric field is applied to the photoactive material. Move according to the tilt of the inclined band.

In the case of the photo-organic flash memory device according to the first embodiment of the present invention, the electron-electron pair or exciton generated by the optical signal as in (a) is dissociated and moved by the negative gate voltage as in (b). In the case of free holes, the free insulating layer accumulates on the surface between the control insulating layer 170 and the photoactive material 180, and in the case of free electrons, the tunneling insulating layer 160 and the free electrons. The surface is stacked between the photoactive materials 180. At this time, since the free electrons and the free holes are simultaneously formed in pairs, the absolute value of the charge amount is the same.

The free electrons and free holes distributed by such a negative gate voltage have different electric potentials on the channel because the distance from the channel is different based on the positions of the free electrons and the free holes. Even though the charge amount of each of the free electrons and the free holes is the same, since the free electrons are located closer to the channel than the free holes and the potential on the channel predominates, the free electrons become the same state in which only electrons exist. This results in a positive threshold voltage change, as in conventional flash memory devices.

As shown in FIG. 3D, in the case of the erasing operation, as in (a), the electron-pair pair or exciton generated by the optical signal is dissociated and moved by the positive gate voltage applied to the gate, and the positive gate voltage Due to the write operation using the negative gate voltage, the free electrons and the free holes move in opposite directions according to the band shape in which the slope is reversed. At this time, the newly formed free electrons and free holes meet the free electrons and free holes that were previously located on the surface through a write operation as in (b), and the newly formed free holes are formed of the tunneling insulating layer 160 and the photoactive material ( The free electrons distributed on the surface between the surfaces 190 and the newly formed free electrons recombine with the free holes distributed on the surface between the control insulating layer 170 and the photoactive material 190, respectively. This results in a situation where the free holes become more dominant with respect to the channel, and change the positive threshold voltage changed by the write operation in the negative direction.

3E illustrates the operation of the photoorganic flash memory device manufactured according to the first embodiment of the present invention. Fresh means initial state and L and W mean channel length and channel width, respectively.

The change in the drain current ID according to the gate voltage VG shows that the memory device, which was not operated only by the optical signal, is operated by the combination of the optical signal and the gate voltage, and even if there is an optical signal, It does not operate at the gate voltage. Light-ON and Light-OFF indicate the case where there is an optical signal and the case where there is no optical signal, respectively.

3F shows a write operation when an optical signal of 100mW / cm 2 intensity is applied. FIG. 3F illustrates the change of the threshold voltage VT according to the write time tPGM. In FIG. 3F, the VPGM is a write voltage and the threshold voltage increases as the write time tPGM increases.

3G illustrates an erase operation when an optical signal of 100 mW / cm 2 intensity is applied. FIG. 3G illustrates a change in the threshold voltage VT according to the erase time tERS. In FIG. 3G, the VPGM is an erase voltage and the threshold voltage decreases as the erase time tERS increases.

On the other hand, the optical organic flash memory device according to the first embodiment of the present invention can be applied to a photodetector including a light receiver due to a feature driven by an optical signal. In the case of a silicon-based CMOS image sensor (CIS) composed of a transistor and a light receiving unit, since a silicon light receiving unit having a size of several μm is required to receive sufficient light, there is a limit in reducing the size of the unit sensor.

When the photoorganic flash memory device according to the first embodiment of the present invention is used as a photodetector, the light receiving part structure including the photoactive material is inserted in the memory device capable of acting as a transistor, thereby having an advantage of scaling.

4 is a cross-sectional view of an optical organic flash memory device having a three-dimensional structure with a vertical nanogap according to a second embodiment of the present invention. As shown in FIG. 4, the photo-organic flash memory device having a three-dimensional structure having a vertical nanogap according to the second embodiment includes an insulating layer 200 and an insulating layer 200 formed on the substrate 100. It includes a thin film 210 formed on. After the thin film 210 and the hard mask 220 are formed in a fin shape, the source 130 and the drain 140 spaced apart from each other with a channel region having a fin shape therebetween are formed. The gate 120 is spaced apart from the side of the channel region 230 with the sacrificial insulating layer 240 interposed therebetween, so that the nanogap in the vertical direction between the channel region 230 and the gate 120 (see 150 in FIG. 5F). Is formed. The photo-organic flash memory device having a three-dimensional structure having a vertical nanogap includes a tunneling insulating layer 160 and a control insulating layer 170, a tunneling insulating layer 160, and a control insulating layer 170 formed inside the nanogap. It further comprises a photoactive material 180 inserted in.

5A through 5G are cross-sectional views illustrating a method of manufacturing the photoorganic flash memory device of FIG. 4. 5A to 5G, a method of manufacturing a photoorganic flash memory device having a vertical nanogap according to a second embodiment will be described.

As shown in FIG. 5A, an insulating layer 200 is formed on a substrate (eg, a semiconductor substrate 100). In relation to the substrate 100, an insulating layer embedded silicon (SOI) substrate in which the insulating layer 200 is embedded in the substrate 100 may be used. Here, the insulating layer 200 refers to a layer made of general silicon oxide (SiO 2).

Thereafter, as shown in FIG. 5A, a thin film 210 is formed on the insulating layer 200.

After that, as shown in FIG. 5B, a hard mask 220 is formed of a nitride film on the thin film 210, and fins are formed from the thin film 210 and the hard mask 220 through a developing technique using a photosensitive film. A fin region (see 230 of FIG. 6) is formed.

Subsequently, as illustrated in FIG. 5C, the sacrificial insulating layer 240 and the gate 120 are sequentially formed on side surfaces of the fin-shaped channel region, and the hard mask 220 is used as an etch stop layer. Leveling is performed through a chemical mechanical polishing (CMP) process. The sacrificial insulating layer 240 and the gate 120 are formed not only on the side of the channel region but also on the upper portion of the channel region until the CMP, and remove the sacrificial insulating layer and the gate covered on the upper portion of the channel region through the CMP. . The sacrificial insulating layer 240 is formed of silicon oxide (SiO 2) capable of selective etching. The gate 120 may be N + polysilicon or P + polysilicon in the case of an N-type field effect transistor.

After that, as shown in FIG. 5D, the insulating layer 240 and the gate 120 are etched to have a length of the channel region. C-C 'of FIG. 5D is the same direction as B-B' of FIG. 5C.

Thereafter, as shown in FIG. 5E, a source (see 130 in FIG. 6) and a drain (see 140 in FIG. 6) spaced apart from each other with the channel region interposed therebetween are formed in the thin film 210. FIG. 5E is a cross-sectional view taken along the direction BB ′ in FIG. 5D. When the source and the drain are formed, processes such as diffusion or ion implantation and subsequent heat treatment may be performed by separating the channels in the thin film 210 by the length of the channel. Form through. As illustrated in FIG. 6 to be described later, the source and the drain are formed at both sides of the channel region under the hard mask 220, respectively.

Subsequently, as shown in FIG. 5F, the sacrificial insulating layer 240 between the gate 120 and the fin-shaped channel region is etched through wet etching to form the nanogap 150 in the vertical direction. Form.

Thereafter, as shown in FIG. 5G, a tunneling insulating layer 160 and a control insulating layer 170 are formed in the nanogap 150. The tunneling insulating layer 160 and the control insulating layer 170 may be a silicon oxide layer or a high dielectric layer formed within a range that does not fill both the nanogap 150. The tunneling insulating layer 160 electrically insulates the channel region 230 and the photoactive material 180, and the control insulating layer 170 electrically insulates the gate 120 and the photoactive material 180.

Thereafter, as shown in FIG. 5H, a photoactive material is inserted between the tunneling insulating layer 160 and the control insulating layer 170 in the nanogap 150. When inserting the photoactive material 180 into the nanogap 150, a solution process or evaporation process is used. The vertical nanogap is a structure in which the photoactive material 180 is directly exposed to the incident direction of light, and thus the gate material may absorb more light than the planar nanogap that interferes with the absorption of light, thereby lowering the driving voltage. The advantage of the three-dimensional structure that the gate surrounds the channel is strong against short-channel effects.

FIG. 6 is a plan view illustrating multi-bit implementation in a 3D structured organic-organic flash memory device having a vertical nanogap according to a second embodiment of the present invention.

As shown in FIG. 6, the three-dimensional photoorganic flash memory device has a multi-bit, i.e., local charging at multiple locations without interference between data due to its structural advantages. It is possible to do

First, since the gate 120 is separated through the CMP process, two bits without the interference of the charges in the left and right channel regions in the gate direction can be realized, and in the case of a photoactive material composed of molecules having a size of several nm, Due to the discrete feature, two bits are possible on each of the source 130 side and the drain 140 side in the longitudinal direction of the channel region, thereby enabling four bits per cell.

In order to store charge locally on the source 130 side or the drain 140 side, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory uses the Channel Hot-Electron Injection (CHEI) method. An unbalanced electric field must be applied to each of the source 130 and the drain 140 as if the charge could be stored locally.

Specifically, in a state where light is irradiated, the gate 120 is applied with a voltage equal to or lower than the threshold voltage Vcrit, in which the photoorganic memory effect does not occur. In this case, in the case of the drain 140, when a positive gate voltage is applied to the drain 140, similar to a hot carrier injection method, a write operation occurs on the side of the drain 140 due to an increased electric field, whereas in the case of the source 130. When the ground voltage (0V) is applied to the write operation, the write operation does not occur at the source 130 side.

In the case of a photo-organic flash memory device having a three-dimensional structure, the gate structure including the channel and the nanogap described in FIG. 4 is not limited to a double gate structure in which sidewalls exist. It can be applied to a triple gate structure covered with a gate structure, a nanowire-shaped pillar structure in which the front surface of the channel region is covered with the gate structure, and a vertical pillar structure in which the channel region is formed upright in a vertical direction by contacting the substrate. have.

The present invention is not limited by the above-described embodiment and the accompanying drawings. It is intended that the scope of the invention be defined by the appended claims, and that various forms of substitution, modification, and alteration are possible without departing from the spirit of the invention as set forth in the claims. Will be self-explanatory.

100: substrate
110: insulating layer
120: gate
130: source
140: drain
150: nanogap
160: tunneling insulation layer
170: control insulation layer
180: photoactive material
190: floating gate
200: insulating layer
210: thin film
240: sacrificial insulating layer

Claims (16)

Forming an insulating layer on the substrate having a channel region;
Forming a gate on the insulating layer;
Etching the insulating layer and the gate to have a length of the channel region;
Forming a source and a drain in the substrate spaced apart from each other with the channel region interposed therebetween;
Removing a portion of the insulating layer to form a nanogap in a horizontal direction;
Forming a tunneling insulation layer and a control insulation layer in the nanogap; And
Inserting a photoactive material into a portion where the tunneling insulating layer and the control insulating layer are not formed in the nanogap;
Including a photo-organic flash memory device manufacturing method. The method of claim 1,
The portion not removed from the insulating layer supports the gate and is a silicon oxide layer. The method of claim 1,
And the tunneling insulating layer and the control insulating layer are respectively formed on the bottom and top of the nanogap, respectively. Forming an insulating layer on the substrate;
Forming a thin film on the insulating layer;
Forming a hard mask on the thin film using a nitride film and forming a fin-shaped channel region from the thin film and the hard mask;
Sequentially forming a sacrificial insulating layer and a gate on side surfaces of the fin-type channel region and flattening the hard mask using an etch stop layer;
Etching the insulating layer and the gate to have a length of the channel region
Forming a source and a drain in the thin film spaced apart from each other with the channel region interposed therebetween;
Etching a sacrificial insulating layer between the gate and the fin-shaped channel region to form a vertical nanogap;
Forming a tunneling insulation layer and a control insulation layer in the nanogap; And
Inserting a photoactive material between the tunneling insulation layer and the control insulation layer within the nanogap;
Including a photo-organic flash memory device manufacturing method. 5. The method of claim 4,
And the channel region is in contact with the insulating layer in a direction facing the surface of the substrate, and forms a nanogap between the gate and the gate. 5. The method of claim 4,
And the tunneling insulating layer and the control insulating layer are respectively formed on the channel region side and the gate side within the nanogap, respectively. The method according to claim 1 or 4,
And the channel region is formed of any one of silicon, germanium, silicon germanium, tensile silicon, tensile silicon germanium, or silicon carbide. The method according to claim 1 or 4,
And the tunneling insulating layer and the control insulating layer are silicon oxide layers or high dielectric layers. The method according to claim 1 or 4,
The photoactive material is any one of fullerene (Fullerene), Phenyl-C61-Butyric Acid Methyl Ester (PCBM), poly (3-hexylthiophene) (P3HT) or derivatives thereof. An insulating layer formed on the substrate having a channel region;
A gate formed on the insulating layer; And
A source and a drain formed in the substrate and spaced apart from each other with the channel region therebetween;
/ RTI >
The insulating layer is formed under a portion of the gate, a horizontal nanogap is formed between the gate, the insulating layer and the substrate,
A tunneling insulating layer and a control insulating layer formed in the nanogap; And
A photoactive material interposed between the tunneling insulation layer and the control insulation layer in the nanogap;
≪ / RTI >
Mineral organic flash memory device. An insulating layer formed on the substrate; And
A thin film formed on the insulating layer;
/ RTI >
The thin film is formed with a source and drain spaced apart from each other with a pin-shaped channel region and the channel region therebetween,
A gate is spaced apart from the side of the channel region with a sacrificial insulating layer interposed therebetween, so that a vertical nanogap is formed between the channel region and the gate.
A tunneling insulating layer and a control insulating layer formed inside the nanogap; And
A photoactive material interposed between the tunneling insulation layer and the control insulation layer;
≪ / RTI >
Mineral organic flash memory device. The photoorganic flash memory device of claim 10 or 11, wherein a positive threshold voltage change or a write operation is implemented when a negative gate voltage and an optical signal are simultaneously applied to the gate of the photoorganic flash memory device. The method according to claim 10 or 11,
A negative threshold voltage change or erase operation is implemented when a positive gate voltage and an optical signal are simultaneously applied to a gate of the photoorganic flash memory device. The method according to claim 10 or 11,
And a two-bit photoorganic memory operation is implemented on each of the source side and the drain side when the source voltage, the gate voltage, and the drain voltage of the photoorganic flash memory device are applied simultaneously with the optical signal. The method of claim 11,
When the source voltage, the gate voltage, and the drain voltage of the photoorganic flash memory device are applied simultaneously with the optical signal, a 4-bit photoorganic memory operation is implemented on each of the source side and the drain side of one side and the other side of the channel. Mineral organic flash memory devices. A light detector for detecting light using a change in a threshold voltage through a combination of an optical signal and an electrical signal applied to a gate of the photoorganic flash memory device of claim 10.

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