KR101275109B1 - Nonvolatile memory device having twin-fins separated by shield electrode and nand flash memory array using the same - Google Patents

Abstract

The present invention provides a nonvolatile memory device capable of fundamentally preventing interference between neighboring cells as a shielding electrode, and a NAND flash memory array capable of significantly increasing the degree of integration by using the same.

Description

Nonvolatile memory device having a twin-pin separated by a shielding electrode and a NAND flash memory array using the same

The present invention relates to a semiconductor memory device and a NAND flash memory array using the same.

In order to increase the memory density in NAND flash memories and the like, studies on the structure of memory cell elements have been continued.

Among them, the FinFET structure has been developed to solve short channel effects (SCE) of planar devices, small lead currents due to leakage current, and drain induced barrier lowering (DIBL).

However, the FinFET structure can solve the problems of the above-described planar structure. However, the FinFET structure can reduce the thickness of the pin required for one cell and the thickness of the ONO (Oxide / Nitride / Oxide) There are certain limitations to this, and it has been pointed out as a problem of high concentration.

In order to solve the problems of the conventional finFET structure as described above, as shown in FIG. 1, as shown in FIG. 1, the substrate 100 is etched to form a silicon fin surrounded by the insulating layer 200, and the silicon fin is formed. The trench is formed by STI dry etching again, and is filled with the isolation insulating layer 300 to be separated into two silicon fins 110 and 120, the ONO layer 400 is formed, and then the gate 500 is formed. By forming two cells in the structure, a paired FinFET structure has been proposed to increase the degree of integration.

Non-Patent Document 1 also discloses a NAND flash memory array using the paired FinFET structure.

However, even with the paired pinpet structure and the NAND flash memory array using the same, there are the following problems.

First, the paired fin pet structure has two fins 110 and 120 separated from each other with a separation insulating film 300 in the middle thereof, so that the paired fin FET structure is different depending on the state of charge stored in the ONO layer 400 of the cell formed at one fin. There is a problem affecting the cells formed on the side pins. This problem becomes more serious as the thickness of the fins 110 and 120 or the thickness of the isolation insulating film 300 is reduced for high integration.

In the case of implementing the NAND flash memory array using the paired finFET structure as shown in FIG. There is a problem in that two selection transistors having different threshold voltages are required on the side (CBL side) and the drain side (CSL side), respectively. In Fig. 2, the selection transistor A shown by a thick line may have a relatively high threshold voltage or a lower value than that of the B transistor.

[Non-Patent Document 1] Sukpil Kim et al., Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage, Symposium on VLSI Technology Digest of Technical Papers, 2006

Accordingly, the present invention is to solve the problem of the conventional paired finpet structure and the NAND flash memory array using the same.

In order to achieve the above object, a nonvolatile memory device according to the present invention comprises a fence-type semiconductor formed to protrude on a semiconductor substrate, an insulating insulating film filled to a certain height of the fence-type semiconductor, and at least the fence-type semiconductor on the insulating insulating film A nonvolatile memory device comprising a gate insulating film stack including charge storage layers formed on both sides of a gate electrode, and a control electrode formed to surround the gate insulating film stack, wherein the fence-type semiconductor intersects with the control electrode and is fixed from above. It is separated by a depth formed of twin pins, the twin pins are characterized in that an insulating film is formed on both sides of the inside, and filled with a shielding electrode between the insulating films.

The shielding electrode may be formed of a semiconductor material or a conductive material doped with impurities.

The charge insulating layer may be formed between two insulating layers of the gate insulating layer stack, and the charge storing layer may be formed of any one selected from nanoparticles and a conductive material.

The shielding electrode may be electrically connected to the semiconductor substrate.

Meanwhile, the NAND flash memory array may include two bit lines formed of the twin pins formed on the fence-type semiconductor in the NAND flash memory array including the nonvolatile memory devices; A shielding line consisting of the shielding electrode formed between the two bit lines; And a plurality of bit lines and shielding lines spaced apart by a predetermined distance from the side surface of the fence-type semiconductor based on the two bit lines and the shielding electrode and having the isolation insulating layer therebetween, wherein the plurality of bit lines and The plurality of word lines may be spaced apart at a predetermined distance in the longitudinal direction of the fence-type semiconductor and formed in a direction perpendicular to the respective bit lines.

Here, one end of the two bit lines constituting the basic unit is connected to one first contact portion, and the other end is connected to the bit line of a neighboring basic unit by one second contact portion, and the first contact portion and A plurality of second contact parts may be formed at predetermined intervals, and one wire may be connected to each contact part.

The plurality of shielding lines may be formed to extend to connect with the first contact portion, respectively.

In addition, one end of the two bit lines constituting the basic unit has a third contact portion formed for each bit line, and the other end is connected to the bit line of the neighboring basic unit by one second contact portion, and thus the second contact portion And a plurality of third contact portions, wherein the plurality of third contact portions are formed to be spaced apart from each other up and down not to overlap with contact portions of neighboring basic units, and one end of the two bit lines constituting the basic unit The layers may be wired with different layers through the third contact portion, and the plurality of second contact portions may be connected with one wire.

The plurality of shielding lines may be formed to extend to be connected to wires connecting the plurality of second contact portions.

In addition, one end of the two bit lines constituting the basic unit is connected to one first contact portion, and the other end is provided with a fourth contact portion for each bit line, and a plurality of the first contact portion and the fourth contact portion are formed. For example, one wire is connected to each of the plurality of first contact parts, and the plurality of fourth contact parts are formed to be spaced apart from each other up and down so as not to overlap with a neighboring contact part. Can be.

In the conventional non-volatile memory device according to the present invention, by separating the fence-type semiconductor into two twin pins by the shielding electrode, the shielding electrode can fundamentally prevent interference between neighboring cells. And / or reduces the width of the shielding electrode and has the effect of being highly integrated.

The NAND flash memory array according to the present invention has a plurality of bit lines intersecting at upper and lower ends and connected to neighboring bit lines, or at least one contact portion connected to neighboring bit lines is formed to facilitate wiring. It becomes unnecessary and there is an effect that can dramatically increase the degree of integration.

Furthermore, the shielding line is extended to the contact portion or the wiring line so that one end thereof is connected to the shielding line, thereby applying a constant voltage (eg, ground) to the shielding line to maximize the shielding effect and perform a necessary operation.

1 is a perspective view illustrating a structure of a conventional paired finFET.
FIG. 2 is a NAND flash memory array using the paired pinpet of FIG. 1.
3 to 8 are process diagrams for manufacturing a nonvolatile memory device according to an embodiment of the present invention.
9 and 10 are part of a process diagram for manufacturing a nonvolatile memory device according to another embodiment of the present invention.
11 to 13 are layouts illustrating a wiring structure of a NAND flash memory array according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

[Inactive Memory Device Example ]

As illustrated in FIG. 8, a nonvolatile memory device according to an exemplary embodiment of the present invention may include a fence-type semiconductor 10a protruding from the semiconductor substrate 10 and an insulating insulating layer 20 filled to a predetermined height of the fence-type semiconductor. And a gate insulating film stack 60 including charge storage layers formed on at least two sides of the fence-type semiconductor on the isolation insulating film, and a control electrode 70 formed to surround the gate insulating film stack. In the device, the fence-like semiconductor 10a is formed into twin pins 11 and 12 separated from the upper portion in a longitudinal direction perpendicular to the control electrode 70 by a predetermined depth, and the twin pins are formed on both sides of the inside. An insulating film 42 is formed and filled with the shielding electrode 50 between the insulating films.

By the above configuration, the shielding electrode 50 can fundamentally prevent the interference between neighboring cells formed on the two twin pins 11 and 12, and thus the width of the twin pins 11 and 12 and / or the shielding electrode. You can reduce the width of (50) and make it as dense as you can.

The shielding electrode 50 may be formed of a semiconductor material (eg, polysilicon doped with impurities) or a conductive material (eg, metal) doped with impurities.

9 and 10, the shielding electrode 50 etches the semiconductor substrate 10 to form fins 14, and is doped with impurities. It can also be formed from the thing 14a.

In addition, although the shielding electrodes 14a and 50 may be surrounded by an insulating layer and floated, the shielding electrodes 14a and 50 may be electrically connected to the semiconductor substrate 10 as shown in FIGS. 8 and 10. By doing the latter, the body bias can be applied through the shielding electrodes 14a and 50, and there is an advantage that the erase operation can be performed.

Next, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention will be briefly described with reference to FIGS. 3 to 8.

First, as shown in FIG. 3, the semiconductor substrate 10 is etched to form a fence-type semiconductor 10a, and then the surroundings of the fence-type semiconductor 10a are filled with an insulating insulating film 20, and the fence-type semiconductor 10a is formed. After the etching mask 30 is formed on the upper portion, the fence-type semiconductor 10a is etched to a predetermined depth using the mask 30 to form the trenches 19 and two twin pins 11 which are the same on both sides. 12) (first step).

Next, as shown in FIG. 4, an insulating film 40 is formed on the surface of the fence-like semiconductor exposed inside the trench 19 through a thermal oxidation process or the like (second step).

Next, as shown in FIG. 5, only the insulating film 42 formed on the bottom of the trench 19 and the insulating film 42 formed on both sidewalls remains (third step).

Subsequently, as shown in FIG. 6, the shielding electrode material is deposited and etched on the entire surface of the substrate to form the shielding electrode 50 in the trench 19, and to insulate the control electrode (gate) on the shielding electrode 50. An insulating film 32 is formed (fourth step).

The shielding electrode material may be a semiconductor material (eg, polysilicon doped with impurities) or a conductive material (eg, metal) doped with the aforementioned impurities.

Subsequently, as shown in FIG. 7, the isolation insulating film 20 is partially etched to expose the two twin pins 11 and 12 (a fifth step).

Next, as shown in FIG. 8, a gate insulating layer stack 60 including a charge storage layer composed of any one selected from nanoparticles and a conductive material is formed on the exposed two twin fins 11 and 12, and then the gate material is deposited. Etching is performed to form the control electrode 70 (sixth step).

Here, the gate insulating layer stack 60 is an ONO (Oxide / Nitride / Oxide) layer, and may be formed only on both sidewalls of the exposed twin fins 11 and 12, as shown in FIG. 8, but the twin fins 11 and 12 may be formed. It may be formed surrounding the three sides of the).

A method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention may be performed by including the process of FIGS. 9 and 10.

That is, as shown in FIG. 9, the isolation insulating film 20 is surrounded by the fence-type semiconductor 10a, and then an etch mask (not shown) is formed, and the fence-like semiconductor 10a is etched to a predetermined depth by using the isolation insulating film 20. After forming the three fins 13, 14, and 15 with the two trenches, the two trenches are filled with the insulating layers 21 and 23 after the etching mask (not shown) is removed.

Subsequently, as shown in FIG. 10, an ion implantation prevention mask (not shown) is formed, and then, impurity ions are implanted into the middle fin 14 of the three fins to form a shielding electrode 14a.

Thereafter, an insulating film (not shown) is formed on the two twin pins 13 and 15 and the shielding electrode 14a, respectively, and the fifth and sixth steps may be performed in the same manner.

[A Array Using Nonvolatile Memory Devices Example ]

Next, an embodiment of a NAND flash memory array using the nonvolatile memory device will be described with reference to FIGS. 11 to 13.

As shown in common in FIGS. 11 to 13, two bit lines 11a and 12a basically formed of the twin pins 11 and 12 formed on the fence-like semiconductor 10a; A shielding line 50a formed of the shielding electrode 50 formed between the two bit lines; And the bit line 11a and 12a and the shielding electrode 50a as the basic units 91 and 92, and are spaced a predetermined distance from the side surface of the fence-type semiconductor 10a and the isolation insulating layer 20 is separated from each other. A plurality of bit lines 11a and 12a and a shielding line 50a are formed between the plurality of bit lines 11a and 12a and the shielding line 50a in the longitudinal direction of the fence-type semiconductor 10a. And a plurality of word lines 70a spaced apart by a predetermined distance and formed in a direction perpendicular to each of the bit lines 11a and 12a.

Accordingly, each word line 70a vertically crosses a plurality of bit lines and shielding lines having the two bit lines 11a and 12a and the shielding electrodes 50a as basic units 91 and 92. At the intersection thereof, memory cell elements consisting of two nonvolatile memory elements are formed.

In this case, the source / drain of the nonvolatile memory device may be formed as an impurity doping layer between neighboring word lines 70a, or may be formed as a fringing field by neighboring word lines 70a. have.

In the memory array configured as described above, the shielding line 50a is formed of a semiconductor material (eg, polysilicon or single crystal silicon doped with impurities) or a conductive material (eg, metal, etc.) doped with impurities. The width can be reduced, and the width of each bit line 11a, 12a can be made as small as possible within the allowable limit of resolution due to the presence of the shielding line 50a, thereby increasing the density of the array.

In the basic array structure, embodiments for contacting each component may be variously implemented, but it is preferable to implement the method shown in FIGS. 11 to 3.

≪ Embodiment 1 >

First, as shown in FIG. 11A, one end (top) of the two bit lines 11a and 12a constituting the basic unit 91 and 92 is connected to one first contact portion 2 or 4. The other end (lower end) is connected to a bit line of a neighboring basic unit and one second contact unit 1, 3, or 5, so that the first contact unit and the second contact unit are provided in plurality (1) at a predetermined interval. , 2, 3, 4, 5, one wire (81) (82) (83) (84) (85) for each of the contact portions (1) (2) (3) (4) (5). This can be connected.

In the basic structure of the array according to the first embodiment, a plurality of bit lines 11a and 12a are adjacent bit lines by contact portions 1, 2, 3, 4, and 5 at upper and lower ends thereof. Are intersected with each other and zigzag-connected, and one wire 81, 82, 83, 84, 85 is connected to each contact portion.

Therefore, according to the structure according to the first embodiment, it is not necessary to make contact for each bit line, thereby reducing the area due to the contact, and also wiring for connecting each contact part can be realized in a single layer, thereby reducing the process steps. There is also an advantage.

≪ Embodiment 2 >

As shown in FIG. 11B, one end (top) of the two bit lines 11a and 12a constituting the basic units 91 and 92 has a third contact portion 2a, 2b; 4b) is formed, and the other end (lower end) is connected to a bit line of a neighboring basic unit and one second contact portion 1, 3, or 5, so that the second contact portion and the third contact portion are plural (1). , 2a, 2b, 3, 4a, 4b, and 5), wherein the plurality of third contact portions 2a, 2b; 4a, 4b are formed so as not to overlap with the contact portions of neighboring basic units. Are formed spaced apart from each other up and down, and one end (upper end) of the two bit lines 11a and 12a constituting the basic units 91 and 92 is the third contact portion 2a, 2b; 4a, 4b. The third contact portions 2a and 4a are connected to the wirings 82a and 84a in the lower layer, respectively, and the third contact portions 2b and 4b are connected to the wirings 82b and 84b in the upper layer, respectively. A plurality of second contact portions ( 1, 3, and 5 may be connected to one wire 87.

According to the structure according to the second embodiment, at least one end of each contact portion (eg, the second contact portion) connected to the neighboring bit line is formed, thereby reducing the area due to the contact.

Third Embodiment

As shown in FIG. 12A, similar to the first embodiment, each shielding line 50a is extended to both ends of each of the bit lines 11a and 12a to form a contact portion (for example, the first). The only difference is that they are electrically connected to the contacts: 2 and 4).

By the above configuration, in addition to the advantages according to the first embodiment, the shielding line 50a may be applied with a constant voltage (for example, ground) to maximize the shielding effect and perform the necessary operation.

<Fourth Embodiment>

As shown in FIG. 12B, similar to the second embodiment, each shielding line 50a is extended to both ends of each of the bit lines 11a and 12a so as to be formed at one end (for example, the wiring 87). The only difference is that they are configured to be electrically connected.

As described above, in addition to the advantages according to the second embodiment, there is also an advantage that a certain voltage (eg, ground) is applied to the shielding line 50a to maximize the shielding effect and perform necessary operations.

<Fifth Embodiment>

As shown in FIG. 13, one end (top) of the two bit lines 11a and 12a constituting the basic unit 91 and 92 is connected to one first contact part 2 or 4 and the other end ( The lower end) has fourth contact portions 1b, 3a, 3b, and 5a formed on each bit line, and a plurality of first and fourth contact portions 1b, 2, 3a, 3b, 4, and 5a are formed. In the plurality of first contact portions 2 and 4, one wire 82 and 84 are connected to each contact portion 2 and 4, and the plurality of fourth contact portions 1b, 3a and 3b are connected to each other. , 5a is formed to be spaced apart from each other up and down so as not to overlap with the neighboring contact portion, alternately different layers and connected to the wiring (for example, the fourth contact portion 1b and 3b are connected to the wiring 81b and 83b in the lower layer, respectively, 4 contacts 3a and 5a may be connected to the wirings 83a and 85a on the upper layer, respectively.

As described above, similarly to the second embodiment, the area due to the contact can be reduced by forming each contact portion (eg, the first contact portion) connected to the neighboring bit line at at least one end.

According to the first to fifth embodiments, the bit lines 11a and 12a can be independently selected by wirings connected to the bit lines 11a and 12a, so that the bit lines for selecting the conventional bit lines are selected. By providing two selection transistors on the bottom and the bottom of the line, unnecessary area is reduced. That is, all the lines crossing the bit lines 11a and 12a are used as the word lines 70a. There is also an advantage that can be increased dramatically.

10: semiconductor substrate
10a: fence-type semiconductor
11, 12: twin pin
30, 32, 42: insulating film
50: shielding electrode
60: gate insulating film stack
70: control electrode

Claims (10)

A gate insulating film stack including a fence-type semiconductor formed to protrude on a semiconductor substrate, an insulating insulating film filled to a predetermined height of the fence-type semiconductor, and a charge storage layer formed on at least both sides of the fence-type semiconductor on the insulating insulating film; In the nonvolatile memory device including a control electrode formed surrounding the gate insulating film stack,
The fence-type semiconductor is intersected with the control electrode and separated into a predetermined depth from the top to form twin pins,
The twin pins are non-volatile memory device, characterized in that the insulating film is formed on both sides of the inside, and filled with a shielding electrode between the insulating film.
The method of claim 1,
The shielding electrode is formed of a semiconductor material or a conductive material doped with an impurity.
The method of claim 1,
The charge insulating layer is formed on the gate insulating layer stack between two insulating layers,
The charge storage layer is a nonvolatile memory device, characterized in that consisting of any one selected from nanoparticles and conductive materials.
The method according to any one of claims 1 to 3,
And the shielding electrode is electrically connected to the semiconductor substrate.
In the NAND flash memory array comprising the nonvolatile memory device of claim 4,
Two bit lines formed of the twin pins formed on the fence-type semiconductor;
A shielding line consisting of the shielding electrode formed between the two bit lines; And
The bit line and the shielding line are spaced apart by a predetermined distance from the side surface of the fence-type semiconductor based on the two bit lines and the shielding electrode, and the plurality of bit lines and the shielding line are formed between the isolation insulating layers. And a plurality of word lines spaced apart from each other in the longitudinal direction of the fence-type semiconductor in a longitudinal direction on a line and formed in a direction perpendicular to each of the bit lines.
The method of claim 5, wherein
One end of the two bit lines constituting the basic unit is connected to one first contact portion, and the other end is connected to the bit line of a neighboring basic unit and one second contact portion, so that the first contact portion and the first contact portion are connected to each other. 2 contact parts are formed in a plurality at regular intervals,
NAND flash memory array, characterized in that one wire is connected to each of the contact portion.
The method of claim 5, wherein
One end of the two bit lines constituting the basic unit has a third contact portion formed for each bit line, and the other end is connected to a bit line of a neighboring basic unit with one second contact portion, so that the second contact portion and the A plurality of third contact portion is formed,
The plurality of third contact portions are formed to be spaced apart from each other up and down not to overlap with contact portions of neighboring basic units,
One end of the two bit lines constituting the basic unit are wired in different layers through the third contact portion,
And the plurality of second contact portions are connected by one wire.
The method according to claim 6,
And the plurality of shielding lines are formed to extend to connect with the first contact portion, respectively.
The method of claim 7, wherein
And the plurality of shielding lines extends to be connected to wires connecting the plurality of second contact portions.
The method of claim 5, wherein
One end of the two bit lines constituting the basic unit is connected to one first contact part, and the other end is formed with a fourth contact part for each bit line, and the plurality of first contact parts and the fourth contact parts are formed.
One wire is connected to each of the plurality of first contact units.
The plurality of fourth contact portions are formed to be spaced apart from each other up and down so as not to overlap with a neighboring contact portion, and the wirings are alternately alternately connected to each other.

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