KR101273074B1 - Interface device of digital circuit - Google Patents

Abstract

An interface device of a digital circuit according to the present invention is connected to a first digital circuit having a single bus and a second digital circuit having a plurality of buses, and the first digital circuit is mapped by mapping a single bus signal specification and a multiple bus signal specification. The single signal transmitted from the plurality of signals is separated into a plurality of signals and transmitted to the second digital circuit, and the plurality of signals transmitted from the second digital circuit are combined into a single signal and transmitted to the first digital circuit.

According to the interface device of the digital circuit according to the present invention, it is possible to implement a system by connecting digital circuit products having different signal specifications (by being produced by different manufacturers), and thus, to develop a new compatible product. Production resources, such as research, development costs, development periods, expansion of production facilities, and establishment of a sales network, will not be wasted.

Description

Interface device of digital circuit

1 is a diagram illustrating a type in which a commonly used MSM is connected to an RFIC chipset.

2 is a block diagram schematically illustrating a form in which an interface device of a digital circuit is connected to an external device according to an embodiment of the present invention.

3 is a block diagram schematically showing components of an interface device of a digital circuit according to an embodiment of the present invention;

Description of the Related Art

100: interface device of the digital circuit 105: SSBI bus unit

110: SBDT bus section 115: SBCK bus section

120: SBST bus section 125: signal synthesis section

130: first comparison unit 140: storage unit

142: mapping table 145: second comparison unit

150: signal separation unit

The present invention relates to an interface device of a digital circuit.

Currently, personal portable terminals such as mobile phones, PDAs (Personal Digital Assistants), notebook computers, smart phones, portable multimedia players (PMPs), etc. are widely used. Such personal portable terminals generally have a wireless communication function.

The portable terminal includes a radio frequency integrated circuit (RFIC) chipset for processing an RF signal, a baseband signal, and a digital signal (hardware layer), and a communication modem for interpreting the digital signal (software layer) and processing the multimedia data. .

Therefore, a general communication modem must communicate with the RFIC chipset essentially (for example, the RFIC chipset may be a circuit for processing a CDMA signal, a GSM signal, a WCDMA signal, or a GPS signal).

Currently, the most commonly used method for communication between a communication modem and an RFIC chipset is a method using three serial buses. If the manufacturers (makers) of the communication modem and the RFIC chipset are the same, there is no problem. In this case, there is a problem in the interface because of differences in data transmission standards.

In order to solve this problem, for example, a manufacturer of a GSM chip may make a standard such as DigRF, which is difficult to use.

As a more specific example of the above problem, currently, communication modems installed in mobile communication terminal products are mainly made up of Qualcomm's MSM (Mobile Station Modem) products. The serial bus method is used.

1 is a diagram illustrating a type in which a commonly used MSM is connected to an RFIC chipset.

As shown in FIG. 1, the MSM 10 uses a 3-wire serial bus interface (SBI) scheme to communicate with the RFIC chipset 20. In the SBI scheme, the SBST bus 13 and the SBCK bus ( 12) and three buses such as the SBDT bus 11.

The SBDT bus 11 is a bidirectional bus, and the SBST bus 13 and the SBCK bus 12 are unidirectional buses. In this way, Qualcomm's MSM is compatible with third-party RFIC chipsets.

However, Qualcomm plans to switch the data transmission standard of MSM 10 to SSBI (1 wire serial bus) method using one bus in the future, which is SBST bus 13, SBCK bus 12, SBDT. The bus 11 implements data processed by a single bus.

This SSBI approach makes MSM products incompatible with other manufacturers' RFIC chipset products (other than Qualcomm's RFIC chipset products) (SSBI's data transfer specifications are generally unpublished).

Therefore, in order to manufacture a personal mobile terminal using MSM products and RFIC chipset products produced by different manufacturers, there is a problem in that new products must be newly developed to meet signal specifications.

The present invention provides an interface device for digital circuits that can communicate with each other by interpreting / converting data of digital circuit products having different signal standards, and thus can build a single system using digital circuit products of different manufacturers. .

An interface device of a digital circuit according to the present invention is connected to a first digital circuit having a single bus and a second digital circuit having a plurality of buses, and the first digital circuit is mapped by mapping a single bus signal specification and a multiple bus signal specification. The single signal transmitted from the plurality of signals is separated into a plurality of signals and transmitted to the second digital circuit, and the plurality of signals transmitted from the second digital circuit are combined into a single signal and transmitted to the first digital circuit.

Hereinafter, an interface device of a digital circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a form in which an interface device 100 of a digital circuit according to an embodiment of the present invention is connected to external devices 10 and 20.

Referring to FIG. 2, the interface device 100 (hereinafter referred to as an “interface device”) of the digital circuit is connected to the first digital circuit 10 and the second digital circuit 20. It is assumed that one digital circuit 10 is a mobile station modem (MSM) and the second digital circuit 20 is an RFIC chipset.

The MSM 10 includes a single bus therein and is connected to the interface device 100 through one line.

In addition, the RFIC chipset 20 includes a plurality of buses therein and is connected to the interface device 100 through a plurality of lines.

In the embodiment of the present invention, the RFIC chipset 20 is provided with three buses, and thus the interface device 100 is connected to the RFIC chipset 20 through three lines.

As described above, since the number of buses mounted in the MSM 10 and the RFIC chipset 20 are different, the respective signal processing standards and the transmission standards are also different. Bus signal standard ", and the signal standard of the RFIC chipset 20 is called" many bus signal standard ".

The interface device 100 separates a single signal transmitted from the MSM 10 into a plurality of signals (hereinafter, referred to as "multiple signals") by mapping a single bus signal standard and a multiple bus signal standard to the RFIC chipset 20. To send.

In addition, the interface device 100 maps a single bus signal specification and a multiple bus signal specification to synthesize a plurality of signals transmitted from the RFIC chipset 20 into a single signal and transmit the same to the MSM 10.

Hereinafter, the interface device 100 of the digital circuit according to the present invention will be described in detail with reference to FIG. 3.

3 is a block diagram schematically illustrating components of an interface device 100 of a digital circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the interface device 100 includes a single signal bus unit 105, a plurality of signal bus units 110, 115, and 120, a signal synthesis unit 125, a first comparison unit 130, It includes a storage unit 140, the second comparison unit 145 and the signal separation unit 150.

As described above, since the interface device 100 according to the embodiment of the present invention is connected to the MSM 10 through one line, it requires one single signal bus unit 105. In general, the MSM ( Since the signal input / output from 10) is called an SSBI signal, the single signal bus unit 105 will be described as an “SSBI bus unit”.

In addition, since the interface device 100 according to the embodiment of the present invention is connected to the RFIC chipset 20 through three lines, three multiple signal bus units 110, 115, and 120 are required. Since the signals inputted and outputted through the three lines of 20) are respectively referred to as SBDT signals, SBCK signals, and SBST signals, the three multiple signal bus units 110, 115, and 120 are respectively referred to as “SBDT bus units” and “SBCK bus units”. "," SBST bus part "will be described.

The SSBI bus unit 105 receives a single signal from the MSM 10 and transfers it to the second comparator 145 or receives a single signal synthesized from the signal synthesis unit 125 and outputs the single signal to the MSM 10. .

The SSBI signal transmitted from the SSBI bus unit 105 is a control signal including data start information and synchronization information, a clock signal for synchronizing a signal, and a signal in which the data signal is synthesized into one signal, and the control signal is SBST. Corresponds to the SBST signal processed by the bus unit 120.

In addition, the clock signal corresponds to the SBCK signal processed by the SBCK bus unit 115, and the data signal corresponds to the SBDT signal processed by the SBDT bus unit 110.

Accordingly, the SSBI signal can be viewed as a sum of the SBST signal, the SBCK signal, and the SBDT signal into one signal.

Meanwhile, the SBDT bus unit 110 receives the SBDT signal from the RFIC chipset 20 and transmits the SBDT signal to the first comparator 130, and receives the SBDT signal separated from the signal separator 150 to receive the RFB chipset 20. )

The SBCK bus unit 115 receives the SBCK signal from the RFIC chipset 20 and transmits the SBCK signal to the first comparator 130, and receives the SBCK signal separated from the signal separation unit 150 to receive the RFIC chipset 20. Will output

In addition, the SBST bus unit 120 receives the SBST signal from the RFIC chipset 20 and transmits the SBST signal to the first comparator 130, and receives the SBST signal separated from the signal separation unit 150 to receive the RFB chipset ( 20).

The SSBI bus unit 105, the SBDT bus unit 110, the SBCK bus unit 115, and the SBST bus unit 120 connect a connection line between the MSM 10 and the RFIC chipset 20 with an internal circuit network and perform a signal. A transmission device for distributing a, has a circuit arrangement structure programmed to recognize only a signal assigned to it and ignore the remaining signals.

The signal synthesizing unit 125, the first comparing unit 130, the signal separating unit 150, and the second comparing unit 145 each have a unique address, and the bus units 105, 110, 115, and 120 have a unique address. Identifies the signals, finds the address given to the signal, and distributes the signal to the component corresponding to the address.

The storage unit 140 stores the mapping table 142 containing the conversion information of the single bus signal standard and the multiple bus signal standard, and is connected to the first comparator 130 and the second comparator 145 to map the table. It provides the data of 140, for example, may be provided as a semiconductor memory device such as a flash memory.

As described above, the SSBI signal is a signal in which the SBDT signal, the SBCK signal, and the SBST signal are combined, and a plurality of frequency signals may be separately analyzed through a logic analyzer.

For reference, since the SBCK signal and the SBST signal have a simple signal format, the SBCK signal and the SBST signal are easy to analyze. Radio Frequency IDentification) As the actual data such as tag information data, the signal type is complicated.

Therefore, the operation of analyzing the separated signal as a digital signal and confirming is performed, and by repeating the separation / analysis operation as described above, it is possible to know what standard the SBDT signal is contained on the SBSI signal.

The mapping table 142 is a database of signal conversion information in which the standards of the SBDT signal, the SBCK signal, and the SBST signal, and the standards of the SSBI signal in which they are combined are mapped.

The mapping table 142 generated through the logic analyzer and the external computer may be loaded into the storage 140 through the write function of the storage 140.

Meanwhile, the first comparison unit 130 is connected to the SBDT bus unit 110, the SBCK bus unit 115, and the SBST bus unit 120 to receive the SBDT signal, the SBCK signal, and the SBST signal, respectively. The first comparison information is generated by comparing the information with the conversion information of the mapping table 142.

The generated first comparison information, the SBDT signal, the SBCK signal, and the SBST signal are transmitted to the signal synthesis unit 125.

The signal synthesizing unit 125 converts and synchronizes the SBDT signal, the SBCK signal, and the SBST signal according to the standard according to the first comparison information, and synthesizes the single signal (SSBI signal) on one frequency signal.

The signal synthesizing unit 125 transmits the synthesized SSBI signal to the SSBI bus unit 105, and the SSBI bus unit 105 transmits the SSBI signal to the MSM 10.

For reference, if the SBCK signal and the SBST signal are to be processed as unidirectional signals, a circuit may be configured such that the SBCK bus unit 115 and the SBST bus unit 120 are not connected to the first comparator 130.

The second comparison unit 145 is connected to the SSBI bus unit 105 to receive the SSBI signal, and compares the SSBI signal with conversion information of the mapping table 142 to generate second comparison information.

The generated second comparison information and the SSBI signal are transmitted to the signal separator 150.

The signal separation unit 150 decomposes the SSBI signal according to various signal standards according to the second comparison information, maintains the decomposed signal according to a format, and loads the signal on each frequency signal, thereby placing the SBDT signal, SBCK signal, and SBST. Generate a signal.

The signal separation unit 150 transmits the generated SBDT signal, SBCK signal, and SBST signal to the SBDT bus unit 110, the SBCK bus unit 115, and the SBST bus unit 120, respectively. Transmitted to the RFIC chipset 20.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications not illustrated in the drawings are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

According to the interface device of the digital circuit according to the present invention, it is possible to implement a system by connecting digital circuit products (communication modem products and RFIC chipset products) having different signal specifications (by being produced by different manufacturers), Therefore, it is possible to avoid wasting production resources such as research, development costs, development periods, expansion of production facilities, and sales network for newly developing compatible products.

Claims (6)

A single signal bus unit connected to a first digital circuit having a single bus and identifying and transmitting a single signal; A plurality of signal bus units connected to a second digital circuit having a plurality of buses and identifying and transmitting a plurality of signals; A storage unit for storing a mapping table of the single bus signal standard and the multiple bus signal standard; A signal separation unit for separating the single signal into a plurality of signals using the mapping table and transferring the separated plurality of signals to the plurality of signal bus units; And A signal synthesizing unit for synthesizing the plurality of signals into the single signal using the mapping table and transferring the synthesized single signal to the single signal bus unit. Interface device of the digital circuit comprising a. The method of claim 1, The first digital circuit is a communication modem, And said second digital circuit is an RFIC chipset. The method of claim 1, wherein the majority signal Interface device of a digital circuit which is at least one individual signal among a control signal, a clock signal, and a data signal. The method of claim 1, wherein the single signal is An interface device of a digital circuit which is a synthesized signal including at least one of a control signal, a clock signal, and a data signal. delete The method of claim 1, Receiving a plurality of signals from the plurality of signal bus units, comparing the transmitted multiple signals with a single bus signal specification of the mapping table, generating first comparison information, and transmitting first comparison information to the signal synthesis unit; part; And Receiving a single signal from the single signal bus unit, comparing the transmitted single signal with the multiple bus signal specifications of the mapping table, generating second comparison information, and transmitting a second comparison information to the signal separation unit; An interface device of a digital circuit comprising a portion.

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