KR101270763B1 - Method for producing reconfigable processing array architecture - Google Patents

Abstract

The present invention relates to a method for generating a reconfigurable processing array structure, the method comprising obtaining information about data dependencies between operations and operations constituting at least one or more applications compiled from a compiler, The present invention provides a method of generating a reconstructed processing array structure that adds interconnections between processing elements to an underlying reconstructed processing array structure to create an extended reconstructed processing array structure.

Description

Method for producing reconfigable processing array architecture

The present invention relates to a method for generating a reconstructed processing array structure, and more particularly, to reconstructed processing for generating an extended reconstructed processing array structure by adding interconnections between processing elements to a base reconstructed processing array structure. A method of generating an array structure.

The research for the present invention was supported by the BK21 project (project unique number: 0567-20100001), which is organized by the Information Technology Business Division of the Ministry of Education, Science and Technology.

In recent years, in order to cope with the increase in NRE cost and rapid change in applications, there are increasing cases of using reconfigurable processors with performance close to Application Specific Intergrared Circuit (ASIC) while being flexible for various applications.

Reconfigurable processors have received a lot of attention recently because they have a flexible hardware structure and can dynamically change internal configurations and maintain high performance while performing various operations.

These reconfigurable processors are divided into fine-grain reconfigurable processors that can be bit-level reconstructed using FPGAs and coarse-grained reconfigurable processors that can be reconstructed by word-level reconstruction.

One of the most important issues in determining the connection structure between functional units of such a reconfigurable processor is design space exploration (DSE). Here, DSE refers to the process of searching for a design structure that provides the desired performance while designing the hardware and consumes the least cost.

Previous studies on the DSE of a reconfigurable processor have been mainly limited to suggesting a regular structure that shows the best performance by analyzing the performance of several regular structures.

Therefore, there is a need for a technique of providing a reconfigurable processor having an extended structure by adding a configuration according to the DSE to an existing regular structure.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of generating a reconfigured processing array structure in which an extended reconfigured processing array structure is generated by adding interconnections between processing elements to a base reconfigured processing array structure.

In order to achieve the above technical problem, according to the present invention, a method for generating a reconfigurable processing array structure includes a data dependency indicating a data dependency relationship between operations and operations constituting at least one or more applications compiled from a compiler. obtaining information regarding dependencies; And adding an interconnection between the processing elements belonging to the base reconstructed processing array structure to the base reconstructed processing array structure based on the obtained information on the operations and data dependencies to generate an extended reconstructed processing array structure. A generation step.

Preferably, the basic reconstructed processing array structure may be a structure of a two-dimensional array in which processing elements of the number or more of the obtained operations are connected in a network in a mesh form.

Preferably, deriving the required number of processing elements based on the obtained information about the operations and data dependencies, and further selecting a base reconstructed processing array structure comprising at least the derived number of processing elements. It may include.

Preferably, the generating step maps the processing elements and the interconnections between the processing elements and the obtained operations and data dependencies of the base reconstructed processing array structure with each other, thereby basing the reconstructed processing on the base reconstructed processing array structure. A mapping case step of generating a mapping case adding an interconnect corresponding to data dependencies not corresponding to the interconnections of the array structure; A mapping case selecting step of selecting a mapping case having the smallest number of added interconnections among the generated mapping cases; And generating an extended reconfigurable processing array structure based on the selected mapping case.

Preferably, the mapping case generating step comprises converting each of the processing elements belonging to the basic reconstructed processing array structure into a first data structure in the form of a graph with VERTEX and interconnections between the processing elements as EDGE; Converting the obtained operations and data dependencies into a second data structure in the form of a graph with VERTEX and EDGE, respectively; And generating a mapping case by mapping the first data structure and the second data structure to each other.

Preferably, the mapping case generation step may share information about the obtained operations and data dependencies, a dedicated processing element allocated per row of the underlying reconstructed processing array structure, among other processing elements belonging to the same row. The method may further include classifying the operations obtained based on the shared resource constraints limited to the resources by row of the two-dimensional array of the basic reconstructed processing array structure.

Preferably, the dedicated processing element handles an arithmetic-logic unit (ALU) that handles arithmetic logic operations, a multiplier that handles multiplication operations, a floating point unit (FPU) that handles floating-point operations, and memory operations. It may include at least one or more of the load / store unit (LSU).

Preferably, the mapping case generation step may be based on the sorted result, a plurality of operations belonging to the same row among the operations one-hop distance from the self, and operations having data dependencies at the same time and two or more hops with themselves. Searching for operations with a data dependency and operations belonging to another row among the operations at distance; And an additional interconnect decision step of determining an interconnect to add to the underlying reconfigured processing array structure based on the data dependencies of the discovered operations.

Preferably, the further interconnect determination step comprises the steps of: mapping the data dependencies of the retrieved operations to a routing interconnect routed through a non-mapping processing element that is not mapped with the operations obtained from the compiler and the data dependencies of the discovered operations. Mapping the remaining data dependencies not mapped to the routing interconnect to the interconnect to add to the underlying reconfigured processing array structure.

Preferably, the generating step adds the obtained operations to the nodes of the tree structure, and adds the data dependencies between the operations added to the nodes according to the result of comparing the interconnections between the processing elements of the underlying reconstructed processing array structure. A-star search (A *) that calculates the additional cost of interconnection to be interconnected and the minimum additional cost incurred according to the data dependencies not yet compared, and then weights the sum of these sums. performing a search); And generating an extended reconfigurable processing array structure based on the least cost graph form derived through the A-Star search.

Preferably, the compiler selects at least one or more applications from among the plurality of applications based on a predetermined priority with respect to the plurality of applications, and when there are a plurality of applications to be executed, the compiler prioritizes the selected at least one or more applications. By compiling in order, information about data dependencies representing operations and data dependencies between the operations constituting the compiled applications may be provided.

Preferably, the base reconstructed processing array structure and the extended reconstructed processing array structure may be structures of a coarse grain reconstructed array.

A computer-readable recording medium containing a program including a function for generating a reconfigurable processing array structure according to the present invention for achieving the above technical problem, comprising at least one application compiled from a compiler Obtaining information about data dependencies indicative of operations and data dependency relationships between the operations; And adding an interconnection between the processing elements belonging to the base reconstructed processing array structure to the base reconstructed processing array structure based on the obtained information on the operations and data dependencies to generate an extended reconstructed processing array structure. Lists programs that contain functions.

According to the present invention, an extended reconfigurable processor array structure capable of performing high performance at a relatively low cost compared to conventional reconfigurable processor array structures (eg, mesh type, 1-hop type, diagonal type, mixed type) is generated. can do.

1A is a diagram illustrating a general template of a coarse grain reconstructed array structure, which is a preferred example of a reconstructed processing array structure.
FIG. 1B is a diagram illustrating a configuration of a processing element that is one component of a coarse grain reconstructed array structure, which is a preferred example of the reconstructed processing array structure.
2A through 2D are diagrams illustrating a reconfigured processing array structure of a general reconfigured processor.
3 is a diagram illustrating an embodiment of a method of generating a reconfigurable processing array structure according to an exemplary embodiment of the present invention.
4A to 4C are diagrams illustrating mapping cases generated through a mapping case generation process in a reconstruction processing array structure generation method according to an exemplary embodiment of the present invention.
5 maps the information obtained from the compiler and the underlying reconfigured processing array structure in the method of generating a reconfigured processing array structure according to an exemplary embodiment of the present invention, and derives interconnections to be added to the existing base reconstructed processing array structure. It is a diagram illustrating the flow of a process to.
6A through 6H illustrate a process of deriving an extended reconfigurable processing array structure by performing an A-star search according to an exemplary embodiment of the present invention.

The following merely illustrates the principles of the invention. Thus, those skilled in the art will be able to devise various apparatuses which, although not explicitly described or shown herein, embody the principles of the invention and are included in the concept and scope of the invention. Furthermore, all of the conditional terms and embodiments listed herein are, in principle, intended only for the purpose of enabling understanding of the concepts of the present invention, and are not intended to be limiting in any way to the specifically listed embodiments and conditions . It is also to be understood that the detailed description, as well as the principles, aspects and embodiments of the invention, as well as specific embodiments thereof, are intended to cover structural and functional equivalents thereof. In addition, these equivalents should be understood to include not only equivalents now known, but also equivalents to be developed in the future, that is, all devices invented to perform the same function regardless of structure.

Thus, the functionality of the various elements shown in the figures, including functional blocks represented by a processor or similar concept, can be provided by the use of dedicated hardware as well as hardware capable of executing software in conjunction with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, a single shared processor, or a plurality of individual processors, some of which may be shared. Also, the use of terms such as processor, control, or similar concepts should not be construed as exclusive reference to hardware capable of executing software, but may include, without limitation, digital signal processor (DSP) hardware, (ROM), random access memory (RAM), and non-volatile memory. Other hardware may also be included.

The above objects, features and advantages will become more apparent from the following detailed description in conjunction with the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

On the other hand, when an element is referred to as "including " an element, it does not exclude other elements unless specifically stated to the contrary.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A is a diagram illustrating a general template of a coarse-grained reconfigurable array (CGRA) structure, which is a preferred example of a reconfigurable processing array structure.

Referring to FIG. 1A, a CGRA 100 structure includes a processing element array (PE array) in which processing elements (PE) 110 for parallel computation are connected to a mesh network in a mesh form to form a two-dimensional array structure. 120).

Each of the processing elements 110 constituting the processing element array 120 is configured with a local memory 130 and a main memory 160 through a set of data buses operating on each row of the processing element array 120. Receive / transmit data manually.

The processing elements PE 110 are computational units capable of performing mathematical or logical operations, multiplications or load / store, and the processing elements 110 load data from the local memory 130. It can also store and store the output of neighboring processing elements through interconnected networks.

Many resource-constrained CGRA designs have dedicated processing elements for specific functions. For example, for each row of the processing element array, some processing elements are reserved for arithmetic operations or multiplications, and some other processing elements are for loading and storing to or from local memory 130. Reserved for execution. As such, the functions assigned to each processing element (ie, the choice of source operands, the destination of the result of the operation, and the operation to be executed) are stored in configuration memory 140, which is the result of compiling the application against CGRA. Is generated.

In general, representative of such dedicated processing elements are arithmetic-logic units (ALUs) for arithmetic logic operations, multipliers for multiplication operations, and floating-point units (FPUs) for floating-point operations. There are load / store units (LSUs) that process memory operations, and they are limited to shared resources, and only one is allocated to each row of the processing element array 120 to be shared by other processing elements belonging to the same row. It can also be configured for use.

For example, in FIG. 1A, an LSU of the processing elements constituting the processing element array is indicated by hatching. 1A, one LSU is assigned to each row of the processing element array.

In general, CGRA is used as a coprocessor for the main processor 150. The main processor 150 manages the execution of the CGRA, such as loading the CGRA configuration and initiating the CGRA execution, via memory-mapped I / O. When the CGRA starts executing, the main processor 150 may perform other tasks. Interrupts can be used to notify the end of CGRA execution. The local memory 130 of the CGRA is managed by the CGRA through a DMA controller (not shown). Hardware double bufferumg allows full overlap between computations and data transfers in CGRA as well as fast switches between buffers. This is very important for large loops that may require multiple buffer switches while executing a single loop.

FIG. 1B is a diagram illustrating the configuration of a processing element 110 that is one component of the coarse grain reconstructed array structure 100 shown in FIG. 1A.

The processing element 110 may include first and second multiplexers 111 and 112 that receive operation output values of neighboring processing elements and operation output values of the neighboring processing elements, a functional unit (FU) 113 to perform an operation, An output register 114 for storing the arithmetic output value of the functional unit 113 and outputting it externally, and a register file 115 for feeding back the arithmetic output value of the functional unit 113. The processing element (PE) 110 is connected to the configuration memory 140 and functions according to functions stored in the configuration memory 140 (ie, selection of source operands, destination of operation results, and execution). Operation).

As shown in FIG. 1A, a typical CGRA has two storage units. One is configuration memory 140 and the other is local memory 130. Configuration memory 140 provides a configuration of instructions (configuration code) executed by processing elements 110. The instructions include information about the operations performed by the processing elements 110 and the interconnections between the processing elements 110. The instructions also include information about when data in the local memory 130 should be loaded onto the data bus and when the data on the bus should be stored into the local memory 130, so that the processing elements 110 may It is possible to receive and transmit data without a separate address generation unit (not shown).

The execution of the CGRA can generally be divided into three phases: an input data loading step (first step), a calculation step (second step), and an output data transmission step (third step).

In the input data loading step (first step), the input data is transmitted to the local memory 130. Input data may be written directly by the processor 150 as a result of task execution or transmitted from main memory 160. Processing element array 120 begins the calculation by getting instructions from configuration memory 140 and also input data from local memory 130. Processing element array 120 then generates output data and writes back to local memory 130 to complete the calculation step (second step). In the output data transfer step (third step), the output data may be processed by the processor 150 or other masters (not shown) of the system or copied to main memory 160 for later use.

2A to 2D illustrate a structure of a reconfigured processing array of a general reconfigured processor, and FIGS. 2A to 2D illustrate a mesh reconstructed processing array structure and a 1-hop reconfigured processing array, respectively. A structure, a diagonal reconstructed processing array structure and a mixed reconstructed processing array structure are shown, respectively.

In the embodiment of the present invention described below, as the base reconstructed processing array structure that is the base unit of the expansion of the reconstructed processing array structure, by selecting the mesh reconstructed processing array structure shown in Figure 2a There is proposed a method of generating an extended reconfigured processing array structure from this, but selecting a mesh type reconfigured processing array structure as the base reconfigured processing array structure is just one embodiment, and the present invention It is not limited to this.

3 is a diagram illustrating an embodiment of a method of generating a reconfigurable processing array structure according to an exemplary embodiment of the present invention.

Referring to FIG. 3, first, the compiler compiles at least one or more applications (S310) to obtain information about operations constituting the applications and data dependencies indicating data dependency relations between the operations. Create

In the present embodiment, when compiling at least one or more applications in the compiler, when there are two or more (plural) applications, the priority may be specified for each application, and may be configured to compile according to these priorities. .

For example, a high-priority application may be compiled from a low-priority application to generate information of operations and data dependencies, or only a few high-priority applications may be compiled to generate information of operations and data dependencies. It can be implemented to provide as reference information of the processing array structure generation.

In operation S320, information about the operations and data dependencies generated through the S310 may be obtained from the compiler.

In operation S330, mapping cases in which operations and data dependencies obtained in operation S320 are mapped to each other are processed at the processing elements and the interconnections between the processing elements of the basic reconstructed processing array structure.

The mapping cases in step S330 are generated by adding interconnections corresponding to data dependencies to the basic reconfigured processing array structure.

As the basic reconstructed processing array structure according to the present embodiment, a mesh reconstructed processing array structure in which at least one processing element obtained in operation S320 is connected to a mesh network to form a two-dimensional array structure. However, this is only one embodiment, and the present invention is not limited thereto.

In general, since there should be more processing elements than the operations to be mapped, the number of processing elements required for the base reconstructed processing array structure is derived based on the information on the operations and data dependencies obtained in step S320, and at least, It may be implemented to select a base reconstructed processing array structure that includes more than the derived number of processing elements.

The mapping case having the smallest number of interconnections to be added is selected from the mapping cases generated in step S330 (S340).

Based on the mapping case selected in step S340, an interconnection is added to the base reconfigured processing array structure to generate an extended reconfigured processing array structure (S350).

4A through 4C are diagrams illustrating mapping cases generated through a mapping case generation process among the reconfigurable processing array structure generation method shown in FIG. 3.

4A to 4C, the present embodiment may be configured to convert the information obtained from the basic reconstructed processing structure and the compiler into a data structure in the form of a graph, and to map the two to each other.

More specifically, FIG. 4A illustrates an example of converting each of the processing elements belonging to the basic reconstructed processing array structure to VERTEX, and converting the interconnection between the processing elements into a first data structure in the form of a graph.

4B shows an example of converting the operation and data dependencies obtained from the compiler into a second data structure in the form of a graph with VERTEX and EDGE, respectively.

4C illustrates an example of a mapping case generated by mapping the converted first data structure and the second data structure to each other.

In this way, when the two are mapped by converting the data into a graph-like data structure, the mapping case can be more easily generated by using an inexact graph matching algorithm.

5 maps the information obtained from the compiler and the underlying reconfigured processing array structure in the method of generating a reconfigured processing array structure according to an exemplary embodiment of the present invention, and derives interconnections to be added to the existing base reconstructed processing array structure. It is a diagram illustrating the flow of a process to.

Referring to FIG. 5, first, a two-dimensional array of basis reconstructed processing array structure to map operations obtained from a compiler and information obtained from a compiler based on shared constraints and information about operations and data dependencies obtained from a compiler. Scatter by the rows of (S510).

At this time, the shared constraint is limited to shared resources that can be shared by other processing elements belonging to the same row by allocating dedicated processing elements for each row of the underlying reconfigurable processing array structure in order to utilize the limited resources more efficiently. One dedicated processing element is an arithmetic-logic unit (ALU) that handles arithmetic logic operations, a multiplier that handles multiplication operations, a floating point unit (FPU) that handles floating-point operations, and memory. This may be a load / store unit (LSU) that processes an operation.

Based on the results classified in step S510, the data dependencies that are difficult to map to the interconnection of the base reconstructed processing array structure are searched for (S520).

Data dependencies that are difficult to map to the interconnects of the underlying reconfigured processing array structure can be classified into two categories.

Firstly, the data dependencies of operations that have data dependencies simultaneously with a plurality of operations belonging to the same row among the adjacent ones, that is, one-hop distances, form a fork shape, and a base reconstruction processing array. It contains data dependencies that are difficult to map to the mesh network connection of the. In this embodiment, such a case is referred to as "fork".

Second, it is difficult to map to the mesh network connection of the underlying reconstructed processing array in the case of data dependency between itself and operations belonging to another row of operations that are more than two hops away. In this embodiment, this case is referred to as "over-length edge".

That is, in step S520, data dependencies that are difficult to map to the interconnection of the base reconstruction processing array corresponding to the fork and over-length edges are searched for.

By determining whether or not data dependencies that are difficult to map to the interconnection of the underlying reconstructed processing array discovered in step S520 can be mapped to routing interconnects routed through operations obtained from the compiler and unmapped processing elements that are not mapped. If it can be mapped to this routing interconnection (S530).

This is because implementing data dependencies between operations to be routed through non-mapping processing elements on the underlying reconfigured processing array structure is much less expensive than adding new interconnects to the underlying processing array structure.

The remaining data dependency not mapped to the routing interconnect is determined as an interconnect to be added to the basic reconfigured processing array structure in operation S530 (S540).

6A to 6H are diagrams illustrating in more detail a process of deriving an extended reconfigurable processing array structure by performing an A * search according to an exemplary embodiment of the present invention.

In the present embodiment, an extended reconfigurable processing array structure is derived using an A * search algorithm.

Here, A-Star Search is a typical graph search algorithm that searches the least cost path (graph form) from the starting point to the target point, and heuristic function is used to evaluate how close to the target. do.

That is, the function f (n) for estimating the cost in the A-Star search is from g (n), which computes the weight from the starting point (e.g., root of the tree structure) to the current node n, and from the current node n. The sum of h (n), which calculates the weight that we expect to have if we went to the best option up to the target point, where h (n) is expected to be the best choice. It is characterized by using a customized heuristic function.

In this embodiment, the operations obtained by the compiler are added to the nodes of the tree structure, and A-star search is performed to derive the minimum cost graph form.

According to this embodiment, g (s) of the A-Star search should be added according to the result of comparing the data dependencies between the operations added to the node in the current state s with the interconnection between the processing elements of the underlying reconstructed processing array structure. Calculated by calculating the additional costs incurred for each interconnection, h (s) is calculated by calculating the minimum additional estimated costs incurred for data dependencies that have not yet been compared. Evaluate.

In the present embodiment, in calculating the additional incurring cost and the additional estimated cost in g (s) and h (s), respectively, the data dependency that is difficult to map to the interconnection of the underlying reconfigurable processor array structure is passed through the non-mapping processing element. The unit cost when configuring routing is defined as C ₁ , and the unit cost when configuring data dependency by adding a separate interconnect is defined as C ₂ , and each of them is arbitrarily given a value of 1 and 3 to calculate the cost. do.

In the present embodiment, the number of data dependencies that are not mapped in the current state s, which are hard to map to the interconnection of the underlying reconfigurable processor array structure, is referred to as N _r , and the fork searched in the current state as in the following formula: It is calculated by summing the number of times N _f and the number of over-length edges (| E ₀ |).

The specific formula for calculating h (s) in the present embodiment is as follows.

Where N _i is the number of operations that are not mapped in the current state s.

First, according to Equation 1, the number of data dependencies (N _r ) that are difficult to map to the interconnection of the underlying reconfigurable processor array structure among data dependencies not mapped in the current state is calculated, and To determine if the number can be resolved through routing later, the calculated number of data dependencies N _r is compared with the number N _i of the unmapped operations in the current state.

The comparison shows that if there are more nodes that are not yet mapped than data dependencies that are difficult to map, the cost of resolving these data dependencies through routing between nodes that are not yet mapped, that is, the number of data dependencies that are difficult to map (N _r ) is multiplied by C ₁ , the unit cost of routing, to calculate h (s).

On the other hand, if the number of data dependencies that are difficult to map is greater than the node that is not yet mapped, then the routing is resolved as far as possible (C ₁ N _i ) and the remainder is calculated as the cost of solving the additional interconnect (C ₁ N _i ). ₂ (N _f + | E0 | -N _i ) Sum these to calculate h (s).

Referring to FIG. 6A, in the present embodiment, a mesh reconfigured processor array structure of a 2 * 3 two-dimensional array consisting of six processing elements PE1, PE2, PE3, PE4, PE5, and PE6 is based on a reconfigured processor array. Use as a structure.

Referring to FIG. 6B, in this embodiment, four operations of 1, 2, 3, and 4 are input from the compiler and data dependencies of 1-> 3, 1-> 4, 2-> 3, and 3-> 4. The description is based on the assumption that 1 and 4 are classified into the first row and 2 and 3 into the second row according to the shared resource constraint.

In this case, one fork occurs due to the interconnection of 1-> 3 and 3-> 4, and there is no over-length edge. Therefore, h (s) is calculated as N _r (1) * C ₁ (1) = 1 until such fork is resolved through the addition of routing / interconnection, and after fork is resolved through the addition of routing / interconnection. Is calculated as 0.

6C, first, 1 is mapped to PE1 to PE3, which are the first processing elements, respectively (s = 1 to 3). Calculating g (s) and h (s) for each case, g (s) and h (s) are calculated to be 0 and 1, respectively, since both have not yet been resolved through routing / interconnection addition.

Since the calculated cost is the same in each case, it is assumed that 1 is mapped to PE1, and then 4, which is classified as the first row, is mapped to PE2 and PE3, the remaining processing elements of the first row, respectively. Calculate the cost according to (s = 4, 5).

In the case of mapping 4 to PE2 (s = 4), the data dependency with 1 previously mapped 1, 1-> 4, can be mapped to PE1-> PE2, which is a mesh-like interaction of the underlying reconfigured processor array structure. Since no additional incurring costs are incurred, g (4) is zero, and fork has not been resolved yet, so h (4) is one.

On the other hand, if 4 is mapped to PE3 (s = 5), then 1-> 4 must be mapped to 1 (PE1)->PE2-> 4 (PE3), in which case the unmapping has not yet been mapped. Since we need to route through the processing element PE2, the additional cost is incurred by C ₁ (1), so g (5) is 1, and fork has not been resolved yet, so h (5) is still 1.

Therefore, 2 and 3 are mapped to the second row PE4 to PE6 based on the case where 1 is a case where the additional generation cost is low and 4 is mapped to PE2.

First, when 2 is mapped to PE4 to PE6 (s = 6 to 8), there is no data dependency between 2 and the previously mapped operations 1 and 4, so compared to the previous step (s = 4), the additional cost There is no situation where fork or fork is resolved, so g (s) and h (s) maintain the same values as 0 and 1, respectively.

Thus, assuming that 2 is mapped to PE4 and 3 is mapped to PE5 (s = 9), then the data dependencies 1 and 2, 4 of 3 and the previously mapped operations 1-> 3, 2 -> 3, 3-> 4 are mapped to the underlying reconstructed processing array structure.

Referring to FIG. 6D, which illustrates the process in more detail, among the data dependencies to be mapped at this stage, 2-> 3, 3-> 4 map to the mesh-shaped interconnection of the underlying reconfigurable processor array structure. However, 1-> 3 cannot be mapped to the mesh-like interconnects of the underlying reconfigured processor array structure, and can also find processing elements that can route 1-> 3 data dependencies between 1 and 3. Thus, data dependencies of 1-> 3 can be solved by adding new interconnects to the underlying reconfigured processor array architecture. Therefore, the additional generation cost is generated by C ₂ (3) so that g (9) becomes 3, and thus fork is solved, so h (9) becomes zero.

In the case of mapping 2 to PE4 and 3 to PE5 (s = 10), data dependences of 3 and previously mapped operations 1, 2, and 4 are 1-> 3, 2-> 3, Map 3-> 4 to the underlying reconstructed processing array structure.

Referring to FIG. 6E, which illustrates the process in detail, data dependencies 1-> 3, 2-> 3, and 3-> 4, which are to be mapped at this stage, are all in the form of a mesh of a basic reconfigurable processor array structure. It cannot be mapped to the interconnect.

2-> 3 can be solved by routing connection (2 (PE4)-> PE5-> 3 (PE6)) through PE5, which is an unmapped processing element, and 3-> 4 also by PE3, which is also an unmapped processing element. This can be solved by routing connection (3 (PE6)-> PE3-> 4 (PE2)).

On the other hand, since 1-> 3 cannot find a processing element that can route between 1 and 3, 1-> 3 can be solved by adding new interconnects to the underlying reconfigured processor array structure.

Therefore, if 1 is mapped to PE1, 4 to PE2, 2 to PE4, and 3 to PE5 (s = 10), then the additional cost is C ₁ (1) + C ₁ (1) + C ₂ ( 3), so that g (10) = 5, and fork is solved accordingly, so h (10) becomes zero.

In the case of mapping 2 to PE5 and 3 to PE4 (s = 11), data dependencies of 3 and previously mapped operations 1, 2, and 4 are 1-> 3, 2-> 3, Map 3-> 4 to the underlying reconstructed processing array structure.

Referring to FIG. 6F, which illustrates the process in detail, among 1-> 3, 2-> 3, and 3-> 4 data dependencies to be mapped at this stage, 1-> 3, 2-> 3 While 3-> 4 may not be mapped to mesh-shaped interconnects of the underlying reconfigurable processor array structure, it may not be mapped.

In addition, since 3-> 4 cannot find any processing elements that can be routed between 3 and 4, 3-> 4 must be solved by adding new interconnects to the underlying reconfigured processor array structure, thus generating additional The cost is generated by C ₂ (3) so that g (11) = 3, so that fork is solved, so h (11) becomes zero.

In the case of mapping 2 to PE5 and 3 to PE6 (s = 12), data dependencies of 3 and previously mapped operations 1, 2, and 4 are 1-> 3, 2-> 3, Map 3-> 4 to the underlying reconstructed processing array structure.

Referring to Figure 6g, which illustrates the process in more detail, among the data dependencies 1-> 3, 2-> 3, 3-> 4 that should be mapped at this stage, 2-> 3 is the underlying reconfigurable processor array. 1-> 3, 3-> 4 cannot be mapped to mesh-shaped interconnects of the underlying reconfigurable processor array structure.

Of these, 3-> 4 can be solved by routing connections through PE3, a non-mapping processing element (3 (PE6)->PE3-> 4 (PE2)), but 1-> 3 can be routed between 1 and 3. Since processing elements are also not found, 1-> 3 must be solved by adding new interconnects to the underlying reconfigured processor array structure, thus causing additional costs incurred by C ₁ (1) + C ₂ (3). G (12) becomes four, and h (12) becomes zero.

If you map 2 to PE6 and 3 to PE4 (S = 13), then the data dependencies of 3 and the previously mapped operations 1, 2, and 4 are 1-> 3, 2-> 3, 3- Of the> 4, 1-> 3 can be mapped to mesh-shaped interconnects of the underlying reconfigured processor array structure, but 2-> 3 must be resolved by routing connections through PE5, an unmapped processing element. > 4 must be solved by adding new interconnects, resulting in an additional cost of C ₁ (1) + C ₂ (3), where g (13) is 4 and h (13) is 0 .

Finally, if 2 is mapped to PE6 and 3 to PE5 (s = 14), then data dependencies of 3 and the previously mapped operations 1, 2, and 4 are 1-> 3, 2-> 3. , 3-> 4 are mapped to the underlying reconfigurable processing array structure, which will be described below in detail with reference to FIG. 6H.

Of the data dependencies to be mapped at this stage, 1-> 3, 2-> 3, 3-> 4, 2-> 3, 3-> 4 will be mapped to the mesh-shaped interconnects of the underlying reconfigurable processor array structure. However, 1-> 3 must be resolved by routing connections (1 (PE1)->PE4-> 3 (PE5)) through the non-mapping processing element PE4, resulting in additional cost of C ₁ (1). G (14) becomes 1, and h (14) becomes 0.

As a result, according to the A-star search algorithm, since the graph form of the minimum cost is derived when s = 14, the mapping case corresponding to the A-star search algorithm may be selected.

That is, the mapping case selected will be a case of mapping 1, 4, 2, and 3 to PE1, PE2, PE5, and PE6, respectively, in which case there is no interconnect to be added to the basic reconfigurable processor array structure. do.

In the case of using the extended reconfigurable processor array structure generated according to the present embodiment, it is possible to use the reconfigurable processor array structures (for example, mesh, 1-hop, diagonal, mixed type) at a relatively low cost. Performance can be derived.

In particular, when searching for the interconnections to be added to the basic reconfigurable processor array structure by applying the method proposed in the present embodiment, it is possible to more easily generate the extended reconfigurable processor array structure.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and may be implemented in the form of a carrier wave (for example, transmission over the Internet) . In addition, the computer-readable recording medium may be distributed over network-connected computer systems so that computer readable codes can be stored and executed in a distributed manner. In addition, functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers of the technical field to which the present invention belongs.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, You will understand. Accordingly, the true scope of protection of the present invention should be determined only by the appended claims.

Claims (13)

Obtaining information about operations that constitute at least one or more applications compiled from a compiler and data dependencies indicative of data dependencies between the operations; And
Create an extended reconstruction processing array structure by adding interconnections between processing elements belonging to the base reconstruction processing array structure to a base reconstruction processing array structure based on the information about the obtained operations and data dependencies. A method for generating a reconfigurable processing array structure comprising a generating step. The method of claim 1,
And the basis reconstructed processing array structure is a structure of a two-dimensional array in which processing elements or more of the obtained number of operations are connected in a mesh network. The method of claim 1,
Deriving the number of processing elements required based on the obtained information about the operations and data dependencies, and selecting a base reconstructed processing array structure comprising at least the derived number of processing elements. Characterized in that the method for generating a reconfigurable processing array structure. The method of claim 1,
The generating step,
Mapping the processing elements and the interconnections between the processing elements and the obtained operations and data dependencies of the underlying reconstructed processing array structure to each other, A mapping case step of generating a mapping case adding an interconnect corresponding to data dependencies not corresponding to the interconnect;
A mapping case selecting step of selecting a mapping case having the smallest number of added interconnections among the generated mapping cases; And
Generating the extended reconfigured processing array structure based on the selected mapping case. 5. The method of claim 4,
The mapping case generation step,
Converting each of the processing elements belonging to the base reconstructed processing array structure into a VERTEX, and converting the interconnections between the processing elements into a first data structure in the form of a graph with EDGE;
Converting the obtained operation and data dependencies into a second data structure in the form of a graph with VERTEX and EDGE, respectively; And
Generating the mapping case by mapping the first data structure and the second data structure to each other. 5. The method of claim 4,
The mapping case generating step may include sharing information on the obtained operations and data dependencies, and a dedicated processing element allocated to each row of the basic reconstructed processing array structure in another processing element belonging to the same row. And classifying the obtained operations for each row of the two-dimensional array of the base reconstructed processing array structure based on the shared resource constraints defined by the data resource constraints. The method according to claim 6,
The dedicated processing element includes an arithmetic-logic unit (ALU) for arithmetic logic operations, a multiplier for multiplication operations, a floating point unit (FPU) for processing floating-point operations, and an LSU (for processing memory operations). and at least one or more of a load / store unit. The method according to claim 6,
The mapping case generation step,
Searching for operations each having a data dependency in relation to at least two or more of those belonging to the same row of the one-hop distance from the one based on the classified result; And
And further determining interconnects to add to the base reconstructed processing array structure based on data dependencies of the retrieved operations. 9. The method of claim 8,
The additional interconnection determination step,
Mapping data dependencies of the discovered operations to a routing interconnect routed through an unmapped processing element that is not mapped with operations obtained from the compiler;
Mapping a remaining data dependency of the searched operations that is not mapped to the routing interconnect to an interconnect to add to the underlying reconfigured processing array structure. Way. The method of claim 1,
The generating step,
The obtained operations are added to nodes of a tree structure, and the data dependencies between the operations added to the nodes are compared to the interconnects to be added as a result of comparing the interconnections between the processing elements of the basic reconstructed processing array structure. To perform the A * search, which calculates the minimum cost of additional costs incurred according to the additional costs incurred and the data dependencies not yet compared, and searches the graph form of the minimum cost by weighting their sums. step; And
Generating the extended reconstructed processing array structure based on the least cost graph form derived through the A-Star search. The method of claim 1,
When there are a plurality of applications to be executed, the compiler selects at least one or more applications from among the plurality of applications based on a predetermined priority with respect to the plurality of applications, and sequentially orders the selected at least one or more applications. Compiling a processor to provide information about operations that constitute the compiled applications and data dependencies indicating a data dependency relationship between the operations. . The method of claim 1,
And the base reconstructed processing array structure and the extended reconstructed processing array structure are structures of a coarse grained reconstructed array. A computer-readable recording medium containing a program comprising a function of generating a reconfigurable processing array structure, the method comprising:
Obtaining information about operations constituting at least one or more applications compiled from a compiler and data dependencies indicative of data dependencies between the operations; And
Create an extended reconstruction processing array structure by adding interconnections between processing elements belonging to the base reconstruction processing array structure to a base reconstruction processing array structure based on the information about the obtained operations and data dependencies. A computer-readable recording medium containing a program that includes a function to do so.

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