KR101255315B1 - Method For Fabricating Thin Film Transistor Array Substrate - Google Patents

Abstract

The present invention forms a gate insulating film and a protective film as a composite layer composed of a polymer substrate and nanoparticles, but by appropriately controlling the dielectric constant according to the type or content of nanoparticles, the performance as a gate insulating film and a protective film that requires different performances is satisfied. A method of manufacturing a TFT array substrate, the method comprising: forming a gate electrode on a substrate; Forming a gate insulating film having a dielectric constant of 6 to 10 and a structure in which nanoparticles are dispersed in a polymer substrate on the entire surface including the gate electrode; Forming a semiconductor layer on the gate insulating layer on the gate electrode; Forming source / drain electrodes on both sides of the semiconductor layer; Forming a protective film having a structure having a dielectric constant of 3 or less on a front surface of the source / drain electrode and having nanostructures dispersed in a polymer substrate; And forming a pixel electrode in contact with the drain electrode on the passivation layer.

Dielectric constant, gate insulating film, protective film

Description

Method for manufacturing TFT array substrate {Method For Fabricating Thin Film Transistor Array Substrate}

1 is a plan view of a TFT array substrate according to the prior art.

FIG. 2 is a cross-sectional view of the TFT array substrate on the line II ′ of FIG. 1. FIG.

3 is a cross-sectional view of a TFT array substrate according to the present invention.

4 is a graph showing the degree of change in permittivity of the composite layer according to the content of TiO ₂ .

* Explanation of symbols on the main parts of the drawings

111: substrate 112: gate wiring

112a: gate electrode 112b: storage electrode

113: gate insulating film 114: semiconductor layer

114a: ohmic contact layer 115: data wiring

115a: source electrode 115b: drain electrode

116: protective film 117: pixel electrode

150: first, second nanoparticles 151: first, second polymer substrate

160: third nanoparticle 161: third polymer substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a method of manufacturing a TFT array substrate for improving the performance of a TFT array substrate by designing materials differently according to performance required for each layer. .

BACKGROUND ART Liquid crystal display devices, which have recently been spotlighted as flat panel display devices, have been actively researched due to their high contrast ratio, suitable for gradation display or moving picture display, and low power consumption.

In particular, it can be manufactured with a thin thickness so that it can be used as an ultra-thin display device such as a wall-mounted TV in the future, and is light in weight and consumes significantly less power than a CRT CRT. It is being used as a next generation display device such as being used as a personal mobile phone terminal, a TV and an aviation monitor.

Such a liquid crystal display device generally includes a TFT array substrate having a thin film transistor, a pixel electrode, and a storage capacitor formed in each pixel region defined by a gate wiring and a data wiring, a color filter layer array substrate having a color filter layer and a common electrode formed thereon; It consists of a liquid crystal layer interposed between the two substrates, by applying a voltage to the electrode to rearrange the liquid crystal molecules of the liquid crystal layer to adjust the amount of light transmitted to display an image.

Hereinafter, a liquid crystal display device according to the related art will be described in detail with reference to the accompanying drawings. Hereinafter, the description will be limited to the TFT array substrate of the liquid crystal display device.

1 is a plan view of a TFT array substrate according to the prior art, and FIG. 2 is a cross-sectional view of the TFT array substrate on the line II ′ of FIG. 1.

First, as illustrated in FIGS. 1 and 2, the TFT array substrate 11 of the liquid crystal display device has the gate lines 12 arranged in a row and the data lines 15 vertically intersecting the gate lines 12. The unit pixel is defined by (), and the gate electrode 12a, the gate insulating layer 13, the semiconductor layer 14, the ohmic contact layer 14a, and the intersection point of the gate line 12 and the data line 15 are defined. A thin film transistor (TFT) stacked on the source / drain electrodes 15a and 15b to control the turn-on or turn-off of the voltage, and the pixel electrode 17 to apply a signal voltage to the liquid crystal layer to transmit light. And a storage capacitor for reducing the level-shift voltage and maintaining the pixel information during the non-selection period.

The storage capacitor Cst is formed on the same layer as the gate wiring 12 and is parallel to the gate wiring 12, the pixel electrode 17, the storage electrode 12b, and the pixel electrode 17. The gate insulating layer 13 and the passivation layer 16 interposed therebetween keep the charge charged in the liquid crystal during the turn-off period of the thin film transistor.

As illustrated in FIG. 1, the storage capacitor Cst may be formed in the middle of a unit pixel, but may be formed in the gate wiring by utilizing a predetermined region of the gate wiring as a capacitor electrode.

A gate insulating layer 13, which is an insulating layer, is further provided between the gate line 12 and the data line 15, and a passivation layer 16 is further provided between the thin film transistor and the pixel electrode.

The gate insulating layer 13 and the protective layer 16 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) having a dielectric constant of about 7.5, and typically, plasma enhanced chemical vapor deposition (PECVD). It forms by vapor deposition by the method.

However, when the gate insulating film and the protective film are formed by depositing the above inorganic materials, there are the following problems.

First, when the gate insulating film is formed of an inorganic material, even if the time is sufficiently long, the gate insulating film having a uniform thickness cannot be formed by only one deposition process. There was a downside. And, in the case of deposition equipment is expensive equipment has a problem that a lot of equipment management costs and investment costs are consumed. Accordingly, a technique of forming a gate insulating film using an organic material having a dielectric constant of 3 to 4, which can be easily formed using a relatively inexpensive equipment, has been proposed.

Unlike the inorganic gate insulating film, the organic gate insulating film is formed by a coating method such as spin coating or slit coating rather than a PECVD method, thereby making the manufacturing process easier and advantageous in terms of equipment cost. The surface can be planarized by removing the step difference between the gate wiring and the gate electrode.

However, the organic gate insulating layer has a smaller dielectric constant value compared with the inorganic gate insulating layer. If the dielectric constant is small, the parasitic capacitance Cgs formed between the gate wiring layer and the data wiring layer is reduced. In general, in the case of the opposite electrode and the insulating film provided therebetween, the capacitance value is proportional to the dielectric constant of the insulating film and the thickness of the insulating film, and is inversely proportional to the area of the opposite electrode.

As such, when the parasitic capacitance Cgs becomes small, the voltage drop ΔΔp increases further, as shown in Equation 1 below, thereby flickering, image sticking, and screen brightness. The uniformity of the block becomes poor.

In this case, Cgs is a parasitic capacitance formed between the TFT gate electrode and the source electrode (or drain electrode), Clc is an electrostatic capacitance accumulated in the liquid crystal cell, and Cst is a capacitance formed in the storage capacitor. ΔVp is the difference voltage between the data voltage Vd applied to the source electrode and the voltage Vlc charged to the liquid crystal cell, and ΔVg is the gate voltage Vgh of the low level and the gate voltage Vgl of the low level. Is the difference voltage.

That is, the parasitic capacitance Cgs is an item that most affects ΔVp as in Equation 1, and is closely related to the panel characteristics and the image quality characteristics. In this case, the parasitic capacitance Cgs may be increased to decrease ΔVp, and the dielectric constant of the gate insulating layer may be increased to increase the parasitic capacitance Cgs. Thus, the gate insulating layer may be formed of a material having a high dielectric constant. It would be desirable.

On the other hand, when the protective film was formed of an inorganic material, it was a cause of lowering the aperture ratio of the device.

Specifically, when the protective film is formed of an inorganic material having a dielectric constant of 6 to 8, there is a disadvantage in that parasitic capacitance (Cdp) is generated between the data line and the pixel electrode due to the high dielectric constant. The parasitic capacitance Cdp formed between the pixel electrode and the data line generates a source delay in which the data voltage level decreases, and generates a vertical crosstalk phenomenon in which the luminance change according to the source delay causes an image quality. It caused dropping.

Therefore, in order not to generate the parasitic capacitance Cdp, the data lines and the pixel electrodes are formed to be spaced apart by a predetermined interval so as not to overlap each other. As a result, the area of the pixel electrodes becomes small and the aperture ratio of the device becomes small.

Therefore, in order to form the pixel electrode to the maximum area and to improve the aperture ratio of the device, the pixel electrode should be formed to overlap the data line. Therefore, the smaller the dielectric constant value of the passivation layer, the better. Accordingly, a technique of forming a protective film from an organic material having a dielectric constant of 3 to 4 has been proposed.

However, unlike the inorganic protective film, the organic protective film is formed by a coating method such as spin coating or slit coating rather than a PECVD method, thereby making the manufacturing process easier and profitable in terms of equipment cost, and suppressing occurrence of parasitic capacitance (C). Although effective, but the thickness of the protective film has a limit in weight reduction.

For example, when the protective film is formed using inorganic materials such as silicon nitride (SiNx) and silicon oxide (SiOx) having a dielectric constant of about 6 to 8, the thickness is formed to have a thickness of 1500 to 5000Å, while the dielectric constant is about 3 to 4 When the protective film is formed using organic materials such as benzocyclobutene (BCB) and acrylic materials, the thickness is about 3 μm.

As described above, the TFT array substrate according to the related art as described above has the following problems.

First, the inorganic gate insulating film formed of silicon nitride has a problem that the deposition process such as PECVD is difficult and the cost of the deposition equipment is high, while the organic gate insulating film formed of poly glycol mono ethyl acetate (PGMEA) has a low dielectric constant. There was a problem that ΔVp was further increased.

In addition, in the case of the inorganic protective film formed of silicon nitride or the like, there is a problem in that the opening ratio of the device is lowered, and in the case of the organic protective film formed of BCB or the like, there is a problem in that the device is limited in weight and thickness.

As a result, it is preferable that the gate insulating film is formed of a material having a high permittivity and easy to process, and a protective film can be formed with a thin thickness and a material having a high dielectric constant, and the present invention achieves the above object. In particular, the present invention relates to a method of manufacturing a TFT array substrate in which a gate insulating film is formed of a high dielectric constant composite layer and a protective film is formed of a low dielectric constant composite layer.

In this case, the composite thin film used for the gate insulating film and the protective film is formed by mixing the polymer substrate and the nanoparticles, and controlling the dielectric constant of the insulating film by selecting and selecting the content ratio or type of the nanoparticles. It features.

The method of manufacturing a TFT array substrate of the present invention for achieving the above object is a step of forming a gate electrode on the substrate, the structure having a dielectric constant of 6 to 10 on the front surface including the gate electrode and nano particles dispersed in a polymer substrate Forming a first composite layer having a semiconductor layer, forming a semiconductor layer on the first composite layer above the gate electrode, and forming source / drain electrodes on both sides of the semiconductor layer, respectively. It is characterized by.

In addition, the method of manufacturing a TFT array substrate of the present invention for achieving another object of the present invention comprises the steps of forming a gate electrode on the substrate, the dielectric constant of the polymer substrate on the front surface including the gate electrode is 9 or more and the band gap Forming a first composite layer having a structure in which at least three first nanoparticles are dispersed, forming a semiconductor layer on the first composite layer above the gate electrode, and source / drain on both sides of the semiconductor layer It characterized in that it comprises a step of forming each electrode.

As such, the dielectric constant can be increased by forming the gate insulating film with the composite layer of the polymer substrate and the nanoparticles, as well as the coating process is not formed by the deposition process such as PECVD, so the process becomes easier and simpler.

In this case, forming a second composite layer having a structure having a dielectric constant of 3 or less on the entire surface including the source / drain electrodes and having a structure in which nanoparticles are dispersed in a polymer substrate, and contacting the drain electrode on the second composite layer. The electrode forming step may be further performed. The protective film may be formed of a composite layer of a polymer substrate and nanoparticles to reduce the dielectric constant, and may be formed by a coating process instead of a deposition process such as PECVD. It is easy and simple. In addition, since the dielectric constant of the protective film is low, it is possible to overlap the data wirings during the formation of the pixel electrode in a subsequent step. As a result, the area of the pixel electrode is increased, so that the aperture ratio of the device is improved.

That is, a composite layer having a structure in which nanoparticles are dispersed in a polymer substrate is formed as a gate insulating film or a protective film, and the dielectric constant is appropriately controlled according to the type or content of the nanoparticles and then applied, thereby serving as a gate insulating film and a protective film requiring different performances. It is characterized in that all of the performance is satisfied.

Hereinafter, a method of manufacturing a TFT array substrate of a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view of a TFT array substrate according to the present invention, and FIG. 4 is a graph showing the degree of change in permittivity of the composite layer depending on the content of TiO ₂ .

Referring to FIG. 3, first, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), and titanium (Ti) on the substrate 111 are described. , Low-resistance metals such as tantalum (Ta) and molybdenum-tungsten (MoW) are deposited by high-temperature sputtering, and then patterned by photolithography to form gate wiring (not shown), gate electrode 112a, and storage electrodes. To form 112b.

Thereafter, a first composite layer having a dielectric constant of 6 to 10 is coated on the entire surface including the gate electrode 112a to form a gate insulating layer 113. In this case, the first composite layer is formed by mixing the first polymer substrate 151 and the first nanoparticles 150, wherein the first nanoparticles 150 are dispersed on the first polymer substrate 151. Exists as. The dielectric constant of the first composite layer may be changed according to the type or content of the nanoparticles, and the dielectric constant of the gate insulating layer (first composite layer) may be 6 to 10 using the nanoparticles.

The first polymer substrate 151 is an organic polymer of polyphosphazene, polysiloxane, polysilane, polyacrylate, polyimide, and polyester. At least one selected from the group consisting of a polymer and an organic / inorganic hybrid polymer may be selected, and may be formed using a single polymer of a single type of monomer or a copolymer of different monomers. ) Can be used.

The second nanoparticles 150 may include barium strontium titanate, barium zirconate titanate, lead zirconate titanate, and lead lanthanum titanate. Lead lanthanum titanate, Strontium titanate, Barium titanate, Barium magnesium fluoride, Bismuth titanate, Strontium bismuth tantalate At least one selected from the group consisting of strontium bismuth tantalate, strontium bismuth tantalate niobate, and metal oxide materials may be used.

Here, the metal oxide-based material may be aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), calcium oxide (Calcium oxide, CaO), zirconium oxide (Zirconium oxide, ZrSiO ₄ or ZrO ₂ ), titanium Titanium oxide, TiO ₂ , Hafnium oxide, HfSiO ₄ or HfO ₂ , Yttrium oxide, Y ₂ O ₃ , Strontium oxide, SrO, Tantalum oxide, Ta ₂ O ₅ ), lanthanum oxide (Lanthanum oxide, La ₂ O ₃ ), barium oxide (Barium oxide, BaO) is at least one of the group consisting of.

In this case, in mixing the first polymer substrate and the first nanoparticles, the first nanoparticles may be dispersed on the first polymer substrate by simply stirring the physical force, but the The first nanoparticle may be dispersed on the first polymer substrate by chemical force, such as by reaction of a functional group provided at the terminal or side chain. Since the former method is likely to be separated from each other after being mixed, the latter method will be more preferable in consideration of stability and the like.

In this way, the dielectric constant can be increased by forming the gate insulating film with the first composite layer of the first polymer substrate and the first nanoparticles, and the coating process is easier and simpler than the deposition process such as PECVD. Become.

Meanwhile, in addition to forming a gate insulating film with a composite layer having a dielectric constant of 6 to 10 formed by mixing the first polymer substrate and the first nanoparticle, the second nanoparticle having a dielectric constant of 9 or more and a band gap of 3 or more is formed. It is also possible to form a second composite layer in which the mixture is mixed and use it as a gate insulating film. In this case, the first composite layer has a dielectric constant of 6 to 10, while the second composite layer has a difference in that the dielectric constant of the second nanoparticles is 9 or more and the band gap is 3 or more.

In this case, the second polymer substrate is an organic polymer of polyphosphazene, polysiloxane, polysilane, inorganic polymer, polyacrylate, polyimide, and polyester. And at least one selected from the group consisting of organic / inorganic hybrid polymers, and may be formed using a single polymer of a single type of monomer or a copolymer of different monomers. Forms can be used.

The second nanoparticles 150 may include aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), calcium oxide (CaO), zirconium oxide (ZrSiO ₄ ), or ZrO ₂ ), titanium oxide (TiO ₂ ), hafnium oxide (Hafnium oxide, HfSiO ₄ or HfO ₂ ), yttrium oxide (Y ₂ O ₃ ), strontium oxide (SrO), tantalum oxide (Tantalum oxide, Ta ₂ O ₅ ), lanthanum oxide (Lanthanum oxide, La ₂ O ₃ ), barium oxide (Barium oxide, BaO) may be used at least any one of the metal oxide-based material.

By forming a composite layer of the gate insulating film with a material having a band gap of 3 or more, the amount of current applied to the gate insulating film can be controlled to be sufficiently small. Since the band gap and the dielectric constant are inversely related to each other, the dielectric constant decreases as the band gap increases. Therefore, the selection of a metal oxide having a dielectric constant of at least 9 and a band gap of 3 or more is important for improving device performance.

In this case, even when the second polymer substrate and the second nanoparticles are mixed, the first nanoparticles may be dispersed on the first polymer substrate by a physical force of agitation. The first nanoparticle may be dispersed on the first polymer substrate by chemical force, such as by reaction of a functional group provided at the terminal or side chain. Since the former method is likely to be separated from each other after being mixed, the latter method will be more preferable in consideration of stability and the like.

In addition, the TFT characteristics such as I _ON and mobility are improved compared to the TFT-LCD using the inorganic gate insulating film by adjusting the interface with the semiconductor layer used and the band gap of the second composite layer (gate insulating film). Better device fabrication is also possible.

As described above, after the gate insulating film is formed of the first composite layer or the second composite layer, amorphous silicon (a-Si) is deposited on the entire surface including the gate insulating film to a thin thickness of 500 Å or less at a high temperature to form a semiconductor layer ( 114) and then implanting n-type impurities and depositing amorphous silicon (a-Si) at a thickness of about 300 to 700 Å at high temperature to form an n + a-Si ohmic contact layer. The a-Si deposition and the n + a-Si deposition are performed continuously in the same process chamber. Of course, they may be formed in separate process chambers, respectively.

Further, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) on the front surface including the ohmic contact layer 114a. Metal having low resistivity, such as molybdenum-tungsten (MoW), is deposited by high-temperature sputtering, and then patterned by photolithography to form data lines 115 and source / drain electrodes 115a and 115b.

As a result, gate wirings and data wirings defining pixels are perpendicularly intersected with each other, and the gate electrode 112a, the gate insulating film 113, the semiconductor layer 114, the ohmic contact layer 114a, and the intersection of the two wirings are formed. A thin film transistor TFT formed of the source / drain electrodes 115a and 115b is provided.

Subsequently, a protective film is formed on the entire surface including the thin film transistor. In this case, as in the related art, an organic material such as BCB (Benzocyclobutene), an acrylic material, or an inorganic material such as SiNx or SiOx may be used as the protective layer, but a third dielectric having a dielectric constant of 3 or less on the entire surface including the source / drain electrode It may be desirable to apply the composite layer to form the protective film 116.

In this case, the third composite layer is formed by mixing the third polymer substrate 161 and the third nanoparticles 160, similarly or similarly to the first composite layer, wherein the third nanoparticles 160 are formed of a third composite layer. 3 is present in a form dispersed on the polymer substrate 161. The dielectric constant of the third composite layer may be changed according to the type or content of the third nanoparticle, and the dielectric constant of the protective layer (third composite layer) may be 3 or less using this.

The third polymer substrate 161 is an organic polymer of polyphosphazene, polysiloxane, polysilane, polyacrylate, polyimide, and polyester. At least one selected from the group consisting of a polymer and an organic / inorganic hybrid polymer may be selected, and may be formed using a single polymer of a single type of monomer or a copolymer of different monomers. ) Can be used.

The third nanoparticles 160 may include barium strontium titanate, barium zirconate titanate, lead zirconate titanate, and lead lanthanum titanate. Lead lanthanum titanate, Strontium titanate, Barium titanate, Barium magnesium fluoride, Bismuth titanate, Strontium bismuth tantalate At least one selected from the group consisting of strontium bismuth tantalate, strontium bismuth tantalate niobate, and metal oxide materials may be used.

Here, the metal oxide-based material may be aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), calcium oxide (Calcium oxide, CaO), zirconium oxide (Zirconium oxide, ZrSiO ₄ or ZrO ₂ ), titanium Titanium oxide, TiO ₂ , Hafnium oxide, HfSiO ₄ or HfO ₂ , Yttrium oxide, Y ₂ O ₃ , Strontium oxide, SrO, Tantalum oxide, Ta ₂ O ₅ ), lanthanum oxide (Lanthanum oxide, La ₂ O ₃ ), barium oxide (Barium oxide, BaO) is at least one of the group consisting of.

At this time, in mixing the third polymer substrate and the third nanoparticles, the third nanoparticles may be dispersed on the third polymer substrate by a physical force of agitation, but the The third nanoparticle may be dispersed on the third polymer substrate by chemical force, such as by reaction of a functional group provided at the terminal or side chain. Since the former method is likely to be separated from each other after being mixed, the latter method will be more preferable in consideration of stability and the like.

As described above, the dielectric constant can be lowered by forming a protective film with the composite layer of the third polymer substrate and the third nanoparticle, and, as a result of the coating process, not formed by a deposition process such as PECVD, the process becomes easier and simpler. In addition, since the dielectric constant of the protective film is low, it is possible to overlap the data line 115 when forming the pixel electrode in a subsequent process. As a result, the area of the pixel electrode is increased, so that the aperture ratio of the device is improved.

As described above, after forming the passivation layer, the passivation layer 116 is removed to expose a portion of the drain electrode 115b to form a contact hole, and an ITO (Indium Tin) is formed on the entire surface of the passivation layer 116 including the contact hole. A transparent conductive material of oxide or indium zinc oxide (IZO) is deposited and patterned to form a pixel electrode 117 contacting the drain electrode 115b. In forming the pixel electrodes, the edges of the data lines are formed to overlap each other to ensure the maximum opening area in the unit pixel.

That is, the present invention provides a gate insulating film and a protective film as a composite layer composed of the same or similar materials, but by applying and controlling the dielectric constant appropriately according to the type or content of nanoparticles, thereby providing a different gate insulating film and a protective film. All of them can be satisfied.

For example, the first composite layer or the third composite layer may be formed by mixing a polysiloxane-based polymer substrate and nanoparticles of TiO _2. As shown in FIG. 4, the dielectric constant of the composite layer depends on the content of TiO ₂ . You can see this change.

In this case, the first composite layer used as the gate insulating film has to have a dielectric constant of 6 to 10, and thus, a polysiloxane-based polymer substrate may be formed by mixing 35 mol% or more of TiO ₂ , and the third composite layer used as the protective film has a dielectric constant of 3 or less. it may be formed by mixing a TiO ₂ of less than 10mol% in poly Roxanne silica-based polymer substrate. As such, the dielectric constant of the composite layer is characterized by the content of the nanoparticles and also depends on the type of nanoparticles.

Although not shown, the TFT array substrate formed as described above is provided with a liquid crystal layer between the two substrates that is oppositely bonded to the opposing substrate, and the opposing substrate includes a black matrix for preventing light leakage and an R, A color filter layer having G and B color resists formed in a predetermined order, an overcoat layer for protecting the color filter layer on the color filter layer and planarizing the surface of the color filter layer, and a pixel on a TFT array substrate formed on the overcoat layer In addition to the electrodes, a common electrode forming an electric field is formed.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The method of manufacturing a TFT array substrate of the present invention as described above has the following effects.

First, the dielectric constant can be increased by forming a gate insulating film with a composite layer of a polymer substrate and nanoparticles, and a coating process is formed without using a deposition process such as PECVD, thereby making the process easier and simpler.

Second, the dielectric constant can be lowered by forming a protective film with a composite layer of a polymer substrate and nanoparticles, and is formed by a coating process instead of a deposition process such as PECVD, thereby making the process easier and simpler. In addition, since the dielectric constant of the protective film is low, it is possible to overlap the data wirings during the formation of the pixel electrode in a subsequent step. As a result, the area of the pixel electrode is increased, so that the aperture ratio of the device is improved.

Third, the gate insulating film and the protective film are formed of a composite layer composed of the same or similar materials, but by appropriately controlling the dielectric constant according to the type or content of the nanoparticles and applying the same, the performances of the gate insulating film and the protective film are different. Are satisfied.

Claims (23)

Forming a gate electrode on the substrate; Forming a gate insulating film having a dielectric constant of 6 to 10 and a structure in which nanoparticles are dispersed in a polymer substrate on the entire surface including the gate electrode; Forming a semiconductor layer on the gate insulating layer on the gate electrode; Forming source / drain electrodes on both sides of the semiconductor layer; Forming a protective film having a structure having a dielectric constant of 3 or less on a front surface of the source / drain electrode and having nanostructures dispersed in a polymer substrate; And And forming a pixel electrode in contact with the drain electrode on the passivation layer. The method of claim 1, And the gate insulating film has a structure in which nanoparticles of TiO ₂ are dispersed in a polysiloxane-based polymer substrate. The method of claim 2, And the gate insulating film is formed by mixing 35 mol% or more of TiO ₂ with a polysiloxane-based polymer substrate. delete The method of claim 1, A method of manufacturing a TFT array substrate, characterized in that the dielectric constant of the gate insulating film and the protective film varies according to the content or type of the nanoparticles. The method of claim 1, The polymer substrate may be an organic polymer of polyphosphazene, polysiloxane, polysilane, inorganic polymer of polysilane, polyacrylate, polyimide, polyester, and organic / inorganic materials. A method of manufacturing a TFT array substrate, characterized in that at least one selected from the group consisting of a hybrid polymer is used. The method of claim 6,  The method of manufacturing a TFT array substrate, characterized in that the polymer substrate is a single polymer or a copolymer (Copolymer). The method of claim 1, The nanoparticles are barium strontium titanate, barium zirconate titanate, lead zirconate titanate, lead lanthanum titanate, Strontium titanate, Barium titanate, Barium magnesium fluoride, Bismuth titanate, Strontium bismuth tantalate, Strontium A method for manufacturing a TFT array substrate, characterized in that at least one selected from the group consisting of titanium bismuth tanalate niobate and a metal oxide-based material is used. 9. The method of claim 8, The metal oxide-based material is composed of Al ₂ O ₃ , MgO, CaO, ZrSiO ₄ , HfSiO ₄ , Y ₂ O ₃ , ZrO ₂ , HfO ₂ , SrO, La ₂ O ₃ , Ta ₂ O ₅ , BaO, TiO ₂ At least one of the group, the manufacturing method of the TFT array substrate. The method of claim 1, And the gate insulating film or the protective film has a structure in which nanoparticles of TiO ₂ are dispersed in a polysiloxane-based polymer substrate. 11. The method of claim 10, Wherein the gate insulating film is formed by mixing 35 mol% or more of TiO ₂ with a polysiloxane-based polymer substrate, and the protective film is formed by mixing 10 mol% or less of TiO ₂ . The method of claim 1, In the step of forming the gate electrode, the gate wiring is formed at the same time, And in the step of forming the source / drain electrodes, simultaneously forming data lines perpendicular to the gate lines. The method of claim 1, And the gate insulating film and the protective film are formed by a coating method. Forming a gate electrode on the substrate; Forming a gate insulating film having a structure in which a first nanoparticle having a dielectric constant of 9 or more and a bandgap of 3 or more is dispersed on a polymer substrate on the entire surface including the gate electrode; Forming a semiconductor layer on the gate insulating layer on the gate electrode; Forming source / drain electrodes on both sides of the semiconductor layer; Forming a protective film having a structure in which second nanoparticles are dispersed in a polymer substrate on the entire surface including the source / drain electrodes; And And forming a pixel electrode in contact with the drain electrode on the passivation layer. 15. The method of claim 14, The first nanoparticles are composed of Al ₂ O ₃ , MgO, CaO, ZrSiO ₄ , HfSiO ₄ , Y ₂ O ₃ , ZrO ₂ , HfO ₂ , SrO, La ₂ O ₃ , Ta ₂ O ₅ , BaO, TiO ₂ At least one of the group of the manufacturing method of the TFT array substrate characterized in that. delete 15. The method of claim 14, The second nanoparticles are barium strontium titanate, barium zirconate titanate, lead zirconate titanate, lead lanthanum titanate ), Strontium titanate, Barium titanate, Barium magnesium fluoride, Bismuth titanate, Strontium bismuth tantalate, A method of manufacturing a TFT array substrate, characterized in that at least one selected from the group consisting of strontium bismuth tanalate niobate and a metal oxide-based material is used. The method of claim 17, The metal oxide-based material is composed of Al ₂ O ₃ , MgO, CaO, ZrSiO ₄ , HfSiO ₄ , Y ₂ O ₃ , ZrO ₂ , HfO ₂ , SrO, La ₂ O ₃ , Ta ₂ O ₅ , BaO, TiO ₂ At least one of the group, the manufacturing method of the TFT array substrate. 15. The method of claim 14, A method of manufacturing a TFT array substrate, characterized in that the dielectric constants of the gate insulating film and the protective film vary according to the content or type of the first and second nanoparticles. 15. The method of claim 14, The polymer substrate may be an organic polymer of polyphosphazene, polysiloxane, polysilane, inorganic polymer of polysilane, polyacrylate, polyimide, polyester, and organic / inorganic materials. A method of manufacturing a TFT array substrate, characterized in that at least one selected from the group consisting of a hybrid polymer is used. 21. The method of claim 20, The method of manufacturing a TFT array substrate, characterized in that the polymer substrate is a single polymer or a copolymer (Copolymer). 15. The method of claim 14, In the step of forming the gate electrode, the gate wiring is formed at the same time, And in the step of forming the source / drain electrodes, simultaneously forming data lines perpendicular to the gate lines. 15. The method of claim 14, And the gate insulating film and the protective film are formed by a coating method.

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