KR101252999B1 - Multilayer printed circuit board with interstitial via hole structure for reduced parastic capacitances - Google Patents

Abstract

PURPOSE: A multilayer printed circuit board with an interstitial via structure with reduced parasitic capacitance is provided to enable a user to easily design a substrate by using an interstitial via hole. CONSTITUTION: A via plating body(110) includes a top pad and a bottom pad. A first metal plate(120) is parallel to one of the top pad and the bottom pad and includes a hole in a normal direction to one of the top pad and the bottom pad. A first dielectric(130) is arranged between the first metal plate and one of the top pad and the bottom pad. A strip line(140) is horizontally connected to one of the top pad and the bottom pad.

Description

MULTILAYER PRINTED CIRCUIT BOARD WITH INTERSTITIAL VIA HOLE STRUCTURE FOR REDUCED PARASTIC CAPACITANCES

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to printed circuit boards and, more particularly, to multilayer printed circuit boards having an inner layer via structure with reduced parasitic capacitance.

Recently, as electronic products are becoming smaller, slimmer, and denser, printed circuit boards (PCBs) are also being miniaturized and slimmed at the same time. In addition, due to the increased portability of electronic devices, the design of printed circuit boards is complicated due to the multi-function, high-capacity data transmission and the like, and requires a high level of technology.

The printed circuit board includes a single-sided PCB in which wiring is formed only on one side of the insulated substrate, a double-sided PCB in which wiring is formed on both sides, and a multilayer printed circuit board (MLB) that is wired in multiple layers. In the past, component devices are simple and circuit patterns are simple, and single-sided PCBs are mainly used. However, in recent years, due to complicated circuits and increased demand for high density and miniaturized circuits, it is common to use double-sided PCBs or multilayer printed circuit boards.

In multilayer printed circuit boards, vias are used to connect different layers. Such vias are largely divided into through-hole vias (THVs) and interstitial via holes (IVHs). Through-type vias are vias formed through a printed circuit board for electrical connection between different layers of the substrate. Inner layer vias are electrically connected to the inner layer at the surface layer or the inner layer at the inner layer without penetrating the printed circuit board. Refers to vias formed to electrically connect the

In terms of signal transmission, vias can be a factor that limits the propagation of high frequency signals or degrades signal integrity (SI) due to impedance mismatches due to structural discontinuities in the signal connection path. In particular, in a small multilayer printed circuit board, excess parasitic capacitance occurring between a via-in-pad connected to the top and bottom of an interstitial via hole and a metal layer above or below the pads. Capacitance) increases as the thickness of the insulating substrate is thin and the dielectric constant is high. As the size of the surplus parasitic capacitance increases, crosstalk of the signal due to impedance mismatch between the inner via and the signal line increases, so that a proper design of the via and the metal layer is required for the SI design.

An object of the present invention is to provide a printed circuit board having a structure in which the parasitic capacitance of the inner layer via is reduced for impedance matching when transmitting a high frequency signal using an interstitial via hole.

According to an embodiment of the present invention to achieve the above object, a via plating body having a body, an upper pad formed in connection with the upper portion of the body, and a lower pad formed in connection with the lower portion of the body; A first metal plate formed parallel to and spaced apart from at least one of the upper pad and the lower pad, and having holes formed in at least a portion of an area in which at least one of the upper pad and the lower pad is projected in a normal direction; And an inner layer via structure having reduced parasitic capacitance comprising a first dielectric disposed between at least one of the upper pad and the lower pad and the first metal plate.

The printed circuit board according to the embodiment of the present invention can reduce the parasitic capacitance generated between the via platen and the metal plate.

According to one embodiment of the present invention, by forming a hole in a metal plate formed parallel to the pad provided in the via, it is possible to reduce the parasitic capacitance generated between the via plater and the metal plate.

1 is a cross-sectional view of a multilayer printed circuit board having an inner layer via structure with reduced parasitic capacitance associated with one embodiment of the present invention.
2 is a perspective view of a multilayer printed circuit board having an inner layer via structure with reduced parasitic capacitance associated with one embodiment of the present invention.
FIG. 3 is a graph illustrating a change in capacitance according to a radius of a hole and a thickness of a dielectric formed in a first metal plate of a multilayer printed circuit board having an inner layer via structure having a reduced parasitic capacitance shown in FIG. 2.
4 is a graph illustrating a change in reflection coefficient according to a radius of a hole formed in a first metal plate of a multilayer printed circuit board having an inner layer via structure having a reduced parasitic capacitance shown in FIG. 2.

Hereinafter, a printed circuit board related to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, the terms used in the present specification will be briefly described, and the present invention will be described in detail.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. Also, in certain cases, there may be a term selected arbitrarily by the applicant, in which case the meaning thereof will be described in detail in the description of the corresponding invention. Therefore, the terms used in the present invention should be defined based on the meanings of the terms and the contents throughout the present invention, rather than the names of the simple terms.

Via in the present specification means a plated hole plated with a metal formed in the inner layer for electrical connection between the inner layer or the inner layer in the surface layer without penetrating the printed circuit board. . Vias may be implemented in the form of blind vias that electrically connect the surface and inner layers of the multilayer printed circuit board, and buried vias for electrical connection between the inner layers of the multilayer printed circuit board. Can be.

In the present specification, a buried via is described as an example, but the present invention is not limited thereto.

In addition, the term "via plated body" herein means a plated body on which a via is formed.

In addition, the dielectric refers to a material that, when an electric field or a voltage is applied to both ends, charges of different polarities are induced on both surfaces to generate a displacement current, but a conduction current is blocked. .

When applying an electrostatic field may refer to a material that generates an electric polarization but no direct current.

In the present specification, the parasitic capacitance refers to an unwanted capacitance inevitably existing inside an electronic component or a circuit such as an inductor, a diode, a transistor, and the like. There is always a capacitance between two conductors spaced apart in a high frequency circuit, and this unwanted parasitic capacitance component is one of the factors that makes the function of an electronic device or circuit impossible to function ideally.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

1 is a parasitic capacitance associated with one embodiment of the present invention is reduced FIG. 2 is a cross-sectional view of a multilayer printed circuit board having an inner layer via structure, and FIG. 2 shows reduced parasitic capacitance associated with one embodiment of the present invention. A perspective view of a multilayer printed circuit board having an inner layer via structure.

As shown, parasitic capacitance is reduced The multilayer printed circuit board 100 having an inner layer via structure may include a via plating body 110, a plurality of metal plates 120 and 150, a plurality of dielectrics 130 and 160, a strip line 140, and the like. .

The metal plate 120 positioned outside the via plater 100 on the upper portion of the metal plates 120 and 150 is referred to as a 'first metal plate' for convenience, and the metal plate 150 existing inside is referred to as a 'second metal plate'. do. In addition, the dielectric 130 existing outside is referred to as a "first dielectric," and the dielectric 160 existing inside is referred to as a "second dielectric."

The number of metal plates and the number of dielectrics described in the present embodiment are only examples, and it is natural that the present invention may be modified according to embodiments of the present invention.

The via plating body 110 may include a body 111, an upper pad 112, and a lower pad 113. The body 111 may be formed in a pillar shape. Hereinafter, the body 111 will be described by way of example in the form of a cylinder.

A hole (not shown) may be formed in the body 111. Inside the body 111, conductors existing in each metal layer may be connected through holes (not shown).

An upper pad 112 may be formed at an upper portion of the body 111, and a lower pad 113 may be formed at a lower portion of the body 111. The upper pad 112 and the lower pad 113 may be vertically connected to the direction in which the body 111 is formed.

The upper pad 112 or the lower pad 113 may be connected to the strip line 140 in a horizontal direction. In addition, the strip line 140 may be used for electrical connection between terminals.

The first metal plate 120 may be formed in parallel with and spaced apart from the upper pad 112 or the lower pad 113. In the present embodiment, the first metal plate 120 has two examples. A hole 121 is formed in the first metal plate 120. The hole 121 formed in the first metal plate 120 may be formed to include at least a portion of an area in which the upper pad 112 or the lower pad 113 is projected onto the first metal plate 120 in a normal direction. . As the upper pad 112 or the lower pad 113 includes more regions projected in the normal direction to the first metal plate 120, the upper pad 112 or the lower pad 113 and the first metal plate 120 are included. The parasitic capacitance occurring between) may be further reduced.

For example, the holes 121 formed in the first metal plate 120 may include all regions in which the upper pad 112 or the lower pad 113 is projected on the first metal plate 120 in a normal direction.

The first dielectric 130 may be inserted between the metal layer on which the upper pad 112 or the lower pad 113 is formed and the first metal plate 120.

In addition, the second metal plate 150 may be formed between the upper pad 112 and the lower pad 113. The second metal plate 150 may have a hole 151 formed therein to allow the body 111 to pass therethrough. The parasitic capacitance generated between the upper pad 112 or the lower pad 113 and the second metal plate 150 may be reduced through the hole 151 formed in the second metal plate 150. The hole 151 formed in the second metal plate 150 may be formed to include at least a portion of the region in which the upper pad 112 or the lower pad 113 is projected on the second metal plate 150 in a normal direction. As the upper pad 112 or the lower pad 113 includes more regions projected in the normal direction to the second metal plate 150, the upper pad 112 or the lower pad 113 and the second metal plate 150 are included. The parasitic capacitance occurring between) may be further reduced.

For example, the holes 151 formed in the second metal plate 150 may include all regions in which the upper pad 112 or the lower pad 113 is projected on the second metal plate 150 in the normal direction.

The second dielectric 160 may be inserted between the metal layer on which the upper pad 112 or the lower pad 113 is formed and the second metal plate 150.

Meanwhile, according to one embodiment of the present invention, an area in which the hole 121 formed in the first metal plate 120 is projected in the normal direction on the upper pad 112 or the lower pad 113 is projected on the second metal plate 150. The parasitic capacitance generated between the upper pad 112 or the lower pad 113 and the first metal plate 120 may vary according to the degree of inclusion and the thickness of the first dielectric 130.

The plan view of the hole 121 upper pad 112 and the lower pad 113 formed in the first metal plate 120 is circular, and the centers of the hole 121, the upper pad 112, and the lower pad 113 are all formed. In the same case, the degree of inclusion of the region in which the upper pad 112 or the lower pad 113 is projected in the normal direction on the second metal plate 150 may be represented by the radius of the hole 121. That is, as the radius of the hole 121 is larger, the upper pad 112 or lower pad 113 may have a greater degree of inclusion of a region projected in the normal direction to the second metal plate 150.

FIG. 3 shows the reduced parasitic capacitance shown in FIG. It is a graph showing the change of parasitic capacitance according to the radius of the hole and the thickness of the dielectric formed in the first metal plate of the multilayer printed circuit board having the inner layer via structure. That is, FIG. 3 illustrates a change in parasitic capacitance occurring between the upper pad 112 or the lower pad 113 and the first metal plate 120 according to the thickness of the first dielectric 130 and the radius of the hole 121. It is a graph. The thickness of the first dielectric 130 is expressed as 'h'.

As shown, it can be seen that the smaller the thickness of the dielectric material, the larger the parasitic capacitance reduction width according to the increase in the radius of the hole 121. When the dielectric thickness is small, the parasitic capacitance (Cvap) generated between the upper pad 112 or the lower pad 113 and the first metal plate 120 has different parasitic capacitances (for example, Cb (between the body and the second metal plate). Since the parasitic capacitance) is relatively larger), the capacitance reduction width may increase due to the increase in the radius of the hole 121. When the thickness of the first dielectric 130 is 50 um, 75 um, 100 um, or 150 um, the capacitance variation ranges are 30 fF, 16.9 fF, 11.1 fF, and 5.3 fF, respectively. When the radius of the hole 121 is greater than about 140 um, the larger the thickness of the dielectric material, the larger the parasitic capacitance value is. The reason is that the length of the body 111 increases with the increase in the thickness of the dielectric body. This is because the capacitance existing between 150 has increased.

Meanwhile, according to the exemplary embodiment of the present invention, the reflection coefficient S ₁₁ may be changed according to the radius of the hole 121 formed in the first metal plate 120.

FIG. 4 shows the reduced parasitic capacitance shown in FIG. It is a graph which shows the change of a reflection coefficient according to the radius of the hole formed in the 1st metal plate of the multilayer printed circuit board which has an inner layer via structure.

 As shown, as the radius of the hole 121 formed in the first metal plate 120 increases, it can be seen that the reflection of the signal due to buried vias formed in the via plating body 110 decreases. In the WLAN bands 2.5 GHz and 5 GHz, the radius of the hole 121 was 160 um, and the magnitude of the return loss was reduced by about 5 dB compared to the case without the hole 121.

As described above, the printed circuit board according to the exemplary embodiment of the present invention forms a hole in a metal plate formed in an area facing the upper pad 112 or the lower pad 113, thereby preventing parasitic capacitance caused by the metal plate and vias. Can be reduced.

The above-described printed circuit board is not limited to the configuration and method of the embodiments described above, the embodiments are configured by selectively combining all or part of each embodiment so that various modifications can be made May be

100: printed circuit board
110: via plated body
111: Body
112: upper pad
113: lower pad
120: first metal plate
130: first dielectric
140: strip line
150: second metal plate
160: second dielectric

Claims (7)

A via plating body having a body, an upper pad formed in connection with an upper portion of the body, and a lower pad formed in connection with a lower portion of the body;
A first metal plate formed parallel to and spaced apart from at least one of the upper pad and the lower pad, and having holes formed in at least a portion of an area in which at least one of the upper pad and the lower pad is projected in a normal direction; And
Parasitic capacitance is reduced, characterized in that it comprises a first dielectric disposed between at least one of the upper pad and the lower pad and the first metal plate. Multilayer printed circuit board having an inner layer via structure. The method of claim 1, wherein the printed circuit board
The parasitic capacitance-reducing inner layer further comprises a strip line connected in a horizontal direction with at least one of the upper pad and the lower pad. Multilayer printed circuit board having a via structure. The method of claim 1, wherein the body is
Reduced parasitic capacitance, characterized in that the hole is formed inside Multilayer printed circuit board having an inner layer via structure. The method of claim 1, wherein the via plated body is
A multilayer printed circuit board having an inner layer via structure with reduced parasitic capacitance, which is implemented in a buried via form. The method of claim 1, wherein the hole formed in the first metal plate
And an inner layer via structure having reduced parasitic capacitance, wherein at least one of the upper pad and the lower pad includes a region projected in a normal direction. The method of claim 1, wherein the printed circuit board
A second metal plate formed between the upper pad and the lower pad; And
Further comprising a second dielectric disposed between at least one of the upper pad and the lower pad and the second metal plate,
The second metal plate has a multilayer printed circuit board having an inner layer via structure with reduced parasitic capacitance, characterized in that a hole is formed so that the body penetrates. The method of claim 6, wherein the hole formed in the second metal plate
The hole formed in the first metal plate has a multi-layer printed circuit board having a parasitic capacitance-reduced inner layer via structure, characterized in that formed so as to include all of the region in which at least one of the upper pad and the lower pad is projected in the normal direction.

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