KR101243759B1 - Virtual lane identification method and apparatus for applying virtual lane scheme to optical transport network - Google Patents

Abstract

The present invention relates to a virtual lane recognition method and apparatus for applying a virtual lane technique to an optical transport network. More specifically, in applying the virtual lane technique of Ethernet to the ultra-high speed OTN signal, especially OTU4 (100G), by periodically changing the rotation direction of the virtual lane, the MFAS signal is received at the receiver without modifying the frame of the existing optical network signal. It relates to a technique for recognizing a virtual lane using.

Virtual Lane Recognition, Virtual Lane Technique, Optical Transport Network

Description

Virtual Lane Recognition Method and Apparatus for Applying Virtual Rain Technique to Optical Transport Networks {VIRTUAL LANE IDENTIFICATION METHOD AND APPARATUS FOR APPLYING VIRTUAL LANE SCHEME TO OPTICAL TRANSPORT NETWORK}

The present invention relates to a virtual lane recognition method and apparatus for applying a virtual lane technique to an optical transport network. More specifically, in applying the virtual lane technique of Ethernet to the ultra-high speed OTN signal, especially OTU4 (100G), by periodically changing the rotation direction of the virtual lane, the MFAS signal is received at the receiver without modifying the frame of the existing optical network signal. It relates to a technique for recognizing a virtual lane using.

The present invention is derived from the research conducted as part of the IT growth engine technology development project of the Ministry of Knowledge Economy and the Ministry of Information and Communication Research and Development. [Task management number: 2008-S-009-01, Task name: Packet-optical integrated switch technology ].

Recently, attempts are being made to converge Ethernet and optical transport networks, and in particular, a discussion for applying a virtual lane technique standardized in IEEE P802.3ba to an optical transport network is underway.

In order to apply the Ethernet virtual lane technique to the high speed optical transmission network signals (OTU3, OTU4), first, the time difference (skew) between each lane during transmission must be measured at the receiver, and second, the virtual lane at the receiver It should be distinguishable. In other words, the receiver should be able to recognize and reassemble each virtual lane in the correct order. Various methods have been proposed for this purpose.

First, there is a method of distributing the frame alignment signal bit by bit to each virtual lane and inverting the odd pairs of the frame alignment signal. However, this method is applicable only to OTU3 and does not consider OTU4 at all.

Secondly, the frame of the OTU is distributed to each virtual lane in units of 8 bytes, and the framing block corresponding to the first 8 bytes of the start point of each frame is moved backward by 8 bytes. In the case of the OTU3 frame, the OTU3 frame is modified such that the framing block is located at the same position every four frames, and thus the framing blocks are equally distributed among the four virtual lanes. On the other hand, since the virtual lane cannot be distinguished using only the frame alignment signal in this method, a signal of 1 byte called a multi frame alignment signal (MFAS) is positioned immediately after the frame alignment signal and used as the virtual lane ID. However, this method requires modifying the OTUk frame itself by shifting the framing block by 8 bytes, which requires significant modifications to the OTUk framer device, and furthermore, it is not applicable to OTU4.

Third, the above-described second method is improved. In this case, the OTU frame is distributed to each virtual lane in units of 8 bytes, and after distribution of one frame, the next frame is distributed by pushing the virtual lanes one by one. However, this method also uses MFAS as a virtual lane ID in OTU3, but there is a problem in that virtual lanes cannot be distinguished only by MFAS in OTU4.

Furthermore, in order to overcome the problem of the third method, a method of overwriting the VL ID information on the last 1 byte of the 6 byte of the frame alignment signal has been proposed. In other words, the VL ID, which is separate information for identifying the virtual lane other than the MFAS, is generated and added to the frame before the frame is distributed to the virtual lane. However, even with this method, it is necessary to modify an OTUk frame to add a VL ID to the frame, and to overwrite a part of the frame alignment signal to add the VL ID.

Accordingly, the present invention is to solve the above problems of the prior art, the existing optical transmission network by periodically changing the rotation direction of the virtual lane in the application of the Ethernet virtual lane technique to the ultra-high speed OTN signal, especially OTU4 (100G) Disclosed is a method and apparatus for recognizing a virtual lane that enables a receiver to recognize a virtual lane using an MFAS signal without modifying a frame of the signal.

According to an aspect of the present invention, there is provided a virtual lane recognition method, comprising: checking a detection period of a frame alignment signal (FAS) included in an input signal by receiving a signal in a predetermined unit; If the detection period of the FAS is constant or has a specific pattern, checking whether the detection period and the MFAS value included in the input signal are normal; Performing recognition and alignment of virtual lanes when the detection period and the MFAS value are normal; And reassembling each virtual lane having completed recognition and alignment to output a frame of a circular optical transmission network signal.

On the other hand, if the detection period of the FAS is not constant and does not have a specific pattern, further comprising the step of generating an error alarm, if the detection period or MFAS value is abnormal, further comprising the step of generating an error alarm. .

In the performing of the virtual lane recognition and sorting, the virtual lane is aligned using the FAS and the virtual lane is recognized by referring to a lane recognition table using a set of MFAS values.

According to another aspect of the present invention, there is provided a transmitting-side virtual lane recognition apparatus, comprising: a framer in charge of frame formation of an optical transmission network signal and processing of the optical transmission network signal; A frame decomposition apparatus for decomposing the frame into a predetermined size so that a frame alignment signal (FAS) and a multi-frame alignment signal (MFAS) of the frame to be transmitted received from the framer are included in one block; And a lane recognizing rotating device that distributes the frame block decomposed by the frame decomposing device to the plurality of virtual lanes in a round-robin manner while periodically changing the rotation direction of the virtual lane.

Preferably, the frame decomposition apparatus decomposes the frame such that the size of one frame block is 8N (N = 1, 2, ... 102) bytes.

In addition, the lane recognition rotary device, the frame block disassembled in the frame decomposition device in a round-robin manner to distribute a plurality of virtual lanes, and when the distribution is completed for one frame forward rotation device or reverse rotation device A frame distribution device configured to rotate the virtual lane by one lane and then perform distribution for the next frame; A forward rotation device configured to rotate the virtual lane in a forward direction according to the control of the frame distribution device; And a reverse rotation device configured to rotate the virtual lane in the reverse direction under the control of the frame distribution device.

In this case, the frame distribution apparatus is rotated once for the entire virtual lane, the number of framing blocks including the FAS and MFAS is distributed to the entire virtual lane,

(Total number of virtual lanes) ≤ 2 ^N (N is an integer) ≤ 2 ⁸

The rotation period of the virtual lane is determined to satisfy the condition of.

Specifically, when the number of virtual lanes is 20, the frame rotation apparatus operates the forward rotation apparatus three times and then operates the reverse rotation apparatus once, and operates the forward rotation apparatus four times and then the reverse rotation apparatus. Is operated one time, the forward rotation device is operated four times and the reverse rotation device is operated once, the forward rotation device is operated four times, and then the reverse rotation device is operated once, and the forward rotation device is operated. After operating four times, the reverse rotation device is operated once, the forward rotation device is operated four times, then the reverse rotation device is operated once, and the forward rotation device is operated three times.

On the other hand, the reception side virtual lane recognition apparatus according to another aspect of the present invention for achieving the above object, aligns the virtual lane by using the frame alignment signal (FAS) for each of the plurality of received virtual lanes and MFAS ( A lane recognizing apparatus for distinguishing virtual lanes using a set of Multi-Frame Alignment Signal) values; A virtual lane reassembly device for reassembling a frame of a circular optical transmission network signal from all virtual lanes in which lane alignment and recognition are completed by the lane recognizing device; And a framer that receives a frame reassembled by the virtual lane reassembly device and is in charge of signal processing, wherein the lane recognizing device detects the FAS for each of the plurality of virtual lanes and detects the FAS. A lane recognition processor for transmitting a virtual lane having a constant detection period to the first lane recognizing apparatus and transmitting a virtual lane having a predetermined detection period to the second lane recognizing apparatus; A first lane recognizing apparatus that receives a virtual lane having a constant FAS detection period from the lane recognizing processor, identifies a virtual lane by referring to a lane recognition table using a set of MFAS values, and performs lane alignment using the FAS; And a second lane recognition for receiving a virtual lane having a predetermined FAS detection period from the lane recognition processor to distinguish the virtual lanes by referring to a lane recognition table using a set of MFAS values, and performing lane alignment using the FAS. Device.

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According to the present invention, the virtual lane can be recognized and aligned at the receiver using the MFAS signal without modifying the standard frame of the ultra-fast OTUk.

Therefore, virtual lane recognition is possible only by adding a simple circuit for changing the rotation direction of the virtual lane to the conventional OTUk framer and the Ethernet transmission / reception module, thereby increasing the compatibility and economical efficiency of the ultra-high speed optical transmission network and Ethernet.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. In the following detailed description of the preferred embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In the drawings, like reference numerals are used throughout the drawings.

In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . Also, to "include" an element means that it may include other elements, rather than excluding other elements, unless specifically stated otherwise.

The present invention is to effectively recognize the virtual lane when the Ethernet virtual lane technique is applied to OTU4 (100G), particularly among the ultra-high speed OTN signal. 100GbE standardizes parallel transmission through 20 virtual lanes, and OTU4 (100G) is proceeding standardization in the direction of inheriting most of the frame structure of the conventional OTU1-3. Therefore, the present invention focuses on the case of transmitting OTU4 through 20 virtual lanes.

First, prior to describing the present invention, the structure of the OTUk frame, the concept of the virtual lane technique, and other background technologies will be described in detail to help the present invention.

1 is a structural diagram of an OTUk (k = 1, 2, 3) frame standardized in ITU-T Recommendation G.709. Here, the k value represents the transmission speed of the signal, which means 2.5G when k = 1, 10G when k = 2, and 40G when k = 3. The structure of the OTUk frame is as shown in FIG. 1 regardless of the k value.

As shown in FIG. 1, an OTUk frame is composed of 4080 x 4 bytes, and is divided into an overhead region 110, a payload region 120, and an FEC region 130. It is set. In addition, a 6 byte frame alignment signal (FAS) 111 is positioned at the start of the OTUk frame, and a 1 byte multi frame alignment signal (MFAS) 112 is positioned immediately after the FAS 111.

FIG. 2 is a diagram illustrating a virtual rain scheme introduced for 40GbE and 100GbE transmission in IEEE P802.3ba.

First, the virtual lane 220 is generated by dividing each of the 64b / 66b encoded 100GbE signals 210 in units of 66b. At this time, the order of inserting the signal 210 into the virtual lane 220 is in a round-robin manner. In other words, if the first 66b block is put in the virtual lane # 0, the second 66b block is put in the virtual lane # 1, and each block is put in the 20 virtual lanes 220 in turn, and the 21st 66b block is Put it back in virtual lane # 0.

Then, if there are 10 physical electric lanes 230, for example, in a system transmitted with 10 parallel signals in a backplane, 20 virtual lanes 220 are bit-interleaving. Multiplexed in the manner of ten electric lanes (230). Accordingly, each electric lane 230 has two virtual lanes.

Thereafter, when there are four physical optical lanes 250 for optical transmission, for example, an optical module that allocates four optical wavelengths and transmits them through the optical link, the 10: 4 multiplexer 240 is used. It can be placed in the four optical lanes 250 in a bit-interleaving manner.

The final optical lane 250 multiplexed through the above-described process has five virtual lanes. In this case, it can be seen that a signal of an arbitrary virtual lane is transmitted along one physical lane. For example, the signal 221 of the virtual lane # 5 is transmitted only through the specific electric lane 231 and the specific optical lane 251. This is due to setting the number of virtual lanes as the least common multiple of all physical lanes.

Meanwhile, in order to apply the Ethernet virtual lane scheme to the OTN frame, signal alignment information for compensating the time delay difference between the virtual lanes and lane identification information for distinguishing the virtual lanes are required.

First of all, the method for lane alignment includes a frame alignment signal (FAS) located in a 6-byte region from the beginning of an OTUk frame, followed by a multi-frame alignment signal (MFAS) of 1 byte. Distributing to virtual lanes can facilitate lane alignment.

3A and 3B illustrate a result of distributing OTUk frames by 20 bytes and distributing them to 20 virtual lanes.

Specifically, FIG. 3A illustrates a grouping of one OTUk frame 300 by 8 bytes. Each block is represented by the form (n: m), which indicates that the block is from column n to column m in the row. For example, (1: 8) shown in the first block 311 of the first row represents columns 1 to 8, and the unit is byte. That is, the first block 311 is a block grouping the first to eighth bytes of one row. The second block 312 that follows is a block grouping the 9th to 16th bytes of the first row. The same can be said for the remaining blocks. Meanwhile, the transmission order of OTUk frames is transmitted from left to right and from top to bottom. That is, immediately after the last block 313 of the first row is transmitted, the first block 321 of the second row is transmitted.

3B shows the result of distributing the grouped OTUk frames to 20 virtual lanes in a round-robin manner. When grouping 8 bytes from the start of the OTUk frame and grouping them in 20 virtual lanes in a round-robin manner, the block corresponding to the start of the OTUk frame (hereinafter referred to as a 'framing block') is intact. The total number of 2040 blocks, including the framing blocks, is divided into 20 virtual lanes, which are allocated in separate lanes.

Although FIG. 3B illustrates that the framing block 311 is placed in the virtual lane # 0, the virtual block 311 may start from any virtual lane. In addition, although the size of one block is described as 8 bytes in FIGS. 3A and 3B, if the size of one block is 8N (N = 1, 2, ..... 102) byte units, 7 bytes (from the start of the frame) FAS and MFAS) are included in one block and one OTUk frame is divided into exactly 20 virtual lanes, so if the block size is 8N (N = 1, 2, ..... 102) byte unit It is also possible.

However, when distributed to virtual lanes as shown in FIG. 3B, framing blocks are always placed in the same lanes (311 and 311 ′). Therefore, in order to align the virtual lanes, it is necessary to evenly distribute the framing blocks to the respective virtual lanes.

4A to 4D illustrate the results of applying the basic lane rotation technique according to the prior art.

Referring to FIG. 4A, when three consecutive OTUk frames 410, 420, and 430 are distributed to 20 virtual lanes by combining 8 bytes, when the one OTUk frame ends, the virtual lanes are rotated by one lane. have. That is, if a first block of a frame is distributed for a random Nth OTUk frame 410 starting from virtual lane # 0 (VL0), the N + 1th OTUk frame 420 is a virtual lane in which one lane is rotated ( 402 is distributed so that the framing block 421 of the frame 420 is in VL1 rather than VL0. Similarly, the N + 2 th OTUk frame 430 is again distributed to the virtual lane 403 in which one lane is rotated so that the framing block 431 of the frame 430 is placed in VL2.

4B shows the result of evenly dividing 20 consecutive OTUk frames into virtual lanes. Referring to FIG. 4B, it can be seen that a combination of signals of each virtual lane based on a framing block has a structure similar to that of an OTUk frame.

4c illustrates a result of reconstructing a set of 20 different blocks included in each virtual lane into alphabets A through T. Referring to FIG. One OTUk frame comes out once from A to T, and each group consists of a total of 102 8-byte sets when the frames are grouped by 8 bytes.

FIG. 4D is a conceptual diagram illustrating the expansion of FIG. 4B. When the group including the framing block is called A, it can be seen that the A blocks are pushed one by one and appear in 20 virtual lanes. In addition, it can be seen that when viewed from the time of any OTUk frame, that is, grouped in the vertical direction, the A block necessarily appears in one virtual lane. Therefore, this lane rotation technique is useful for lane alignment because the FAS is equally distributed to each virtual lane. However, the basic lane rotation scheme described with reference to FIGS. 4A-4D does not help distinguish virtual lanes.

On the other hand, since the OTUk frame has an MFAS signal for distinguishing multiple frames, a method of distinguishing virtual lanes using the same may be considered. When the frames are grouped by 8 bytes, the MFAS signal is also included in the framing block, so it is equally distributed to each virtual lane as in the FAS. If the number of virtual lanes is a power of 2 ( ^2N ; N is a natural number), it is possible to distinguish the virtual lanes through MFAS. For example, if there are four virtual lanes, a framing block appears once every four OTUk frames in each virtual lane. At this time, the MFAS value is increased by 4, and each virtual lane is represented by a set of different MFAS values. Since the MFAS values are sequentially displayed from 0 to 255, when the four virtual lanes are rotated by the simple lane rotation technique, one of the following four sets has the MFAS values.

{4N}, {4N + 1}, {4N + 2}, {4N + 3} (N = 0,1,2, ..... 63)

Therefore, the virtual lane can be easily distinguished by the MFAS value.

However, if the number of virtual lanes is not a power of two, the virtual lanes cannot be distinguished by the MFAS value. For example, if there are 20 virtual lanes, the distribution result is as follows according to the basic lane rotation technique.

VL0 {0, 20, 40, 60, 80 ... 220, 240, 4 , 24 ...}

VL1 {1, 21, 41, 61, 81 ... 221, 241, 5, 25 ...}

VL2 {2, 22, 42, 62, 82 ... 222, 242, 6, 26 ...}

VL3 { 3 , 23 , 43 , 63, 83 ... 223, 243, 7, 27 ...}

VL4 { 4 , 24 , 44, 64, 84 ... 224, 244, 8, 28 ...}

...

VL19 {19, 39, 59, 79, 99 ... 239, 3 , 23 , 43 ...}

Therefore, in this case, the virtual lane cannot be distinguished only by looking at the MFAS value.

FIG. 5 illustrates a method of overwriting a VL ID (Virtual Lane Identifier) for virtual lane identification on the last byte of the FAS signal according to the related art. In case of dividing the frame by 8 bytes, it is advantageous for the receiver to include frame alignment information and VL ID information in the first 8 bytes of the OTUk frame 500. However, the first 8 bytes of the OTUk frame 500 are composed of a 6-byte FAS 510, a 1-byte MFAS 520, and a portion of a section monitoring (SM) 530 signal of OTUk overhead. Among these, MFAS and SM signals cannot be overwritten because they are used for special purposes after the receiver reassembles OTUk frames. Therefore, the VL ID is overwritten with the last byte of the FAS that is relatively useless.

Analyzing the prior art for distinguishing virtual lanes, there are several different approaches.

The first method is to modify the OTUk frame structure standardized by the ITU-T to define a part for the VL ID. In other words, the lane rotation scheme described with reference to FIG. 4A is combined with the method of overwriting the VL ID described with reference to FIG. 6. However, this method has a disadvantage in that part of the FAS must be used for another purpose (VL ID).

The second method is to advantageously specify the number of virtual lanes for 100 GbE in OTUk in IEEE P802.3ba. In other words, if the number of virtual lanes is a multiple of 4 instead of 20, as described above, OTU4 can also use MFAS as a virtual lane ID without modifying the frame structure at all. However, if two standards bodies favor each other's signal or do not want to modify the frame structure, a method is needed to properly distribute the 20 virtual lanes without modifying the OTU4 frame structure.

6A to 6C are diagrams for describing a method of periodically changing a rotation direction of a virtual lane according to the present invention.

According to the present invention, as shown in FIG. 6A, the virtual lane is rotated forward for 601 consecutive OTUk frames (601), and then the virtual lane is rotated backward for one OTUk frame (602). The virtual lane is then rotated forward for m consecutive OTUk frames (603). In this case, n and m are natural numbers and can be adjusted according to the number of virtual lanes. When all virtual lanes are rotated, the number of framing blocks input to each virtual lane is adjusted to be a power of two.

FIG. 6B shows the results distributed to the virtual lanes by the present invention using English characters representing the OTUk frame fragments defined in FIG. 4C. Group A is a fragment group of an OTUk frame including a framing block. FIG. 6B shows an example of an MFAS value at a position of group A. FIG. As such, by changing the rotation direction of the virtual lane in a periodic pattern of "6-4-4-4-4-4-6-4 -...", 256 MFAS values (0 to 255) are converted into 20 virtual It can be distributed to have an independent set of lanes. The rotation direction changing period described with reference to FIG. 6B corresponds to an example, and the rotation direction changing period of the virtual lane may be changed according to the number of virtual lanes and the rotation order of the virtual lane.

FIG. 6C illustrates a set of extracting only MFAS values when the virtual lane is rotated as shown in FIG. 6B. Unlike the conventional art, it can be seen that a specific MFAS value appears only in a specific virtual lane. Therefore, according to the present invention, it is possible to distinguish the virtual lane using only the MFAS signal at the receiver after frame transmission without generating a separate VL ID or modifying the structure of the OTUk frame at the transmitter.

FIG. 7 is a block diagram of a virtual lane recognition apparatus according to an aspect of the present invention. A transmission side apparatus for distributing a frame (eg, an OTUk frame) of an optical transmission network signal to a virtual lane by periodically changing a rotation direction of the virtual lane. And a receiving side apparatus 800 that aligns and recognizes the virtual lanes, reassembles them, and restores them to a frame of a circular optical transmission network signal.

The transmitting device 700 includes a framer 710, a frame breaker 720, and a lane recognition rotary device 730.

The framer 710 is in charge of framing the optical transmission network signal and processing the optical transmission network signal, and may use a framer chip well known in the art, and a detailed description thereof will be omitted.

The frame decomposition apparatus 720 decomposes the frame into a predetermined size so that the FAS and MFAS of the OTUk frame to be transmitted are included in one block. In this case, the frame decomposition apparatus 720 preferably decomposes the OTUk frame such that the size of one frame block is 8N (N = 1, 2, ... 102) bytes.

The lane recognition rotating apparatus 730 distributes the frame blocks decomposed by the frame splitting apparatus 720 to the plurality of virtual lanes in a round-robin manner while periodically changing the rotation direction of the virtual lane.

Specifically, the lane recognition rotary device 730 is configured to include a forward rotation device 731, a reverse rotation device 732 and a frame distribution device 733.

The forward rotation device 731 and the reverse rotation device 732 rotate the virtual lanes in the forward and reverse directions, respectively, according to the rotation direction determined by the frame distribution device 733.

The frame distribution apparatus 733 distributes the frame blocks decomposed by the frame decomposition apparatus 720 to a plurality of virtual lanes in a round-robin manner. When the distribution of one OTUk frame is completed, the frame lanes are divided. After dispensing by lane, continue dispensing.

In this case, the frame distribution apparatus 733 may not rotate the virtual lane only in a specific direction but periodically change the rotation direction of the virtual lane. To this end, the frame distribution apparatus 733 determines the rotation period of the virtual lane according to the number of virtual lanes, and controls the forward rotation device 731 and the reverse rotation device 732 to rotate the virtual lane.

The frame distribution apparatus 733 may determine the rotation period of the virtual lane so that the number of times the framing blocks including the FAS and the MFAS are distributed to all the virtual lanes satisfies the following condition as a result of rotating the entire virtual lane once. Do.

(Total number of virtual lanes) ≤ 2 ^N (N is an integer) ≤ 2 ⁸

For example, if the number of virtual lanes is 20, the frame distributor 733 operates the number 3 forward rotating device 731 and then operates the number 1 reverse rotating device 732 as described with reference to FIG. 6B. After operating the fourth forward rotary device 731 again, the first reverse rotary device 732 is operated, and again the fourth forward rotary device 731 is operated, and then the first reverse rotary device 732 is operated. After operating the fourth forward rotary device 731 again, the first reverse rotary device 732 is operated, and again the fourth forward rotary device 731 is operated, and then the first reverse rotary device 732 is operated. By rotating the fourth forward rotary device 731 again and then operating the first reverse rotary device 732 and repeating the third forward rotary device 731 again, it rotates once for the entire virtual lane. As a result, the framing block is a full virtual lane The number distribution may be such that 32 (= 2 ⁵⁾ dog.

Meanwhile, the receiving device 800 includes a lane recognizing device 810, a virtual lane reassembling device 820, and a framer 830.

The lane recognizing apparatus 810 aligns virtual lanes for each virtual lane using FAS, and distinguishes and recognizes each virtual lane using a set of MFAS values.

In detail, the lane recognizing device 810 includes a lane recognizing processor 811, a first lane recognizing device 812, and a second lane recognizing device 813.

The lane recognition processor 811 detects the FAS for each virtual lane and checks a period in which the FAS is detected, and then transfers the virtual lane having a constant period to the first lane recognizing apparatus 812 and the virtual lane having a specific pattern. Transfer to the second lane recognition device 813.

The first lane recognizing apparatus 812 is a device that processes a virtual lane in which a period in which the FAS appears is always constant, and the second lane recognizing device 813 processes a virtual lane in which a period in which the FAS appears is a specific pattern. to be. The first lane recognizing device 812 and the second lane recognizing device 813 refer to the lane recognizing table 840 using a set of MFAS values to distinguish and recognize each virtual lane, and perform lane alignment using the FAS. do. At this time, the lane identification table 840 is configured in advance, and stores the pattern of the period in which the FAS appears in each virtual lane.

The virtual lane reassembly apparatus 820 reassembles a frame (eg, an OTUk frame) of a circular optical transmission network signal from all virtual lanes in which lane alignment and recognition are completed by the lane recognizing apparatus 810.

The framer 830 is in charge of framing the optical transmission network signal and processing the optical transmission network signal, and may use a framer chip well known in the art, and a detailed description thereof will be omitted.

8 is a flowchart illustrating a virtual lane recognition process according to another aspect of the present invention, and illustrates a lane recognition process when one OTUk frame is decomposed into 8 byte units and transmitted through 20 virtual lanes.

First, it receives a signal in units of 8 bytes (S901) and checks whether it is an 8 byte group starting with a predetermined FAS signal, 'F6F6F6282828 _HEX ', and if the FAS signal is not detected, the step S901 is repeated.

When the FAS signal is detected (S902), the MFAS value corresponding to the next 1 byte of the FAS signal is stored (S903). After that, the signal is input in units of 8 bytes until the FAS signal is displayed and the test is performed.

If the interval between the first FAS signal and the second FAS signal is 2 groups or 30 groups (S904), the virtual lane is transmitted to the second lane recognition apparatus (S905). On the other hand, if the interval is 32 groups (S907), the virtual lane is transmitted to the first lane recognizing apparatus (S908). On the other hand, if the interval does not correspond to all 2 groups, 30 groups and 32 groups, an error alarm is generated (S912). Here, one group corresponds to a group unit described with reference to FIG. 4C, that is, 102 x 8 bytes.

Thereafter, the first lane recognizing apparatus processes the virtual lane in which the FAS signal and the MFAS appear every 8 x 102 x 32 bytes. First, after checking whether the FAS signal detection period and the MFAS value are normal (S909), the skew is compensated using the FAS. The virtual lane is recognized with reference to the lane recognition table (S910). On the other hand, if it is abnormal, after generating an error alarm (S912) and returns to the first step (S901) of the lane recognition process.

On the other hand, the second lane recognizing apparatus processes the virtual lane in which the FAS signal and the MFAS appear once every 8 x 51 x 2 bytes and 8 x 51 x 30 bytes, and first checks whether the FAS signal detection period and the MFAS value are normal ( S906) The skew is compensated using the FAS, and the virtual lane is recognized with reference to the lane recognition table (S910). On the other hand, if it is abnormal, after generating an error alarm (S912) and returns to the first step (S901) of the lane recognition process.

Thereafter, the virtual lane reassembly apparatus reassembles each virtual lane that has been aligned and recognized through the first lane recognizing device and the second lane recognizing device in order and outputs the frame in the form of a circular optical transmission network signal (S911).

The present invention is not limited to the above-described embodiments and the accompanying drawings. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

1 is a structural diagram of an OTUk (k = 1, 2, 3) frame standardized in ITU-T Recommendation G.709;

2 is a diagram illustrating a virtual lane technique introduced for 40GbE and 100GbE transmission in IEEE P802.3ba,

3A and 3B illustrate a result of distributing OTUk frames by eight bytes and distributing them to 20 virtual lanes;

4a to 4d is a view showing the result of applying the basic lane rotation technique according to the prior art,

FIG. 5 is a diagram illustrating a method of overwriting a VL ID for virtual lane identification with a last byte of a FAS signal according to the prior art; FIG.

6a to 6c are views for explaining a method of periodically changing the rotation direction of the virtual lane according to the present invention,

7 is a configuration diagram of a virtual lane recognition apparatus according to an aspect of the present invention, and

8 is a flowchart of a virtual lane recognition process according to another aspect of the present invention.

Claims (11)

A framer responsible for forming a frame of an optical transmission network signal and processing the optical transmission network signal; A frame decomposition apparatus for decomposing the frame into a predetermined size so that a frame alignment signal (FAS) and a multi-frame alignment signal (MFAS) of the frame to be transmitted received from the framer are included in one block; Transmitting side virtual lane recognition comprising a lane-recognition rotating device for distributing the frame block decomposed by the frame decomposition device to a plurality of virtual lanes in a round-robin manner while periodically changing the rotation direction of the virtual lane Device. The method of claim 1, And the frame decomposition apparatus decomposes the frame such that the size of one frame block is 8N (N = 1, 2, ... 102) bytes. According to claim 1, The lane recognition rotary device, The frame block disassembled by the frame decomposition apparatus is distributed to a plurality of virtual lanes in a round-robin manner, and when the distribution of one frame is completed, the virtual lane is rotated one lane using a forward rotation apparatus or a reverse rotation apparatus. A frame distribution device for distributing the next frame; A forward rotation device configured to rotate the virtual lane in a forward direction according to the control of the frame distribution device; And And a reverse rotation device configured to rotate the virtual lane in a reverse direction according to the control of the frame distribution device. The method of claim 3, wherein The frame distribution apparatus rotates once for the entire virtual lane, and as a result, the number of framing blocks including FAS and MFAS is distributed to the entire virtual lane, (Total number of virtual lanes) ≤ 2 ^N (N is an integer) ≤ 2 ⁸ Transmitting side virtual lane recognition apparatus characterized in that for determining the rotation period of the virtual lane to satisfy the condition of. 5. The method of claim 4, When the frame distribution apparatus has 20 virtual lanes, After operating the forward rotating device three times, the reverse rotating device is operated once, the forward rotating device is operated four times, and then the reverse rotating device is operated once, and the forward rotating device is operated four times. Operate the reverse rotation device once, operate the forward rotation device four times, operate the reverse rotation device once, operate the forward rotation device four times, and then operate the reverse rotation device once, And operating the forward rotating device once and then operating the forward rotating device three times after operating the forward rotating device four times. A lane recognizing apparatus that aligns the virtual lanes with respect to each of the plurality of received virtual lanes using a frame alignment signal (FAS) and distinguishes the virtual lanes using a set of multi-frame alignment signal (MFAS) values; A virtual lane reassembly device for reassembling a frame of a circular optical transmission network signal from all virtual lanes in which lane alignment and recognition are completed by the lane recognizing device; And A framer that receives a frame reassembled by the virtual lane reassembly device and is in charge of signal processing; Here, the lane recognition device, Detecting the FAS for each of the plurality of virtual lanes and checking the detection period of the FAS, the virtual lane having a constant detection period is transmitted to the first lane recognizing device, and the virtual lane having a predetermined pattern has a detection period to the second lane recognizing device. Lane recognition processor for transmitting; A first lane recognizing apparatus that receives a virtual lane having a constant FAS detection period from the lane recognizing processor, identifies a virtual lane by referring to a lane recognition table using a set of MFAS values, and performs lane alignment using the FAS; And A second lane recognizing apparatus that receives a virtual lane having a predetermined pattern from the lane recognition processor by using a set of MFAS values, distinguishes virtual lanes by referring to a lane recognition table, and performs lane alignment using FAS. Receiving-side virtual lane recognition apparatus comprising a. delete Checking a detection period of a frame alignment signal (FAS) included in the input signal by receiving a signal in a predetermined unit; If the detection period of the FAS is constant or has a specific pattern, checking whether the detection period and the MFAS value included in the input signal are normal; Performing recognition and alignment of virtual lanes when the detection period and the MFAS value are normal; And And reassembling each virtual lane that has been recognized and aligned, and outputting a frame of a circular optical transmission network signal. 9. The method of claim 8, And generating an error alert when the detection period of the FAS is not constant and does not have a specific pattern. 9. The method of claim 8, And generating an error alert when the detection period or the MFAS value is abnormal. 9. The method of claim 8, The performing and recognizing the virtual lanes may include: aligning virtual lanes using the FAS and recognizing virtual lanes by referring to a lane recognition table using a set of MFAS values.

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