KR101236673B1 - Memory compression - Google Patents

Abstract

Exemplary embodiments of the invention include a method of compressing data for storage in a memory. According to one embodiment, the method forms a set of values based on the monotonically ordered sequence of lookup table values. For one or more paired values in this set, this exemplary method generates a difference in the values in the pair. After modifying the set by replacing one of the values in the pair with a difference based value, this exemplary method stores the final values based on the modified set in memory. The invention also includes a memory for storing lookup table values. One example memory includes a decoder, an encoder, and one or more cross of interconnected interconnect lines that interconnect the encoder with the decoder. These cross-crossed interconnection patterns may be implemented on one or more planar layer of conductor tracks that are alternately perpendicular to the insulating material.

Memory Compression, Lookup Tables, Walsh Transforms, Butterfly Circuits

Description

Memory Compression {MEMORY COMPRESSION}

The present invention enables the size and cost reduction of low cost electronic devices based on embedded microprocessors with memory requirements for fixed data, such as lookup tables or programs.

Electronic devices often use microprocessors to perform a variety of tasks, from very simple to very complex. When a device (electronic communication device, remote control device, other mobile device, etc.) is designed for a specific function or functions, a program corresponding to these functions is usually read-only memory (ROM) when development is completed. ) Other fixed data, such as lookup tables for values of any function needed for calculations such as exponential or logarithmic functions or trigonometric functions, may also be stored in the ROM.

The low cost and compact form of ROM is Mask Programmed ROM. In a mask programmed ROM, the address is decoded to provide a logic level on one of the plurality of signal lines corresponding to the address. The address line intersects the bit line corresponding to the desired output word, and a transistor is disposed at the intersection of all the address lines and the bit lines, in which case binary "1" is the desired bit output for that address. This ROM is actually equivalent to a huge OR-gate for each output bit, which determines the output bit as "1" if address A1.OR.A2.OR.A3 .... is active, otherwise "0". Determined by

The transistor used to represent the stored '1' provides an input to each multi-input OR gate. Figure 1 shows such a ROM, where a 32 bit long word is stored for each of 1024 addresses. If larger memory is desired, the pattern of FIG. 1 may be repeated to form consecutive rows of 1024 words, and a particular word with activation of a specific column address line to enable output from the selected row. A row-selection line is provided to select.

The transistors are disposed by custom-designed diffusion and / or contact and / or metallization masks used during the fabrication process, which are adapted to the desired bit pattern. Since mask-making is expensive, it is only used if the ROM contents are expected to be fixed for a large number of production units. Thus, other forms of memory such as electronic or UV-erasable and reprogrammable read only memory (EAROM, EEROM, EPROM, "flash" memory, etc.), and other more recent nonvolatile memory developments, such as ferroelectric memory, It is more common to select a masked ROM over the convenience of the convenience that the memory can be manufactured and later filled as well as modified during use, before knowing the desired content. It can be said that the silicon area of the mask programmed ROM and the resulting cost benefits to date are not sufficient to outweigh the ease of in-situ programming.

One solution that can provide the benefits of mask ROM while preserving some flexibility is to store a fixed table or character set display for a mature part of the program, i.e., a subroutine or a mathematical function, but not rewrite it. Linking and calling them by smaller programs in programmable memory. As such, when the mask-ROM routine needs to be replaced, the replacement routine only needs to be placed in reprogrammable memory and the mask-ROM version needs to be bypassed (a process called "patching"). However, the area benefits of mask ROM are still not sufficient to facilitate widespread use of this technology. Thus, there is a need for fixed-content memory, which is considerably more compact and economical than the mask ROM so far.

Exemplary embodiments of the invention include a method of compressing data for storage in a memory. According to one embodiment, the method includes forming a set of values based on a monotonically ordered series of lookup table values. For one or more paired values in the set, this exemplary method generates a difference of the values in the pair. After replacing one of the values in the pair with a value based on the difference to modify the set, this exemplary method stores the final values based on the modified set in memory.

According to one embodiment, the remaining values in the modified pairs remain unchanged. After this first iteration, the final values based on the modified set are stored in memory. As another alternative, additional iterations may be performed to further compress the data store. For example, in a second iteration, this exemplary method forms a pair between unmodified values and a pair between modified values, resulting in a new difference of values within these new pairs. Thereafter, this exemplary method modifies the current set by replacing one of the values in the pairs with a value based on the difference. This process is repeated until a predetermined number of iterations are completed. After completing the last iteration, the final values based on the modified set of values generated by the last iteration are stored in memory.

According to another embodiment, the remaining values in the modified pairs are replaced with values generated based on the sum of the values in the pair. After this first iteration, the sum and difference of each pair are combined to generate the final values. As another alternative, additional iterations may be performed to further compress the data store. For example, in a second iteration, this exemplary method forms a pair between the summation values and forms a pair between the difference values and generates a new summation and difference of the values within each of the new pairs. This process is repeated until a predetermined number of iterations are completed. After completing the last iteration, the sum and difference corresponding to the pairs of the last iteration are combined to generate the final values.

In one embodiment, by using the algorithm of the present invention, the ROM for storing the quantity 2 ^N1 of word length L1 is from the total size of L1 x 2 ^N1 bits to 2 ^N2 words of L2 bits, total L2 x 2 ^N2 Compressed into a ROM that stores bits, where L2 < L1 and N2 < N1.

One application is to provide a lookup table for the regular function F (x), which is addressed by the binary bit pattern corresponding to x and outputs the value F pre-stored at that location. In this case, primary compression replaces the alternate values of the function with its delta values from the previous address. As another alternative, each pair of adjacent values may be replaced by its summation (least significant bit (LSB) is discarded) and its difference. If the function is regular, the difference between successive values is much smaller than the function value itself, and thus can be stored with fewer bits.

The quadratic algorithm repeats the compression procedure, taking as input an array of even-address values from the first stage and separately receiving an odd-address delta value array, one function value, two 1s instead of four function values. Obtaining a differential difference and one secondary difference. The second difference is usually much smaller than the first difference, and thus can be stored using much fewer bits than the first difference to achieve further compression. A systematic procedure is disclosed for creating a higher order compression algorithm using a fast Walsh transform based on a modified Butterfly operation in which the LSB of the sum term is discarded. The value is reconstructed using an inverse transform when reading the ROM.

The second implementation stores a block of numerically contiguous values by storing a common or nearly common most significant bit (MSB) pattern and a different LSB pattern, thereby reducing the average number of bits for the stored value. This allows for a more convenient block size, i.e. regular block size, if the common most significant bit pattern in the block can differ by at most + or -1. The extra bits associated with the least significant part determine whether the common most significant part should be increased or decreased for a particular retrieved value. The second implementation allows for simpler reconfiguration than the first implementation.

The invention also includes a memory for storing a plurality of lookup table values, where each lookup table value is associated with an address comprising a plurality of address symbols. One example memory includes a decoder, an encoder, and one or more cross-crossed interconnect line patterns. The decoder generates an enable signal for one of the decoder outputs by decoding one or more of the plurality of address symbols, while the encoder generates an output word based on the enable signal. A cross pattern of crosses connects each of the decoder outputs to one encoder input. To reduce the size of the memory, certain aspects of the present invention employ one or more planar layer of conductor tracks that are interleaved perpendicular to the insulating material to utilize the vertical dimension of the memory. Form cross-connected interconnect patterns.

One exemplary use of this memory makes it possible to compress the memory size for storing values of irregular functions or for storing random values such as computer program instructions. In this case, the algorithm of the present invention operates on data values or functions in sorted numerical order, which can be achieved by substituting a fixed pattern of address lines on a chip. The compression procedure described for the regular function can then be used to replace any absolute data value with its delta to the nearest absolute data value stored anywhere, thus storing the delta rather than storing the absolute data value. Less bits are used. If two or more adjacent values are the same, they can be compressed into one and the corresponding address lines can be merged using the OR gate input. Each OR gate input requires one transistor, so it is equivalent to a memory bit in terms of occupied silicon area.

Reconstruction of the addressed value compressed using the M-order algorithm involves reading a L2-bit long word each time one of the M adjacent address lines is activated. Subsequently, its constituent parts, including the base value, primary and higher difference, are combined according to which of the address lines is activated. The M address lines of each group may be combined using an M-line to log ₂ (M) -line priority encoder to obtain log ₂ (M) bits that systematically enable reconstruction combining logic.

Using the present invention, the ROM silicon area can be reduced by two to five times, depending on the order of the algorithm and the amount of reconstruction combining logic used. Bit-exact reconstruction always occurs, which is of course required when the compressed data is a computer program.

In a second aspect of the exemplary memory implementation, compression of random ROM content is achieved by sorting the data in numerical order by replacing the address line. It is possible to store the same number of bits of information in the ROM with fewer actual bit elements than the information bits, because the information is effectively stored in the substitution pattern. Because it can accommodate a large number of interconnect pattern layers separated by an insulating layer on the chip, a large number of different address line substitution patterns (each containing information) can be produced, thus utilizing the vertical dimension. To store an increased amount of information.

1 shows a mask programmed read only memory (ROM).

2 is a graph of one exemplary regular function.

3 is a diagram illustrating an exemplary compression algorithm.

4 illustrates exemplary reconstruction logic.

5 shows a graphical comparison between a true monotonic function and an exponential approximation.

6A-6D illustrate one exemplary process for removing a first layer of a butterfly circuit for reconstructing stored data.

7 shows a conventional MOS transistor.

8 is a diagram illustrating a configuration of an exemplary memory circuit.

9A and 9B illustrate one exemplary row address decoder.

10 is a diagram illustrating an exemplary process for arranging stored data in a sorted order.

11 is a diagram illustrating an example implementation of a memory using first order compression of random data.

12A-12C illustrate one example implementation of address decoding.

13 is a diagram illustrating an exemplary priority encoder.

14A and 14B are diagrams comparing example encoder and decoder combinations.

First, an exemplary application of the present invention is described in which a lookup table for the values of the desired regular function, for example the monotonic increment function, is required for a particular calculation. Equation 1 shows an exemplary function,

Where "a" is the base of the log. This function is derived from the logarithmic arithmetic operations described in all pending US patent applications Ser. Nos. 11/142760 and 11/142485, filed June 1, 2005, which are incorporated herein by reference in their entirety. Included in the specification.

로 표시된, 512x의 보수에 대해 그려져 있으며, 인수

이 증가됨에 따라 단조 증가 함수값을 제공한다. 원하는 것은 16384개의 가능한 개별적인 테이블 지점들로부터 임의의 주어진 x 값에 대해, 23 이진 자리수(binary place)의 정확도를 갖는 함수값에의 빠른 액세스를 제공하는 것이다. 다른 대안으로서, 밑 e가 사용될 수 있으며, 이 경우 24 이진 자리수로 유사한 정확도가 달성된다.A graph for this function is shown in FIG. 2 with the base 2 for the value of x divided by 0 to 16383 divided by 512, i.e., 9 bits to the right of the binary point and 5 bits to the left of the binary point. This function is in the range of 0 to 32.

Are drawn for the complement of 512x, denoted by the argument

As it increases, it provides a monotonically increasing function value. What is desired is to provide quick access to a function value with an accuracy of 23 binary places for any given x value from 16384 possible individual table points. As an alternative, the base e can be used, in which case similar accuracy is achieved with 24 binary digits.

The uncompressed lookup table for the latter will contain 16348 24-bit words, totaling 393216 bits. The value of the word must be rounded to the nearest LSB, which is an important fact described later. However, whatever the values are, there is a need for any compression and decompression algorithms applied to these lookup table values to regenerate the desired rounded values in a bit-exact manner.

< OOxxxxxxxxxxxx에 대해 F(x) = 0으로 간주될 수 있으며, 따라서

> 00111111111 = 4095에 대해서만 값이 필요하다. 그렇지만, 이것은 이 예시적인 함수에 특별한 것이며, 따라서 여기에서 자세히 설명하지 않는다. 오히려, 16384개 값 전부의 제공에 대해 살펴본다.For values of x greater than 17.32, this function is zero to 24-bit accuracy if base e, and zero if base 2 is 2 when x> 24. This is x> 24, i.e. x> 11 xxx.xxxxxxxxx or

<F (x) = 0 can be considered for <OOxxxxxxxxxxxx

A value is required only for> 00111111111 = 4095. However, this is special to this exemplary function and therefore is not described in detail here. Rather, we look at the provision of all 16384 values.

에서의 단지 최하위 1 비트 차이(1 least significant bit difference)에 대한 연속적인 값들 간의 차분은 함수 자체보다 명백히 훨씬 더 작 으며, 따라서 더 적은 비트로 표현될 수 있다. 이 관찰은 임의의 매끈한 함수(smooth function)에 대해 유효하다. 따라서, 1차 압축 알고리즘은

의 짝수 주소값에 대해서만 24-비트 값을 저장하고 홀수 주소에는 이전의 짝수번째 값으로부터의 델타-값을 저장하는 것을 포함한다.take over

The difference between successive values for only the least least significant bit difference in is obviously much smaller than the function itself, and thus can be represented with fewer bits. This observation is valid for any smooth function. Therefore, the first compression algorithm

Storing a 24-bit value only for even address values, and storing delta-values from previous even values in odd addresses.

에 대해서는 24-비트 값만이 필요하고, 홀수 주소

에 대해서는 24-비트 값 및 14-비트 값 둘다가 판독되고 가산되어야 한다. 따라서, ROM은 16384 x 24 = 393216 비트로부터 8192 x (24 + 14) = 311296 비트로 압축되었으며, 21%의 절감, 즉 원래의 크기의 79%로의 압축이 얻어진다.In direct calculations for the example function, the highest delta that comes out is 16376 (2 ^-24 times), which can be accommodated in a 14-bit word. Thus, the ROM can be reconstructed as 8192 24-bit words and 8192 14-bit words. An even address

Requires only 24-bit values for odd addresses

For 24-bit and 14-bit values, both must be read and added. Thus, the ROM was compressed from 16384 x 24 = 393216 bits to 8192 x (24 + 14) = 311296 bits, resulting in a 21% reduction, that is, compression to 79% of the original size.

The quadratic algorithm can be derived by applying the process of replacing adjacent pairs of values with values and delta values to a first array of 8192 24-bit values and separately to a second array of 8192 14-bit delta values. have. The first application yields two apart deltas in the original function, which is almost twice the single-spaced delta and thus requires 15-bit storage. The second application of this algorithm to an array of 14-bit primary deltas yields a second delta, which should theoretically be in the range of 0 to 31, requiring 5 bits. However, due to the above rounding to the nearest 24-bit word of the function, the range of secondary deltas increases from min -1 to max 33, requiring 6 bits of storage. The reason for this is that one value can be rounded down while adjacent words are rounded up to increase (or decrease) the delta by one or two.

의 최상위 12 비트로 4096 x 59 비트 ROM을 어드레싱하는 것을 포함하며, 이어서

의 최하위 2 비트가 다음과 같이 4개의 서브워드로부터의 원하는 값의 재구성을 제어하는 데 사용된다.The ROM size is now reduced to 4096 24, 15, 14 and 6-bit values, totaling 4096 x 59 = 241664 bits, respectively, resulting in a 39% savings, i.e. compression to 61% of the original size. The reconstruction of the desired value is used to obtain four subwords of length 24, 15, 14 and 6-bits respectively.

Addressing a 4096 x 59 bit ROM with the most significant 12 bits of

The least significant two bits of are used to control the reconstruction of the desired value from the four subwords as follows.

LSB = 00에 대해 24, 15, 14 및 6-비트 값을 F, D2, D1, 및 DD로 표기하면, 원하는 값은 F이고,

If the 24, 15, 14, and 6-bit values for LSB = 00 are denoted as F, D2, D1, and DD, the desired value is F,

01 F + D1

10 F + D2

11 F + D1 + D2 + DD

to be. A 14-bit adder is needed to form F + D1, a 15-bit adder is required to form F + D2, and a 6-bit adder is required to form D2 + DD. Thus, a 35 bit full adder cell is needed to reconstruct the desired value. In the case of the exemplary function, the DD range of -1 to +33 can be shifted from 0 to 34 by decreasing the stored 15-bit D2 value by 1 and using the following rule.

LSB = 00에 대해, 원하는 값이 F이고,

For LSB = 00, the desired value is F,

01 F + D1

10 F + D2 + 1

11 F + Dl + D2 + DD

의 LSB에 따라 1 또는 DD를 D2에 가산하고, 일반적으로 마이너스에서 플러스까지의 DD의 임의의 범위가 수용될 수 있게 해주기 위해 값 DD0 또는 DD1을 가산할 수 있다.to be. Thus, the 6-bit adder

1 or DD can be added to D2 according to the LSB, and the value DD0 or DD1 can be added to generally allow any range of DD from minus to plus to be acceptable.

3 shows a compression algorithm by repeating the process of finding differences between adjacent values. The desired values to be stored are 16384 24-bit values initially denoted by f0, f1, f2, .., f6, ..., (as follows), f (16384). The first application of the process of finding the difference leaves the even value intact, but each odd value is replaced by the difference from the previous even value. For example, f5 is replaced by d4 = f5-f4. For the exemplary smooth function, these differences are calculated to be up to 14-bit long values, which are 1024 times smaller than the original 24-bit value. For a much smoother function that is nearly straight, the difference between two values that are only 1/16384 apart of the range can be expected to be 1/16384 times smaller than the original maximum and thus be 14 bits shorter. . In general, this shortening of word length occurs for any smooth function. Thus, in the second row, the function value is represented by 8192 value pairs, one 24-bit long and the other 14 bits long.

In the third row of Fig. 3, the even-numbered values denoted by f0, f2, f4, ... and the differential values denoted by d0, d2, d4, .. apply the difference algorithm to the remaining f-values and separately d- Shown apart to indicate application to the value. The result shown in line 4 is that every second even value, i.e. every fourth value of the original values, is still present as a 24-bit value, but even-numbered values such as f2-f0 are 15-bit difference. have. The other d-values remain likewise unchanged 14-bit values, but the values in between, such as d6-d4, are reduced to 6-bit second order differences. The original 16384 24-bit values are now compressed into a set of 4096 values, including 24-bit, 15-bit, 14-bit and 6-bit values.

This process can be repeated until most values have a high order difference of only two bit lengths. These ultimate high order differences form a slightly random pattern because the original 24-bit values are rounded up or down to the nearest 24 binary digits. The total size of the memory is reduced depending on how many times the difference algorithm is applied.

4 shows the reconstruction logic for a second-order differential compression algorithm. The original method of storing 16384 24-bit words, shown in the figure above, includes a lookup table with a 14-bit address. The figure below shows a second-order differential compression technique with a lookup table reduced to 4096 59-bit values. They are addressed using only the top 12 bits of the original 14-bit address, which effectively defines a group of four values where the target value exists. 59 bits, including 24-bit absolute, 15-bit double-space difference, 14-bit single-space difference, and 6-bit secondary difference, are applied to each adder as shown. The adder of the first column is enabled by the second least significant bit, if that bit is '1', adds a 15-bit difference to a 24-bit value and a 6-bit secondary difference to a 14-bit difference, otherwise If the enable bit is '0', the 24-bit value is passed without adding a 15-bit value and the 14-bit value is passed without adding a 6-bit value. The adder in the second column adds the output of the first two adders if the least significant bit of the original 14-bit address is '1', otherwise passes through the 24-bit value. As such, it controls which of the group of four values the least two bits of the original 14-bit address occur.

Note that additional savings can be made by noting that D2 is nearly twice as large as D1, so that 14-bit value INT (D2 / 2) = RightShift (D2) to obtain a bit exact value of D1. Only 15-bit D2 needs to be stored with the correction to be applied. This correction is a quadratic difference represented by D1- (D2 / 2), which D1- (D2 / 2), according to direct calculation, occupies a range of -1 to 8, requiring 4 bits of storage. okay. Then, it can also be seen that this secondary difference is approximately equal to 1/4 of the value DD. Thus, the second order difference can be replaced by the difference from DD / 4, which, by direct calculation, has a range of -1 to +1 which requires two bits of storage, and in fact can be denoted DDD. That's the third difference.

Thus, in order to regenerate each of 16384 24-bit function values with bit-accuracy, the stored value includes 4096 sets of four values as follows.

24-bit value: F (4i)

15-bit value: D2 (4i) = F (4i + 2)-F (4i)

6-bit value: DD (4i) = (F (4i + 3)-F (4i + 2))-(F (4i + 1)-F (4i))

2-bit value: DDD (4i) = (INT (D2 (4i) / 2))-(F (4i + 1)-F (4i))-INT (DD (4i) / 4)

The four function values F (4i), F (4i + 1), F (4i + 2), F (4i + 3) can then be reconstructed with bit-accuracy from below.

F (4i + 1) = F (4i) + INT (D2 (4i) / 2) + INT (DD (4i) / 4)-DDD (4i)

F (4i + 2) = F (4i) + D2 (4i)

F (4i + 3) = F (4i) + INT (D2 (4i) / 2) + DD (4i) + INT (DD (4i) / 4)-DDD (4i)

The four original 24-bit values were replaced by a total of 47 bits instead of 96, with a slightly better compression ratio than 2: 1.

Conversely, as another alternative, only 14-bit D1 may be stored with the correction to be applied to 2D1 to obtain D2. In this way, other configurations, such as storing the following, are possible.

24-bit value F (4i)

14-bit value D1 = F (4i + 1)-F (4i)

6-bit value DD = (F (4i + 3)-F (4i + 2))-D1

3-bit value DDD = (F (4i + 2)-F (4i))-(2D1 + INT (DD / 4))

This makes the reconstruction slightly simpler. It will be appreciated that operations such as INT (DD / 4) represent obvious logical functions that do not use the two LSBs of DD.

Before calculating a table showing the compression achieved using different order algorithms, a more systematic version of higher order compression is developed based on a modified Walsh Transform. The Walsh transform method forms the sum and difference of adjacent pairs of values and replaces the original values with this sum and difference. For example, in the first iteration to compress data containing f0, f1, f2, and f3, f0 is replaced by s0 = f0 + f1, f1 is replaced by f1-f0, and f2 is s2 = f2 + is replaced by f3, and f3 is replaced by d2 = f3-f2. The circuit that calculates the sum and difference of the value pairs is called a butterfly circuit.

All of the summations are arranged adjacently following every difference. The differences are shorter words than summation, as seen previously. This process is then repeated for a block of sum values for a higher order algorithm as well for a higher order algorithm and then for a block of differential values (each half of the length of the original value) separately. The highest-order algorithm for 16384 values is 14. At that time, the blocks each have only one value and thus can no longer be compressed. The fourteenth order algorithm is actually a 16384-point Walsh transform, and the lower order algorithm is stopped at the abort stages of the full Walsh transform. The sum and difference associated with the last iteration is combined to form the final compression value stored in memory. It will be appreciated that the last iteration may be any selected iteration and therefore need not be the 14 th iteration.

When forming the sum of two 24-bit values, the word length can be increased by one bit. However, the sum and difference always have the same least significant bit, so this least significant bit can be discarded in one of them without losing information. By discarding the least significant bit in the summation and using Equation 2,

Instead, the summation is prevented from increasing in length. Upon reconstruction, the difference is added to or subtracted from the summation, and the LSB of the difference is used twice by feeding the carry / borrow input of the first adder / subtractor stage to replace the missing summation LSB. do. Mathematically, the modified transform butterfly can be written as

SUM (i) = INT ((F (2i + 1) + F (2i)) / 2)

DIFF (I) = F (2i + 1)-F (2i)

The reconstruction can be written as

F (2i +1) = SUM (i) + INT (DIFF (i) / 2) + AND (1, DIFF (i))

F (2i) = SUM (i)-INT (DIFF (i) / 2)-AND (1, DIFF (i))

More Than Walsh-Fourier Transforms

SUM (i) = F (2i + 1) + F (2i)

DIFF (i) = F (2i + 1)-F (2i)

And his station

F (2i + 1) = (SUM (i) + DIFF (i)) / 2

F (2i) = (SUM (i)-DIFF (i)) / 2

A modified version of the known "butterfly" operation used in.

Fast, base-2, pseudo-walsy transform (pseudo-FWT) converts a group of two adjacent values into one value and one delta, or four adjacent A group of values may be constructed using the modified butterfly described above to convert one value, two delta values, one secondary delta value, or the like. This makes a systematic process for investigating or implementing the higher order algorithms. The FORTRAN code for proper pseudo-walsh conversion is given below.

C F IS THE GROUP OF M VALUES TO BE PSEUDO-WALSH TRANSFORMED

C AND N = LOG2 (M) IS THE ORDER OF THE ALGORITHM

SUBROUTINE PSWLSH (F, M, N)

INTEGER * 4 F (*), SUM, DIFF

N1 = M / 2

N2 = 1

DO 1 I = 1, N

L0 = 1

DO 2 J = 1, N1

L = LO

DO 3 K = 1, N2

SUM = (F (L + N2) + F (L)) / 2

DIFF = F (L + N2) -F (L)

F (L + N2) = DIFF

F (L) = SUM

L = L + 1

3 CONTINUE

LO = L + N2

2 CONTINUE

N1 = N1 / 2

N2 = 2 * N2

1 CONTINUE

RETURN

END

The table below shows the degree of data compression of the example function achieved using other orders of pseudo-walsh algorithm.

The order of the algorithm Number of words Total word length Total number of bits Base-e Base-2 0 16384 24 393216 376832 One 8192 38 311296 (319488) 294912 2 4096 59 241664 (258048) 221184 3 2048 93 190464 (215040) 169984 4 1024 147 150528 (182272) 135168 5 512 238 121856 (161792) 106496 6 256 381 97536 (142848) 89088 7 128 624 79072 (135424) 71680 8 64 1084 69376 59968 9 32 1947 62304 51136 10 16 3507 56112 45072 11 8 5738 45904 37096 12 4 10020 40080 30492 13 2 17782 35564 26296 14 One 32085 32085 23188

가 23 이진 자리수까지 계산되고, 밑이 e인 경우에는 24 자리까지 계산되며 이는 비슷한 정확도를 나타낸다.The number of bits in parentheses is obtained when the Walsh transform is used using standard butterfly operations. The compression degradation of the standard Walsh transform is partly due to an increase in the word length of the summing term and partly due to an increase in the rounding error in the original table values when higher order differences are formed, which is a modified butter. It becomes less noticeable when a ply is used and the LSB of the summation is discarded. In both cases, reconstruction of the bit accuracy of the original value is achieved when the appropriate inverse algorithm is applied. If base is 2, function

Is calculated to 23 binary digits, and if it is the base e, it is calculated to 24 digits, indicating similar accuracy.

Thus, with the final conversion order 14 working on the entire array, the lookup table is reduced to a single word 32085 (23188) bits wide, which is on average less than 2 bits per table value, but each value is 24-bit ( 23-bit) accuracy. A single word is no longer a table and does not require an address because it can always be read and values can only be hardwired to the input of the reconstruction adder. However, 14 levels of reconstructing adders are needed, and the number of single-bit adder cells required is approximately 65000. Since the adder cell is larger than the memory bits, it does not represent the minimum silicon area. The minimum area is achieved in some compromise between the number of bits stored and the number of adder cells needed for value reconstruction. Nevertheless, a silicon area reduction of approximately 4 or 5 times appears to be entirely feasible.

It can also be concluded that the method given above builds a machine that will calculate any individual value of the smooth function. The memory table disappears at the extremes and is replaced by hardwired inputs to the adder tree. By this, an adder stage that adds zero can be simplified to handle only carry transfers from the previous stage and likewise an adder that always has a "1" at one of its inputs can be similarly simplified. This may lead to a simplification step.

을 저장하는 데 필요한 512-워드 테이블에 적용될 수 있다. 이 함수는 인수 범위의 일부분에 걸쳐 충분할 수 있는 상기 예시적인 함수에 대한 근사치이다. 전범위에 걸쳐 이 근사치를 사용하고 또 더 짧은 워드 길이를 갖는 필요한 정정만을 저장하는 것이 유용하다.The pseudo-FWT table compression algorithm also uses a value when the base 2 log is used and X ₂ is 9 bits long.

Can be applied to the 512-word table needed to store the. This function is an approximation to the example function that may be sufficient over a portion of the argument range. It is useful to use this approximation over the entire range and store only the necessary corrections with shorter word lengths.

Using the base-2, the bit pattern for the exponential function of this base-2 is repeated in the shift as the argument changes from 0.X ₂ to 1.X ₂ , 2.X ₂ , and so on, so 0.X ₂ (where X ₂ is a 9-bit value) Only the marked principal range needs to be synthesized. The table below provides the total number of bits that need to be stored to synthesize the function, where 0 to 511 are rounded to the nearest 23 bits after the binary decimal point for the value of the argument X ₂ .

The order of the algorithm Word count Total word length Total number of bits 0 512 23 11776 One 256 37 9472 2 128 57 7296 3 64 89 5696 4 32 139 4448 5 16 219 3504 6 8 358 2864 7 4 585 2340 8 2 974 1948 9 One 1608 1608

The last row configures the machine to compute the function without memory, using only a controlled adder with a fixed hardwired input.

또는

의 값(이 값은 로그 영역에서의 가산 및 감산을 위한 로그 산술에서 사용됨)을 얻기 위해 이 지수 함수에 대한 정정이 필요하다.In addition to the bits mentioned above,

or

A correction to this exponential function is needed to get the value of (this value is used in logarithmic arithmetic for addition and subtraction in the logarithmic region).

및

의 원하는 값들과 지수 함수 간의 차분이 밑-2의 경우에 대해 나타내어져 있다. 이들 차분은 원래의 함수보다 더 적은 공간을 차지하는 룩업 테이블에 저장될 수 있으며, 칩 면적은 대략적으로 오른쪽 아래의 곡선 아래의 삼각형 면적으로 표시된다. 게다가, 정정도 역시 정칙 함수를 형성하기 때문에, 그 테이블도 역시 본 명세서에 기재된 기술에 의해 압축될 수 있다.5

And

The difference between the desired values of and the exponential function is shown for the case of base-2. These differences can be stored in a lookup table that takes up less space than the original function, and the chip area is approximately represented by the triangular area under the curve at the bottom right. In addition, since the correction also forms a regular function, the table can also be compressed by the techniques described herein.

In a variant of the compression algorithm, most of the reconstruction adders can be eliminated. This is based on the finding that the sum of a given 24-bit value and a given 14-bit value always results in the same 14 LSB being obtained. Thus, it is efficient to store a 14-bit delta, i.e. a 14-bit pre-calculated summation of a 24-bit value and a 14-bit value, i.e. c0 = f0 + d0, instead of d0. However, it is also necessary to store an extra bit indicating whether the addition of the 14-bit delta to the 24-bit value caused a carry from the 14th bit to the 15th bit. As such, by storing 15 bits instead of 14 bits, the first 14 bits of the reconstruction adder can be eliminated. The 15th bit applies to the carry delivery circuit for the most significant 10 bits. The carry transfer circuit is simpler than a full adder and can be eliminated if there are later add stages in the application where the 15th bit can be inserted. This will be described with reference to FIG. 6. In fact, the least significant bit of the original pair of contiguous values is retained, but associated with the common highest part. In addition, the extra bits indicate whether the top portion should be increased when reconstructing the second value of the pair.

6A shows a conventional butterfly circuit that adds or subtracts the same 14-bit value to or from a 24-bit value to produce one of two alternative values according to a SELECT control line. 6B shows that the butterfly circuit can be simplified with a 14-bit adder that adds or subtracts a 14-bit value to or from a 24-bit 14 LSB to produce one of the two alternative 14 LSBs of the result. Represents a carry or borrow bit from an add or subtract operation that is combined with a 10 MSB of 24 bit value to produce one of two alternative 10-bit MSB patterns. The MSB pattern may be the same if no barrow or carry is generated by the 14-bit adder / subtractor. In FIG. 6C, two alternative 14-bit results are simply pre-stored, and corresponding to the difference (subtraction) operation is stored with 10 MSBs instead of 24-bit values, while corresponding to the summation result is 14-bit. Stored instead of the value. However, the fifteenth bit is needed to indicate whether 10 MSBs are equal or incremented by one when summed. The 15th bit is always 0 in the differential case and is shown as an input to the selector with 14 LSBs from the 24-bit word. If zero is implemented in memory as the absence of a transistor, then the columns of zero do not occupy silicon area. In Figure 6C the carry transmitter is still needed to increase 10 MSBs as needed.

The selector in FIG. 6C does not need to be provided explicitly. It is essential in memory that an address bit selects one or the other of a number of stored values. Thus, two alternative 14 (or 15) bit patterns are simply selected by a select line, which is the least significant bit of the 14-bit address. 10 MSBs are addressed by 13 MSBs in the address. Thus, the memory contains 8192 10-bit words and 16384 14 / 15-bit words, a total of 319488 bits, which is 8192 bits more to eliminate the 14-bit adder. Finally, FIG. 6D illustrates omitting the carry transmitter by delaying increasing 10 MSB with carry bits and only feed forwarding the carry bits to be used for convenient opportunities in subsequent adders.

Dividing a 24-bit word into a 10-bit portion and a 14-bit portion in FIG. 6 results from an exemplary function that represents the delta between even and odd addressed values that are never greater than 14-bit values. The 10 MSB is always only 1 different between the same or even and adjacent odd addressed values. Similarly, the difference between two distant values is never greater than a 15-bit value, and the difference between four distant values is never greater than a 16-bit value. Thus, a group of four (or even five) adjacent values have the same highest 8 bits except for a possible increase of 1, while having different least significant 16-bit portions. Thus, an alternative realization is to arrange the memory into 4096 8-bit values and 16384 17-bit values, with the 17th bit indicating whether 8 MSBs should be increased by one. This reduces the number of bits to 311296. A table showing the number of bits of memory for different partitions is shown below.

Group size Number of MSBs Number of LSBs (+1) Memory bits 2 10 15 319488 4 8 17 311296 8 7 18 309248 16 6 19 317440 32 5 20 330240 64 4 21 345088

This table indicates that there is an optimal partition that minimizes the number of bits.

This process can now be repeated by recognizing that the LSB pattern in each group is monotonically increasing values. For example, in each group of 64 values in the last case, two adjacent values cannot differ by more than a 14-bit value. Thus, they can be divided into 32 groups of two and two alternative 14 or bit LSB patterns that store 7 MSBs for each pair, which must be incremented by 1, with the 15th bit being 7 MSBs. Indicates whether should be increased by one.

Other ways of representing a group of 64 21-bit values are shown below, implying the total number of memory bits.

Group size Number of MSBs Number of LSBs (+1) 64-bit for groups Total memory 2 7 15 1184 304128 4 5 17 1168 300032 8 4 18 1184 304128

Repeating the procedure for the group of 32 results in:

Group size Number of MSBs Number of LSBs (+1) 32-bit for group Total memory 2 6 15 576 297472 4 4 17 576 297472 8 3 18 588 303616

For 16 groups, the following is obtained.

Group size Number of MSBs Number of LSBs (+1) Bit for 16-group Total memory 2 5 15 280 292864 4 3 17 284 296960

For any given table of regular functions, the above attempt can be performed to determine how to obtain the minimum number of stored bits.

The above method can be used not only for a smooth function but also for a smooth function for each section. For example, if a group of 32 values is compressed at one time using any of the above techniques, the values within each group of 32 need only represent a smooth function, ie a continuous function. Discontinuities between different groups are not important.

To explain how this technique can be applied to more random data, a general configuration of a MOS ROM is described first. 7 shows the configuration of a MOS transistor. The conductive gate electrode is made of a conductive material with a high melting point to withstand processing temperatures and is usually separated from the silicon substrate by a thin insulating layer of silicon dioxide. The gate and the oxide insulator below it are generally created by first covering the entire substrate with the gate structure and then etching away except where the gate is desired. Next, drain electrodes and source electrodes are formed by injecting impurities into both sides of the gate. The implanted impurities must be able to integrate with the silicon substrate crystal structure by raising the temperature just below the melting point of the silicon. Once the MOS transistors have been formed, these transistors can be interconnected by depositing aluminum interconnect wiring.

8 shows a ROM manufactured as described above. Alternating stripes of source and drain diffusions form a number of transistors in which the source and drain are in parallel. This transistor is located where the gate structure is not etched away. Transistors are placed where binary 1 is desired to be stored, and transistors are not placed where binary 0 should be stored. In fact, in FIG. 8, the transistor is shown to include a gate from a source line above the drain line and a gate from a source line below the drain line. Both are two transistors that are enabled with the same gate signal, and are therefore in parallel in nature. The number of individual drain lines corresponds to the number of bits in the word. All of the source lines for the same word are connected to the left side of the word row enable signal, which is pulled to ground to read the words in that row.

Different columns of transistors correspond to different words in that row. The address decoder accepts a binary address input and sends an enable signal on all gates in a column, thus enabling all bits of a particular word to send to the drain line. If the word contains zero at that position, the drain line is pulled down by the turned-on transistor, otherwise it is not pulled down if there is no transistor (corresponding to zero in that word).

Multiple rows of words can be produced, and the address line operates from top to bottom through all rows. The source enable line for each word-row is connected to a second row-address decoder, where the full address is a combination of column address and row address. A suitable row-address decoder that pulls down the source line of the enable word-row is shown in Figures 9A and 9B.

As shown in FIG. 9A, the cascadeable configuration block includes two MOS transistors whose source is commonly connected to a "cascoding input" (C). The address line is connected to the gate of one transistor, the drain of which represents a complementary address signal, which is connected to the gate of the other transistor. As a result, either the transistor or the other transistor conducts between the source and the drain, depending on whether the address line is high or low. The cascade of this building block is shown in Fig. 9B, where the drain connections DR1 and DR2 of the first device controlled by the address bit A1 are both controlled by the address bit A2. It is connected to the source connection of two identical building blocks, which are located above. These drain connections are in turn connected to a pair of building blocks, all of which are controlled by address bits A3, to provide eight drain connections, which are likewise below. As such, the N-bit address bit pattern is decoded by a binary tree of building blocks to create a conducting path from one of the 2 ^N final drain connections to a first source connection called " chip enable &quot;.

Pulling down the chip enable line pulls down one of the drain connections corresponding to the enabled conduction path, which in turn pulls down one of the word-row source lines, which in turn causes that word row (the word transistor corresponding to this word row). Pulls down the drain line for &lt; RTI ID = 0.0 &gt; a &lt; / RTI &gt; turned on by the column address. A sense amplifier (not shown) detects which bit line can draw current from the power supply and generates an output bit pattern corresponding to the addressed word. Sense amplifiers compensate for losses through long chains of transistors and provide buffered logic-level outputs to processors outside of memory.

10 illustrates a method in which a memory including random values may be arranged in order of numerical values. The words are simply aligned and arranged in numerical order while remaining connected to the same output line of the address decoder. This requires that the decoded address line must be crossed crosswise as shown, which can be achieved with a suitable multilayer interconnection pattern. The address lines can be rearranged in different cross-crossing patterns for linking to the words of the next row, which is likely to be arranged in a completely different order. It does not achieve compression on its own and merely illustrates the possible way of arranging random data on the chip in monotonically increasing order of numerical values while still reading out the exact value associated with each address.

11 illustrates an implementation of a memory for first order compression of random data using a decoder, cross-cross pattern, and encoder. Compared to FIG. 10, every other word in the value-sorted order has been eliminated. The word before the removed word now contains an OR gate that ORs two addresses, thereby addressing its own address as well as the address of the abbreviated word that was adjacent to it. The address line of the omitted word now enables a shortened delta word that is added to the previous word by the reconstruction logic to regenerate the omitted word. The number of bits of memory has been reduced to full and delta words for every pair of original full words at the expense of two input OR gates per pair. The two-input OR gate is up to four transistors, which can be counted as four bits. This must be added to the delta-word length in estimating the amount of silicon area to be saved.

The address line cross pattern also requires chip area. By reassigning the OR gate below the previous word, a crossover interconnection pattern can pass over the area occupied by the previous word using an appropriate number of wiring layers that are insulated or separated from each other. Such layers can be prepared using photolithography techniques. For the purposes of the present invention, it is assumed that essentially an infinite number of wiring layers can be used and that the insulating layer separates the crossover and / or crossover interconnection patterns from unwanted contacts. Indeed, to store more data using the same chip area, using layers on the layers of the interconnection pattern uses vertical dimensions.

Care should be taken in extending the concept of higher-order difference algorithms to random data, because differences greater than the first order may not represent meaningful regularity. Instead, selecting one whole word as the default for a group of words and replacing other words in the group with its delta from the default can improve the efficiency of compression. For example, a group of four values f0, f1, f2 and f3 may be replaced with f0, d1 = f1-f0, d2 = f2-f0, and d3 = f3-f0. Then, the logical OR of the four addresses must address the value of f0. The four-input gate is up to eight transistors. The silicon area occupied by this four-input OR gate is the cost of reducing three full words f1, f2 and f3 to three delta-words d1, d2 and d3. The four-input OR gate is only twice as complex as the two-input OR gate, but memory reduction is now approximately three times more. Thus, the overhead of the OR gate is reduced compared to the achieved savings. Whenever two data values to be stored are identical and thus appear next to each other in a value sorted order, they are replaced with a single value and the delta does not need to be stored. Then, no address line corresponding to zero delta is needed, and the OR of the two address lines to a single stored value can be absorbed as the last step of address decoding by using an AND-OR gate as shown in FIG.

12A shows two decoders of the FIG. 9 type, for example, decoding eight address bits into one of 256 address lines. Since FIG. 9 has an open-drain output, a pull-up transistor (or resistor) must be added to reset the output to a known state between memory reads. Then, 256 lines (A0 ... A255) of one decoder cross over 256 lines (B0-B255) of the other decoder to form 65536 intersections. When individual lines of 65536 lines must be decoded, a two-input AND gate is placed at its junction as shown in FIG. 12B, providing an address decoder complexity of four transistors per output line, for eight reasons. This is because the number of transistors in the 256-line decoder is negligible in the comparison. However, when only an OR of two addresses is needed, Figure 12C shows how eight transistors of two AND gates can be reconnected to form an AND-OR without using additional transistors.

Some common DSP programs used in mobile devices have been analyzed to estimate possible savings using the techniques described above. The first program containing 8464 16-bit instructions was determined to contain only 911 different 16-bit values. Obviously, the above technique, where many values are repeated many times, storing them only once and using AND-OR address decoding, can save approximately 9 times the chip area without having to use delta values. The second program of 2296 words was found to contain only 567 different 16-bit values, which also allows for a significant compression ratio. The combined program is compressed from 10760 words to 1397 words. In conventional memory address decoders, four transistors per address used in AND-OR address decoding were needed, thus not increasing the complexity. A more accurate estimate of the size reduction is the addition of four transistors per address in the address decoder to 16 transistors per word in the memory array, resulting in 20 transistors per word total for conventional memory, which is 4+. It is reduced to 16/9 transistors, which represents approximately a 3x reduction.

When the number of words to be stored exceeds the number of possible values, for example when storing a 16-bit value of 1 megaword, combine all the addresses where the same word will be stored to enable that particular 16-bit word. If you use AND-OR address decoding to do this, it is clear that you do not need to store more than 65536 values. This type of memory benefits from the use of more redundant interconnect layers to handle the complex interconnect patterns of AND-OR addressing. This technique is therefore a method of using vertical dimensions (more interconnect layers) on the chip to realize more efficient memory.

In the latter case, 65536 possible words do not even need to be stored. Once an appropriate address line has been AND-ORed to one of the 65536 lines needed to cause an output of a value between 0 and 65535, a device called a priority encoder can be used as the 65536: 16 line encoder, which 16: 65536 Inverse function of line address decoder. Priority encoders can be manufactured with up to six transistors per input, which is less than 16-bits per word otherwise needed. The priority encoder is shown in FIG.

A set of N inputs numbered from 0 to N-1 is divided into a first half (0 to N / 2-1) and a second half (N / 2 to N-1). The corresponding pair of lines are selected from the first half and the second half (eg, lines 0 and N / 2 as shown) and are OR'ed together. The NOR gate provides a logic '0' output when either of the inputs is one. The N-type transistor is energized when the bottom input is 1 and connects the top input to output B, which must be zero. The P-type transistor is energized when either input is 1 and connects the top input to output B when the top input is 1. Thus, output B has the polarity of the top input if either of the inputs is 1, otherwise output B is an open circuit. All outputs B are in parallel, forming a wired OR and providing 1 output if the active input line is in the upper half of the inputs, otherwise a '0' is output. This is the most significant bit of the desired encoding. This process is then repeated to produce N / 2 outputs A0 through A (N / 2-1) to generate the second most significant bit of the desired encoding, and so on. The number of stages required to fully encode the input lines is therefore N / 2 + N / 4 + N / 8 ... = N-1, with each stage having six transistors (four-transistor NOR gate and P-type and N-type transistor).

The combination of the address decoder and its inverse, i. E. The priority encoder, only reproduces the input as shown in FIG. However, if the lines are crossed, a random 1: 1 mapping (also referred to as a Substitution box, ie an S-box or information lossless coding) is generated. If some addresses are AND-ORed to imply that some output is missing, a many-to-one mapping or information lossy coding is generated. Thus, a read only memory having an output word length equal to the address word length can thus be created. Information is clearly stored in the address line cross intersection or substitution pattern, which is the only difference between FIGS. 14A and 14B. Using an estimated four transistors per line at the address decoder and six at the priority encoder shows savings for memory sizes over 1024 10-bit words. However, using multiple interconnect layers, several different interconnect patterns can be created, all of which share the same priority encoder and address decoder, providing a method of selecting the desired interconnect pattern. . As shown in Fig. 13, a series pass switch for each line composed of P-type and N-type transistors in parallel can be used for this. Thus, M interconnect patterns can be selected and M.2 ^N N-bit word size memories can be created using 2 + 10 / M transistors per word, which is efficient as the number of layers increases. This increases. For example, by generating a power supply of -V _t (for P-type switches) or V _cc + V _t (for N-type switches) to ensure that the switch is conductive for both logic 1 and logic 0 levels. Single-transistor pass-through switches may be used.

In summary, it has been found that a table of stored data representing a monotonic function can be compressed by storing a delta between only one default value for each group of numerically adjacent values and the default value for other values in the group. As another alternative, the group of values may be transformed using the Walsh transform using a modified butterfly operation. In the latter limited case, the result is that an arbitrary monotonic function can be synthesized with an array of adders with limited input, because the memory table disappears. An alternative to storing deltas is disclosed, which includes storing the LSB portion of the precalculated result of adding the delta and extra bits indicating whether carry to the MS portion is needed, and thus most reconstruction There is no need for an adder. This technique has been extended to the interval-wise monotonic function, where the function is monotonic for each compression group. This technique was then extended to random data, such as computer programs, by substituting address lines to consider that the data was first sorted in numerical order.

If the delta is zero, it does not need to be stored and no address line needs to be created to address it, thus simplifying the OR operation of the required address for the base word. In the analysis of a typical DSP program, most compression can be achieved using this technique alone. In addition, all possible output values can be generated by the priority encoder using six transistors per address line, without storing them, which is more efficient when the number of possible output values is greater than 64. The information then resides in an interconnect pattern connecting the address decoder to the priority encoder. Finally, the memory uses the vertical dimension to construct some of these interconnection patterns, and the pass switch is used to select the desired pattern to ultimately reduce the number of transistors used per word to one or two transistors per word. It has been found that by selecting several random data sets can be stored.

Of course, the invention may be practiced otherwise than as specifically described herein without departing from the essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes that come within the meaning and range of equivalency of the appended claims are to be embraced within their scope.

Claims (54)

A method of compressing data for storage in memory, Forming an ordered set of lookup table values by reordering the lookup table values in a monotonic order, Pairing adjacent values in the ordered set to form a plurality of non-overlapping pairs of values, For one or more paired values, generating a difference between the values in the pair of values, Reducing the number of bits needed to store the lookup table values by replacing one value in at least one pair of values with a corresponding difference to produce a compressed ordered set, and Storing the compressed order set in the memory Data compression method comprising a. 2. The method of claim 1, wherein modifying the set further comprises maintaining another one of the values in the paired values. 3. The method of claim 2, further comprising the step of repeating the occurring and the replacing step before the storing step. 4. The method of claim 3, wherein at least one of the pairs is different for different iterations. 2. The method of claim 1, wherein said compressed order set comprises at least one of said lookup table values. The method of claim 1, wherein the generating step comprises generating a difference and summation of the values in the pair, The replacing step, Replacing one of the values in the pair with a value based on the difference, and Replacing another one of the values in the pair with a value based on the summation Data compression method comprising a. 7. The method of claim 6, further comprising discarding the least significant portion of the summation. 7. The method of claim 6, further comprising the step of repeating the occurring and the replacing step before the storing step. 9. The method of claim 8, wherein said pairs of values differ for different iterations. 7. The method of claim 6, further comprising generating combined values from a final iteration by concatenating each of the sum and the difference corresponding to the paired values of the last iteration, And said replacing comprises replacing said values in said paired values of said last iteration with corresponding combined values. 7. The method of claim 6, further comprising repeating the generating and replacing steps until one of the summations includes a sum of all lookup table values rearranged in a monotonic order, and Generating a combined value by combining summations and differences from corresponding iterations More, Said replacing comprises replacing said values in said paired values from a final iteration with said combined value. 7. The method of claim 6, further comprising obtaining one or more synthesized values based on the combination of the sum and the difference generated for one or more paired values, Replacing one of the values in the paired values with the value based on the difference comprises replacing one of the values in the paired values with a least significant portion of the synthesized values. . 2. The method of claim 1, further comprising reconstructing one or more lookup table values based on the one or more values in the compressed order set stored in memory in accordance with a predetermined reconstruction formula. 2. The method of claim 1, wherein said lookup table values comprise values derived from a monotonic function. 15. The method of claim 14, wherein each of the forming, the generating, the replacing, and the storing are applied to discrete monotonic segments of a piecewise monotonic function. The data compression method further comprising the step of. 2. The method of claim 1 wherein the lookup table values comprise non-monotonic values arranged in a monotonic order. 17. The method of claim 16, further comprising placing the values in the compressed order set in a first layer of the memory, and through one or more crisscrossed address lines disposed in the second layer of the memory. Accessing one or more of the values in the compressed order set. A method of compressing data for storage in memory, Forming an ordered set of lookup table values by rearranging the lookup table values in a monotonic order, Pairing adjacent values in the ordered set to form a plurality of non-overlapping pairs of values, Generating, for one or more paired values, a difference and summation of the values within the paired values, In order to generate a compressed ordered set, storing the lookup table values by reducing the number of bits needed to store the ordered set by replacing values in at least one pair of values with corresponding sums and differences. Reducing the number of bits needed, and Storing the compressed order set in the memory Data compression method comprising a. 19. The method of claim 18, further comprising generating combined values by combining each of the summation and the difference for each paired value, And said replacing comprises replacing each of said sum and said difference with a corresponding combined value. 19. The method of claim 18, further comprising the step of repeating the occurring and the replacing step before the storing step. 21. The method of claim 20, further comprising generating combined values from the last iteration by combining summations and differences corresponding to the pairs of the last iteration, And said replacing comprises replacing each of said sum and said difference with a corresponding combined value. 19. The method of claim 18, further comprising rounding each sum to the nearest unit to form one or more modified sums; And said replacing comprises replacing values in at least one pair of values with said corresponding difference and said modified sum. 23. The method of claim 22, further comprising repeating the reoccurring, rounding, and replacing steps prior to the storing step, and From the last iteration, generating combined values by combining summations and differences corresponding to the pairs of the last iteration More, And said replacing comprises replacing each of said sum and said difference with a corresponding combined value. 19. The method of claim 18, further comprising generating a synthesized value for one or more of the paired values by combining the difference with the summation, And the replacing step includes replacing values in at least one pair of values with values based on the summation and the least significant portion of the synthesized value. 19. The method of claim 18, wherein the lookup table values comprise values derived from a monotonic function. 27. The method of claim 25, further comprising applying the forming, the generating, and the replacing step to separate forging sections of the forging function for each section. 19. The method of claim 18, wherein the lookup table values comprise non-monotonic values that are arranged in a monotonic order. 29. The method of claim 27, further comprising: placing the values in the compressed order set in a first layer of the memory, and the compressed order set through one or more cross-crossed address lines disposed in the second layer of memory. Accessing one or more of the values in the data compression method. 19. The method of claim 18, further comprising discarding the least significant portion of the summation before the replacing. A method of compressing data for storage in memory, Forming an ordered set of lookup table values by reordering the lookup table values in a monotonic order, the order set comprising non-overlapping pairs of values (f0, f1) and (f2, f3), generating d0 by obtaining a difference between f0 and f1 and generating d2 by obtaining a difference between f2 and f3, Reducing the number of bits needed to store the lookup table values by replacing f1 with d0 and replacing f3 with d2 to produce a compressed ordered set, and Storing the compressed ordered set in the memory based on the set modified by the replacement. Data compression method comprising a. The method of claim 30, wherein prior to the storing step, Pairing values in the compressed ordered set to generate paired values (f0, f2) and (d0, d2), generating d1 by obtaining a difference between f0 and f2 and generating d3 by obtaining a difference between d0 and d2, and replacing f2 with d1 and d2 with d3 Data compression method further comprising. 31. The method of claim 30, further comprising generating s0 by summing f0 and f1 and generating s2 by summing f2 and f3. 33. The method of claim 32, wherein replacing comprises replacing f0 with s0, replacing f1 with d0, replacing f2 with s2, and replacing f3 with d2. . 34. The method of claim 33, further comprising: generating a first combined value by combining s0 and d0, and generating a second combined value by combining s2 and d2 More, The replacing step further comprises replacing s0 and d0 with the first combined value, and replacing s2 and d2 with the second combined value. 34. The method of claim 33, further comprising generating c0 by synthesizing s0 with d0 and generating c2 by synthesizing s2 with d2, The replacing further includes replacing f0 with s0, replacing f2 with s2, replacing d0 with the lowest portion of c0, and replacing d2 with the lowest portion of c2. Way. 34. The method of claim 33, further comprising: pairing values in the modified set to generate paired values (s0, s2) and (d0, d2), generating s1 by summing s0 and s2 and generating s3 by summing d0 and d2, and generating d1 by finding the difference between s0 and s2 and generating d3 by finding the difference between d0 and d2 More, The replacing step further includes replacing s0 with s1, replacing s2 with d1, replacing d0 with s3, and replacing d2 with d3. 37. The method of claim 36, further comprising generating a combined value by combining s1, d1, s3, and d3, And said replacing step further comprises replacing s1, d1, s3 and d3 with said combined value. delete delete delete delete delete delete delete delete delete delete delete delete 38. Compressed data representing original data compressed using the method of any one of claims 1-12 or 14-37, and Reconstruction logic to reconstruct the original data from the compressed data Memory containing. 51. The memory of claim 50 wherein the memory is read only memory (ROM). An electronic device comprising a memory, The memory comprising: 38. Compressed data representing original data compressed using the method of any one of claims 1-12 or 14-37, and Reconstruction logic to reconstruct the original data from the compressed data Electronic device comprising a. 53. The electronic device of claim 52, wherein the memory is a read only memory (ROM). The electronic device of claim 52 wherein the electronic device is an electronic communication device.

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