KR101232287B1

KR101232287B1 - Alignment apparatus and method

Info

Publication number: KR101232287B1
Application number: KR1020110067281A
Authority: KR
Inventors: 권기원
Original assignee: 성균관대학교산학협력단
Priority date: 2011-07-07
Filing date: 2011-07-07
Publication date: 2013-02-12
Also published as: KR20130005715A

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment apparatus for aligning semiconductor elements when aligning semiconductor elements such as semiconductor wafers or chips in three dimensions. An alignment device according to the present invention includes: a transmission circuit pattern formed on a first semiconductor element and transmitting a predetermined electric signal; A reception circuit pattern formed on a second semiconductor element positioned above or below the first semiconductor element and receiving a signal transmitted from the transmission circuit pattern; And a positioning unit for determining an alignment position of the first semiconductor element and the second semiconductor element by sensing the strength or strength of the signal received by the receiving circuit pattern. According to the present invention, when the semiconductor elements are bonded, the semiconductor elements are aligned using the strength or strength of the signal in the receiving circuit pattern, so that alignment marks, patterns, etc. formed on the semiconductor elements by a mounting apparatus such as a pick-and-place tool or the like are formed. Even in the hidden state, the alignment between the semiconductor devices can be accurately performed, and the incidence of defective products due to the misalignment can be significantly reduced.

Description

Alignment apparatus and method

The present invention relates to an alignment apparatus for stacking wafers and wafers, stacking chips and chips, or aligning circuits when stacking wafers and chips, which is essential in semiconductor technology for increasing the degree of integration through three-dimensional stacking.

Recently, with the development of semiconductor integrated technology, a technology of three-dimensionally stacking semiconductor devices such as semiconductor wafers or chips has been developed. Through Silicon Via (TSV) technology allows integrated circuits made on multiple chips to be packaged in a single package to form what is called a System in Package (SiP).

To stack three or more chips, a TSV must be formed on the chip, and the back of the chip (the side where the circuit is not printed) and the front of the other chip are mechanically bonded.

1 illustrates a method of bonding a plurality of chips onto a wafer. Referring to FIG. 1, a dielectric adhesive layer 12 is placed on a landing wafer 10. The chip 14 is then placed on the landing wafer 10 by a pick-and-place tool 22. The chip 14 is bonded to the landing wafer 10 by the dielectric adhesive layer 12. At this time, the circuit pattern 16 on the landing wafer 10 and the through-hole vias 18 formed on the chip 14 should be aligned correctly.

2 illustrates a method of bonding another wafer (plural chips already bonded) onto the wafer. Referring to FIG. 2, the wafer 20 on which the plurality of chips 14 are bonded is placed on the landing wafer 10, and this process is performed by a wafer-level bonding tool 24. . And the bonding of the wafer 20 on the landing wafer 10 by the dielectric adhesive layer 12 is the same as above. Even in this bonding process, the circuit pattern 16 on the landing wafer 10 and the through-holes 18 formed on the chip 14 must be accurately aligned.

In the process of three-dimensionally stacking semiconductor elements such as semiconductor wafers or chips, an alignment apparatus is used for alignment between the circuit pattern of the wafer and the through-hole vias of the chip, or the alignment of the circuit pattern between two different wafers.

However, when picking up a very thin wafer or chip with a pick and place tool as described above, due to a structural problem of the picking device, a circuit pattern drawn on the wafer or chip below is not visible. Thus, the conventional alignment device recognizes the circuit pattern as an image signal before picking operation, and aligns the circuit pattern or the circuit pattern with the through-hole vias based on the image signal.

However, during the picking operation, a slight vibration or movement often occurs, and thus an alignment error occurs frequently. Typically, this alignment error is difficult to detect until an electrical property check is performed on the package that has been integrated. Another problem is that with the development of semiconductor integrated technology, the circuit pattern becomes gradually finer, whereas the imaging equipment of the alignment device is difficult to realize a precise resolution corresponding thereto.

The present invention has been proposed to overcome the limitation of the "Blind Align" of the conventional alignment device as described above, and to solve the problems caused by the alignment using the imaging equipment, forming a transmission and reception circuit pattern for alignment in the semiconductor device and detected on the receiving side By arranging the semiconductor devices using the strength or strength of the signal, the semiconductor devices can be aligned very precisely without the recognition of circuit patterns or through-hole vias printed on the semiconductor devices or measurement with imaging equipment. The purpose is to provide a new alignment device.

An alignment device according to an embodiment of the present invention, an alignment device for three-dimensionally aligning a plurality of semiconductor elements, comprising: a transmission circuit pattern formed on the first semiconductor element and transmitting a predetermined electrical signal; A reception circuit pattern formed on a second semiconductor element positioned above or below the first semiconductor element and receiving a signal transmitted from the transmission circuit pattern; And a positioning unit configured to determine an alignment position between the first semiconductor element and the second semiconductor element by sensing the signal strength or strength received from the receiving circuit pattern.

In an alignment device according to another embodiment of the present invention, the transmission circuit pattern and the reception circuit pattern transmit and receive radio frequency (RF).

In the alignment apparatus according to another embodiment of the present invention, the transmitting circuit pattern and the receiving circuit pattern transmit and receive radio frequency through inductive coupling.

In the alignment device according to another embodiment of the present invention, the transmitting circuit pattern and the receiving circuit pattern transmit and receive radio frequency through capacitive coupling.

The alignment apparatus according to another embodiment of the present invention, the transmitting circuit pattern and the receiving circuit pattern is each provided with an inductor for transmitting and receiving radio frequencies.

In the alignment device according to another embodiment of the present invention, a signal attenuation prevention hole is formed between the inductor of the transmission circuit pattern and the inductor of the reception circuit pattern.

In the alignment device according to another embodiment of the present invention, a magnetic material is filled in the hole for preventing signal attenuation.

In the alignment device according to another embodiment of the present invention, an insulating material is filled in the signal attenuation prevention hole.

In an alignment device according to another embodiment of the present invention, the transmission circuit pattern is supplied with power in a non-contact manner.

In the alignment device according to another embodiment of the present invention, the transmission circuit pattern is powered by the power supply node in an integrated contact manner.

According to the alignment apparatus of the present invention, when semiconductor devices such as semiconductor wafers or chips are three-dimensionally stacked, the semiconductor devices are aligned by transmitting and receiving signals between the transmission circuit pattern and the reception circuit pattern formed in each semiconductor device, such as a pick and place tool. When picking a semiconductor device by the placing device, alignment error due to vibration or movement of the picking device can be corrected even when circuit patterns, alignment marks, and through-hole vias are covered, and alignment accuracy can be improved even in "Blind Align". There is an effect to significantly reduce the rate of defective products due to alignment errors.

1 illustrates a method of bonding a plurality of chips onto a wafer,
2 is a view illustrating a method of bonding another wafer on a conventional wafer;
3 is a configuration diagram showing an example of the transmission and reception circuit pattern formation according to the present invention;
4 is a perspective view showing an example of transmitting and receiving radio frequency in the present invention,
5 is a graph illustrating signal strength in a reception circuit pattern in the embodiment of FIG. 3;
6 is a block diagram showing another embodiment of the present invention, and
FIG. 7 is a graph illustrating signal strength in a reception circuit pattern in the embodiment of FIG. 6.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be given the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

The alignment device of the present invention relates to an alignment device for alignment between semiconductor devices in a process of three-dimensionally bonding semiconductor devices. Here, the term "semiconductor device" is used to mean semiconductor devices such as wafers or chips.

In the alignment apparatus of the present invention, a circuit pattern specific to a semiconductor device to be stacked is printed, and the alignment positions of the semiconductor devices are determined by transmitting and receiving signals between the circuit patterns. When the alignment positions of the semiconductor devices are determined, bonding between the semiconductor devices is performed using a pick-and-place tool or a wafer-level bonding tool.

In the following description, ordinal expressions such as first and second are used to distinguish semiconductor devices to be stacked. For example, a second semiconductor element is stacked on or under the first semiconductor element. In the embodiment, only two of the first semiconductor element and the second semiconductor element are mentioned, but the third semiconductor element may be further stacked on the second semiconductor element.

3 shows an example in which a transmission and reception circuit pattern is formed in a semiconductor device according to the present invention. Referring to FIG. 3, a transmission circuit pattern 52 for transmitting a predetermined electric signal is formed in the first semiconductor element 50, and in the second semiconductor element 60 positioned below the first semiconductor element 50. A receiving circuit pattern 62 for receiving a signal transmitted from the transmitting circuit pattern 52 is formed.

The transmission circuit pattern 52 and the reception circuit pattern 62 may transmit and receive various types of wireless signals. According to a preferred embodiment, the transmitting circuit pattern 52 and the receiving circuit pattern 62 transmit and receive radio frequency (RF). Here, the transmission circuit pattern 52 formed in the first semiconductor element 50 requires a power source to generate an RF signal. This power supply can be provided in a contactless manner by a commonly known Radio Frequency Identification (RFID) chip. As another example, a power supply node (not shown) may be provided at an edge of a semiconductor device such as a wafer, and the like, and may be powered in a contact manner through the power supply node.

As another example from the example of FIG. 3, the first semiconductor element 50 may be disposed below and the second semiconductor element 60 may be positioned above. For example, the first semiconductor element 50 may be a landing wafer, and the second semiconductor element 60 may be a piece chip mounted thereon. In this case, a means (for example, an RFID chip or a power supply node, etc.) for supplying power to the transmission circuit pattern 52 will be installed on the landing wafer which is the first semiconductor element 50.

In the illustrated example, the transmit circuit pattern 52 and the receive circuit pattern 62 are formed of inductor pairs. When a test signal generated from an RFID chip or the like is applied to the transmission circuit pattern 52 of the first semiconductor element 50, the inductor forming the transmission circuit pattern 52 transmits an RF signal as illustrated in FIG. 4. In this case, the inductor of the reception circuit pattern 62 formed corresponding to the transmission circuit pattern 52 receives the RF signal according to the inductive coupling phenomenon.

Although not shown, the transmitting circuit pattern 52 and the receiving circuit pattern 62 are formed as a pair of capacitors, and transmit and receive an RF signal in a manner that detects a change in the capacitor value due to capacitive coupling. You may.

Referring to FIG. 3, the positioning unit 70 is connected to the receiving circuit pattern 62 of the second semiconductor device 60. The positioning unit 70 determines the alignment position between the first semiconductor device 50 and the second semiconductor device 60 by sensing the strength or strength of the signal received by the receiving circuit pattern 62. The positioning unit 70 may include a sensor for sensing the magnitude of the inductance, a microcomputer for outputting the position control value of the second semiconductor element 60 by calculating the output of the sensor.

When the inductors of the transmitting circuit pattern 52 and the receiving circuit pattern 62 are long aligned, the intensity of the signal detected by the receiving circuit pattern 62 will be greatest. 5 shows a change in intensity of the signal sensed by the positioning unit 70. Referring to FIG. 5, when the inductors of the transmitter and the receiver are long aligned, the signal strength is greatest, and when the inductor misalignment occurs, the signal strength gradually decreases to the negative or positive axis.

While the picking device of the pick and play tool 80 shown in FIG. 3 finely adjusts the position of the second semiconductor element 60 in front, rear, left and right, the positioning unit 70 intensifies the signal in the receiving circuit pattern 62. Detect. Then, the picking device is fixed in position at the point where the signal strength is greatest. Through such a control process, accurate alignment between the first semiconductor device 50 and the second semiconductor device 60 can be performed even when the through-hole via or the circuit pattern is covered by the picking device.

On the other hand, the signal generated in the transmission circuit pattern 52 generates an eddy current while passing through the silicon layer forming the semiconductor element, thereby the signal arriving at the receiving circuit pattern 62 may be weak. Figure 6 shows another embodiment for solving the signal attenuation caused by the eddy current.

Referring to FIG. 6, a signal attenuation prevention hole 72 is formed between the inductor of the transmission circuit pattern 52 and the inductor of the reception circuit pattern 62. For example, in the TSV forming process of the semiconductor device, the silicon layer existing between the two inductors may be removed to form the hole 72 for preventing signal attenuation as shown in FIG. 6.

The signal attenuation prevention hole 72 allows a higher level signal to be detected in the reception circuit pattern 62. Although the illustrated example illustrates a state in which the signal attenuation prevention hole 72 is filled with nothing (that is, a state in which an air layer is formed), it is filled with a magnetic material or another insulating material having a lower resistance value than air. The intensity of the signal detected by the receiving circuit pattern 62 may be further increased.

FIG. 7 illustrates the strength of a signal in the reception circuit pattern 62 sensed by the positioning unit 70 when the signal attenuation prevention hole 72 is formed. The graph shown in black in FIG. 7 is a graph when there is a silicon layer between two pairs of inductors (i.e., the same as in FIG. 5), and the graph shown in red is a graph when a hole 72 for preventing attenuation is formed. .

As shown, when the two inductor pairs are correctly aligned, the signal intensity is greater than that of FIG. 5, and the range of the alignment error is also significantly reduced.

The above-described alignment device of the present invention is characterized in that a circuit pattern for transmitting and receiving wireless signals is formed on a semiconductor device to be stacked. Here, such a circuit pattern can be put in a scribe line (usually about tens of um) formed between a chip and a chip on a silicon wafer by a conventional semiconductor manufacturing technique. Therefore, it will be obvious to those skilled in the art to practice the present invention based on the technical idea of the present invention.

Meanwhile, in the above-described embodiment, the first semiconductor device and the second semiconductor device have been described in which two devices are aligned. However, when three or more semiconductor devices are stacked, some semiconductor devices may combine a transmission circuit pattern and a reception circuit pattern together. It may be provided. In addition, the transmitting circuit pattern and the receiving circuit pattern may be integrally formed into one circuit pattern.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

50: first semiconductor element 52: transmission circuit pattern
60 second semiconductor element 62 receiving circuit pattern
70: positioning unit 72: signal attenuation prevention hole
80: Pick & Place Tool

Claims

In the alignment device for aligning a plurality of semiconductor elements in three dimensions,
A transmission circuit pattern formed on the first semiconductor element and transmitting a predetermined electric signal;
A reception circuit pattern formed on a second semiconductor element positioned above or below the first semiconductor element and receiving a signal transmitted from the transmission circuit pattern; And
It includes a positioning unit for determining the alignment position of the first semiconductor element and the second semiconductor element by sensing the signal strength or strength received from the receiving circuit pattern,
And the transmitting circuit pattern and the receiving circuit pattern transmit and receive a radio frequency (RF).

delete

The method of claim 1,
And the transmitting circuit pattern and the receiving circuit pattern transmit and receive a radio frequency through inductive coupling.

The method of claim 1,
And the transmitting circuit pattern and the receiving circuit pattern transmit and receive radio frequencies through capacitive coupling.

The method of claim 3,
And the transmitting circuit pattern and the receiving circuit pattern each have an inductor for transmitting and receiving radio frequencies.

The method of claim 5,
And a hole for preventing attenuation between the inductor of the transmission circuit pattern and the inductor of the reception circuit pattern.

The method according to claim 6,
Alignment apparatus in which a magnetic material is filled in the signal attenuation prevention hole.

The method according to claim 6,
Alignment device is filled with an insulating material inside the hole for preventing the signal attenuation.

The method according to any one of claims 1 and 3 to 8,
The transmitting circuit pattern is an alignment device that is powered in a non-contact manner.

The method according to any one of claims 1 and 3 to 8,
The transmitting circuit pattern is an alignment device that receives the power supply node is powered by the integrated contact method.