KR101226559B1 - Magnetic field communication system and magnetic field communication transmitter and magnetic field communication reciever using therein - Google Patents

Abstract

A magnetic field communication system is disclosed. The magnetic field communication system includes a magnetic field communication transmitter and a magnetic field communication receiver, the magnetic field communication transmitter encodes a data signal, mixes the encoded signal with a carrier frequency sinusoidal signal to generate a transmission signal, and transmits the transmission signal to an antenna Transmits to an external magnetic field communication system through a magnetic field communication channel, and the magnetic field communication receiver receives a magnetic field signal transmitted from the external magnetic field communication system through the magnetic field communication channel using the antenna, and the magnetic field The signal is demodulated using each of the carrier frequency sinusoidal signal and the carrier frequency sinusoidal signal, and decoded using each of a plurality of baud rate clock signals having different phases for each of the demodulated signals.

Description

MAGNETIC FIELD COMMUNICATION SYSTEM AND MAGNETIC FIELD COMMUNICATION TRANSMITTER AND MAGNETIC FIELD COMMUNICATION RECIEVER USING THEREIN}

Embodiments in accordance with the concept of the present invention relates to a magnetic field communication device, and more particularly, to a magnetic field communication system having a simple structure, low manufacturing cost, and a wide communication range, and a magnetic field communication transmitter and a magnetic field communication receiver used in the system.

Magnetic fields have a nearly constant magnetic permeability in a medium excluding magnetic materials, unlike electric fields in which the dielectric constant varies greatly with the medium of the communication channel. Therefore, magnetic field communication has been in the spotlight as a next generation wireless communication system that enables wireless communication in extreme environments such as metal, underwater, underground, building collapse, and so on, and solves the problems of existing wireless communication in which reception rate varies greatly depending on the medium.

In a conventional magnetic field communication system, since a carrier is generated using an oscillator and a received signal is received from a receiver using a sinusoidal signal generated using a phase-locked loop (PLL) chip, There is a problem in that the circuit structure is complicated and the manufacturing price is high. In particular, the PLL chip has a problem that the carrier frequency can not be changed arbitrarily as well as expensive. In addition, the conventional magnetic field communication system has a limitation that the communication range is narrow.

The technical problem to be achieved by the present invention is to widen the communication range by using a current amplifier in the transmitter, the carrier in the transmitter generates a carrier using the internal clock of the field programmable gate array (FPGA), the received signal in the receiver Demodulated using a sine wave and a cosine wave generated by using an internal clock signal of the demodulated signal. It is to provide a magnetic field communication system and a magnetic field communication transmitter and magnetic field communication receiver used in the system that can simplify the structure and lower the manufacturing cost by decoding each of the signals.

The magnetic field communication system according to an embodiment of the present invention includes a magnetic field communication transmitter and a magnetic field communication receiver, wherein the magnetic field communication transmitter encodes a data signal and mixes the encoded signal with a carrier frequency sinusoidal signal to generate a transmission signal. And transmits the transmission signal to an external magnetic field communication system through a magnetic field communication channel using an antenna, and the magnetic field communication receiver uses the antenna to transmit a magnetic field signal transmitted from the external magnetic field communication system through the magnetic field communication channel. And demodulate the magnetic field signal by using a carrier frequency sinusoidal signal and a carrier frequency sinusoidal signal, respectively, and output each of a plurality of baud rate clock signals having different phases for each of the demodulated signals. To decode.

The difference between the phase of the carrier frequency sinusoidal signal and the phase of the carrier frequency sinusoidal signal may be 90 degrees, and the phase difference between the plurality of baud rate clock signals may be 90 degrees.

The magnetic field communication transmitter may amplify and transmit the current of the transmission signal.

Each of the carrier frequency sinusoidal signal and the carrier frequency sinusoidal signal may be generated by dividing an internal clock signal of a field programmable gate array (FPGA), converting the divided signal, and each of the plurality of baud rate clock signals It may be generated by dividing the internal clock signal of the FPGA.

Magnetic field communication transmitter according to an embodiment of the present invention encodes a data signal, FPGA (Field Programmable Gate Arrat) for outputting the encoded signal and the carrier frequency clock signal; Regulating the encoded signal, converting the carrier frequency clock signal into a carrier frequency sinusoidal signal, and mixing the regulated encoded signal with the carrier frequency sinusoidal signal to generate a transmission signal, the transmission signal A modulator for outputting a; And a transmitter for amplifying the transmission signal and transmitting the amplified transmission signal through a magnetic field communication channel.

The FPGA comprises a data input module for receiving the data signal; A carrier frequency division module for dividing the internal clock signal of the FPGA at a carrier frequency to generate the carrier frequency clock signal; A baud rate division module for generating a baud rate clock signal by dividing the internal clock signal of the FPGA at a baud rate; And an encoding module for mixing the data signal and the baud rate clock signal to generate the encoded signal.

The modulator may include a low pass filter converting the carrier frequency clock signal into the carrier frequency sine wave signal; A voltage level regulator regulating the encoded signal; And a mixer for mixing the carrier frequency sinusoidal signal with the regulated encoded signal to generate the transmission signal.

The transmitter includes a voltage amplifier for amplifying a voltage of the transmission signal; A current amplifier for amplifying the current of the transmission signal output from the voltage amplifier; And a transmission antenna configured to transmit the transmission signal output from the current amplifier through the magnetic field communication channel.

In accordance with another aspect of the present invention, a magnetic field communication receiver includes: a receiver configured to receive a magnetic field signal from a magnetic field communication transmitter through a magnetic field communication channel, remove noise of the magnetic field signal, and output an amplified received signal; Converts a first carrier frequency clock signal into a carrier frequency sinusoidal signal, converts a second carrier frequency clock signal into a carrier frequency sinusoidal signal, mixes the received signal with the carrier frequency sinusoidal signal, and outputs a first demodulated signal; A demodulator for mixing the received signal with the carrier frequency cosine wave signal to output a second demodulated signal; And outputting the first carrier frequency clock signal and the second carrier frequency clock signal, wherein data is present among signals generated by mixing the first demodulation signal with each of a plurality of baud rate clock signals. Selecting a signal as a first output signal, selecting a signal having data from among signals generated by mixing the second demodulation signal with each of the plurality of baud rate clock signals, and selecting the first output signal as the second output signal. And a field programmable gate array (FPGA) for outputting at least one of the output signal and the second output signal that satisfies a preamble condition as at least one data signal.

The demodulator comprises: a plurality of first low pass filters for converting the first carrier frequency clock signal into the carrier frequency sinusoidal signal and converting the second carrier frequency clock signal into the carrier frequency cosine wave signal; A plurality of mixers for mixing the received signal with the carrier frequency sinusoidal signal to generate a first baseband signal, and for mixing the received signal with the carrier frequency sinusoidal signal to generate a second baseband signal; A plurality of second low pass filters to remove high frequency noise of each of the first baseband signal and the second baseband signal; A plurality of second amplifiers each amplifying the first baseband signal and the second baseband signal output from each of the plurality of second lowpass filters; A plurality of analog-to-digital converters converting the first baseband signal and the second baseband signal output from each of the plurality of second amplifiers into digital signals and outputting the first demodulated signal and the second demodulated signal; Can include them.

The FPGA may include: a first carrier frequency division module for dividing an internal clock signal of the FPGA at a carrier frequency to generate the first carrier frequency clock signal; A second carrier frequency division module for dividing the internal clock signal of the FPGA at the carrier frequency to generate the second carrier frequency clock signal; A first baud rate division module for dividing the internal clock signal of the FPGA at a baud rate to generate a first baud rate clock signal; A second baud rate division module for dividing the internal clock signal of the FPGA at the baud rate to generate a second baud rate clock signal; A plurality of agents generating a first output signal by mixing the first demodulation signal and the first baud rate clock signal, and generating a second output signal by mixing the first demodulation signal and the second baud rate clock signal; 1 output modules; A plurality of agents generating a third output signal by mixing the second demodulation signal and the first baud rate clock signal, and generating a fourth output signal by mixing the second demodulation signal and the second baud rate clock signal; 2 output modules; A first selection module configured to select and output a signal in which data exists among the first output signal and the second output signal; A second selection module configured to select and output a signal in which data exists among the third output signal and the fourth output signal; And a decoding module configured to output, as a data signal, a signal satisfying a preamble condition among a signal output from the first selection module and a signal output from the second selection module.

Magnetic field communication system according to an embodiment of the present invention, and the magnetic field communication transmitter and magnetic field communication receiver used in the system has the effect of extending the communication range of the magnetic field communication, simplify the structure and reduce the manufacturing cost.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more fully understand the drawings recited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a view for explaining a magnetic field communication system according to an embodiment of the present invention.
2 is a schematic block diagram of a magnetic field communication transmitter according to an embodiment of the present invention.
FIG. 3 is a schematic block diagram of a field programmable gate array (FPGA) shown in FIG. 2.
4 is a schematic block diagram of a modulator shown in FIG. 2.
FIG. 5 is a schematic block diagram of the transmitter of FIG. 2.
6 is a diagram illustrating a magnetic field communication receiver according to an exemplary embodiment of the present invention.
FIG. 7 is a schematic block diagram of a receiver shown in FIG. 6.
8 is a schematic block diagram of a demodulator shown in FIG. 6.
FIG. 9 is a schematic block diagram of a field programmable gate array (FPGA) shown in FIG. 6.
FIG. 10 is a circuit diagram of an antenna shown in FIG. 1, 5, or 7, respectively.

It is to be understood that the specific structural or functional descriptions of embodiments of the present invention disclosed herein are only for the purpose of illustrating embodiments of the inventive concept, But may be embodied in many different forms and is not limited to the embodiments set forth herein.

Embodiments in accordance with the concepts of the present invention are capable of various modifications and may take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a view for explaining a magnetic field communication system according to an embodiment of the present invention.

Referring to FIG. 1, the magnetic field communication system 100 includes a first magnetic field communication system 200-1 and a second magnetic field communication system 200-2 communicating with each other through a magnetic field communication channel 600.

The first magnetic field communication system 200-1 includes a first magnetic field communication transmitter 300-1, a first magnetic field communication receiver 400-1, and a first antenna 500-1.

The first magnetic field communication transmitter 300-1 encodes a data signal, mixes the encoded signal with a carrier frequency sinusoidal signal, generates a transmission signal, and transmits the transmission signal to the first antenna 500-1. Is transmitted to the second magnetic field communication system 300-2 through the magnetic field communication channel 600.

The first magnetic field communication receiver 400-1 receives a magnetic field signal transmitted from the second magnetic field communication system 300-2 through the magnetic field communication channel 600 by using the first antenna 500-1. The magnetic field signal is demodulated using each of the carrier frequency sinusoidal signal and the carrier frequency sinusoidal signal, and decoded using each of a plurality of baud rate clock signals having different phases for each of the demodulated signals.

The difference between the phase of the carrier frequency sinusoidal signal and the phase of the carrier frequency sinusoidal signal may be 90 degrees, and the phase difference between the plurality of baud rate clock signals may be 90 degrees.

When the phase difference between the magnetic field signal and the carrier frequency sinusoidal signal is 0 degrees, Equation 1 is established when the first magnetic field communication receiver 400-1 mixes and demodulates the magnetic field signal and the carrier frequency sinusoidal signal.

[Equation 1]

Where f _c represents a carrier frequency, T represents a period, and t represents time.

When the phase difference between the magnetic field signal and the carrier frequency sinusoidal signal is 90 degrees, Equation 2 is established when the first magnetic field communication receiver 400-1 mixes and demodulates the magnetic field signal and the carrier frequency sinusoidal signal.

&Quot; (2) "

Where f _c represents a carrier frequency, T represents a period, and t represents time.

That is, when the first magnetic field communication receiver 400-1 mixes each of the carrier frequency sinusoidal signal, the carrier frequency cosine wave signal, and the magnetic field signal, when one demodulation signal is 0, the other demodulation signal is 1/2. It has a value of T.

The first magnetic field communication receiver 400-1 has a demodulation rate of about 70% or more even when the demodulation rate is the lowest, for example, when the phase difference is 45 degrees. Therefore, the magnetic field communication receiver 400-1 of the present invention can demodulate the magnetic field signal using each of the carrier frequency sinusoidal signal and the carrier frequency sinusoidal signal without using a PLL chip, thereby simplifying the circuit and reducing the manufacturing cost. It can be effective.

The first magnetic field communication transmitter 300-1 may amplify and transmit a current of the transmission signal. Since a high current is supplied to the first antenna 500-1 by amplifying the current of the transmission signal, the first antenna 500-1 can generate a strong magnetic field, thereby widening the communication range of the magnetic field communication system 100. have.

Each of the carrier frequency sinusoidal signal and the carrier frequency sinusoidal signal may be generated by dividing an internal clock signal of the FPGA and converting the divided signal, for example, low pass filtering, each of the plurality of baud rate clock signals of the FPGA. It may be generated by dividing the internal clock signal.

Therefore, since the first magnetic field communication system 200-1 can perform magnetic field communication without including an oscillator, the first magnetic field communication system 200-1 can simplify the circuit and reduce the manufacturing cost.

Since the structure of the second magnetic field communication system 200-2 is the same as that of the first magnetic field communication system 200-1, a description of the same parts will be omitted.

2 is a schematic block diagram of a magnetic field communication transmitter according to an embodiment of the present invention.

Referring to FIG. 2, the magnetic field communication transmitter 300 implemented as an embodiment of the first magnetic field communication transmitter 300-1 and the second magnetic field communication transmitter 300-1 shown in FIG. 1 includes an FPGA 340, The modulator 360 and the transmitter 380 are included.

The FPGA 340 encodes the data signal DS received from the input device 320 and outputs the encoded signal EDS and the carrier frequency clock signal CFC.

The modulator 360 regulates the encoded signal EDS output from the FPGA 340, and converts the carrier frequency clock signal CFC output from the FPGA 340 into a carrier frequency sine wave signal CFS. The regulated encoded signal (REDS) and the carrier frequency sinusoidal signal (CFS) are mixed to generate a transmission signal (SS '), and outputs the transmission signal (SS').

The transmitter 380 amplifies the transmission signal SS ′ output from the modulator 360, and transmits the amplified transmission signal SS to the magnetic field communication channel 600 using the transmission antenna 386 shown in FIG. 5. Send via).

The transmitting antenna 386 shown in FIG. 5 is the same antenna as the first antenna 500-1 or the second antenna 500-2 shown in FIG. 1.

3 is a schematic block diagram of the FPGA shown in FIG.

2 and 3, the FPGA 340 may include a data input module 342, a carrier frequency division module 344, a baud rate division module 346, and an encoding module 348.

A module in the present specification may mean hardware capable of performing functions and operations according to each name described in the present specification, or computer program code capable of performing specific functions and operations. It may mean, or may mean, an electronic recording medium, for example, a processor, on which computer program code is capable of performing specific functions and operations.

In other words, a module may mean a functional and / or structural combination of hardware for performing the technical idea of the present invention and / or software for driving the hardware.

The data input module 342 receives the data signal DS from the input device 320.

The carrier frequency division module 344 divides the internal clock signal CLK of the FPGA 340 into a carrier frequency to generate a carrier frequency clock signal CFC.

For example, when the internal clock signal CLK of the FPGA 340 is 50 MHz and the carrier frequency is 125 kHz, the internal clock signal CLK of the FPGA 340 is divided by the division ratio 200 to generate a carrier frequency clock signal of 125 kHz ( CFC).

The baud rate division module 346 divides the internal clock signal CLK of the FPGA at a baud rate to generate a baud rate clock signal BRC.

For example, when the internal clock signal CLK of the FPGA 340 is 50 MHz and the baud rate is 1 kHz, the internal clock signal CLK of the FPGA 340 is divided at a division ratio of 25000 to give a baud rate clock signal of 1 kHz ( BRC).

The encoding module 348 mixes the encoded signal EDS by mixing the data signal DS output from the data input module 342 and the baud rate clock signal BRC output from the baud rate division module 346. Occurs.

The encoding module 348 may start the start bit (start) in the data signal DS output from the data input module 342 to determine whether the preamble condition is satisfied in the magnetic field communication receiver 400 illustrated in FIG. 6. At least one of a bit / end bit, a frame check bit, and an error correction bit may be added and encoded.

4 is a schematic block diagram of a modulator shown in FIG. 2.

2 and 4, the modulator 360 includes a low pass filter 362, a voltage level regulator 364, and a mixer 366.

The low pass filter 362 converts the carrier frequency clock signal CFC output from the FPGA 340 into a carrier frequency sinusoidal signal CFS.

The voltage level regulator 364 regulates the encoded signal EDS output from the FPGA 340.

The mixer 366 mixes the carrier frequency sinusoidal signal CFS output from the low pass filter 362 and the regulated encoded signal REDS output from the voltage level regulator 364.

FIG. 5 is a schematic block diagram of the transmitter of FIG. 2.

2 and 5, the transmitter 380 includes a voltage amplifier 382, a current amplifier 384, and a transmit antenna 386.

The voltage amplifier 382 amplifies the voltage of the transmission signal SS 'output from the modulator 360.

The current amplifier 384 amplifies the current of the transmission signal SS '' output from the voltage amplifier 382.

The transmit antenna 386 transmits the transmission signal SS output from the current amplifier 384 through the magnetic field communication channel 600.

6 is a diagram illustrating a magnetic field communication receiver according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the magnetic field communication receiver 400 implemented in each of the first magnetic field communication receiver 400-1 and the second magnetic field communication receiver 400-2 shown in FIG. 1 includes a receiver 420. , Demodulator 440 and FPGA 460.

The receiver 420 receives the magnetic field signal SS from the magnetic field communication transmitter 300 through the magnetic field communication channel 600, removes and amplifies the noise of the magnetic field signal SS, and amplifies the received signal RS. Outputs

The demodulator 440 converts the first carrier frequency clock signal CFC1 output from the FPGA 460 into a carrier frequency sine wave signal SIN, and the second carrier frequency clock signal CFC2 output from the FPGA 460. Is converted into a carrier frequency sinusoidal signal COSIN, and the first demodulated signal DMS1 is output by mixing the received signal RS output from the receiver 420 with the carrier frequency sinusoidal signal SIN. The second demodulation signal DMS2 is output by mixing the reception signal RS and the carrier frequency cosine wave signal COSIN.

The FPGA 460 outputs a first carrier frequency clock signal CFC1 and a second carrier frequency clock signal CFC2, and outputs a plurality of baud rate clock signals from the first demodulation signal DMS1 output from the demodulator 440. Selects a signal having data among the signals generated by mixing with each of BRC1 and BRC2 as the first selection signal SS1 and selects a plurality of second demodulation signals DMS2 output from the demodulator 440. A signal having data among the signals generated by mixing with each of the baud rate clock signals BRC1 and BRC2 is selected as the second selection signal SS2, and the first selection signal SS1 and the second selection are selected. At least one of the signals SS2 that meets a preamble condition is output as at least one data signal DS ′.

FIG. 7 is a schematic block diagram of a receiver shown in FIG. 6.

6 and 7, the receiver 420 includes a reception antenna 422, a band pass filter 424, and an amplifier 426.

The transmit antenna 386 is the same antenna as the first antenna 500-1 or the second antenna 500-2 shown in FIG. 1.

The receiving antenna 422 receives the magnetic field signal SS from the magnetic field communication transmitter 300 through the magnetic field communication channel 600.

The bandpass filter 424 removes noise from the magnetic field signal SS output from the receiving antenna 422.

The amplifier 426 generates the reception signal RS by amplifying the magnetic field signal SS 'from which the noise output from the band pass filter 424 is removed.

8 is a schematic block diagram of a demodulator shown in FIG. 6.

6 and 8, the demodulator 440 includes a plurality of first low pass filters 442-1 and 442-2, a plurality of mixers 444-1 and 444-2, and a plurality of first Two low pass filters 446-1, 446-2, a plurality of second amplifiers 448-1, 448-2, and a plurality of analog-to-digital converters 450-1, 450-2. .

The first low pass filter 442-1 converts the first carrier frequency clock signal CFC1 output from the FPGA 460 into a carrier frequency sinusoidal signal SIN, and the first low pass filter 442-2 The second carrier frequency clock signal CFC2 output from the FPGA 460 is converted into a carrier frequency cosine wave signal COSIN.

The mixer 444-1 generates the first baseband signal BBS1 by mixing the received signal RS output from the receiver 420 with the carrier frequency sine wave signal SIN, and the mixer 444-2 generates the first baseband signal BBS1. The received signal RS is mixed with the carrier frequency cosine wave signal COSIN to generate a second baseband signal BBS2.

Each of the plurality of second low pass filters 446-1 and 448-2 may include a first baseband signal BBS1 and a second baseband signal output from each of the plurality of mixers 444-1 and 444-2. BBS2) Remove each high frequency noise.

Each of the plurality of second amplifiers 448-1 and 448-2 may include the first baseband signal BBS1 ′ and the first baseband signal output from each of the plurality of second low pass filters 446-1 and 446-2. Amplify each of the two baseband signals BBS2 '.

Each of the plurality of analog-to-digital converters 450-1 and 450-2 may include a first baseband signal BBS1 ″ and a second baseband output from each of the plurality of second amplifiers 448-1 and 448-2. Each of the baseband signals BBS2 ″ is converted into a digital signal and output as a first demodulated signal DMS1 and a second demodulated signal DMS2.

9 is a schematic block diagram of the FPGA shown in FIG. 6.

6 and 9, the FPGA 460 includes a first carrier frequency module 462, a second carrier frequency division module 464, a first baud rate division module 466, and a second baud rate division module ( 468, a plurality of first output modules 470-1 and 470-2, a plurality of second output modules 472-1 and 472-2, a first selection module 474, and a second selection module ( 476 and decoding module 478.

The first carrier frequency division module 462 divides the internal clock signal CLK 'of the FPGA 460 into a carrier frequency to generate a first carrier frequency clock signal CFC1.

The second carrier frequency division module 464 divides the internal clock signal CLK 'of the FPGA 460 at the carrier frequency to generate a second carrier frequency clock signal CFC2.

Each of the first carrier frequency dividing module 462 and the second carrier dividing module 464 selects an initial value differently so that the phase of the first carrier frequency clock signal CFC1 and the phase of the second carrier frequency clock signal CFC2 are respectively different. Happens differently.

For example, when the internal clock signal CLK 'of the FPGA 460 is 50 MHz and the carrier frequency is 125 kHz, the internal clock signal CLK' of the FPGA 460 is divided by the division ratio 200 to generate a 125 kHz clock signal. Occurs.

The first baud rate division module 466 divides the internal clock signal CLK 'of the FPGA 460 at a baud rate to generate a first baud rate clock signal BRC1.

The second baud rate division module 468 divides the internal clock signal CLK 'of the FPGA 460 at a baud rate to generate a second baud rate clock signal BRC2.

For example, when the internal clock signal CLK 'of the FPGA 460 is 50 MHz and the baud rate is 1 kHz, the internal clock signal CLK' of the FPGA 460 is divided at a division ratio of 25000 to generate a 1 kHz clock signal. Occurs.

The first output module 470-1 mixes the first demodulation signal DMS1 output from the demodulator 440 and the first baud rate clock signal BRC1 output from the first baud rate division module 466. The first output signal OS1 is generated, and the first output module 470-2 generates a second baud rate clock signal BRC2 output from the first demodulation signal DMS1 and the second baud rate division module 468. ) Is mixed to generate a second output signal OS2.

The second output module 472-1 mixes the second demodulation signal DMS2 output from the demodulator 440 and the first baud rate clock signal BRC1 output from the first baud rate division module 466. A third output signal OS3 is generated, and the second output module 472-2 generates a second baud rate clock signal BRC2 output from the second demodulation signal DMS2 and the second baud rate division module 468. ) Is mixed to generate a fourth output signal OS4.

Each of the plurality of first output modules 470-1 and 470-2 is output from the demodulator 440 during one clock of each of the first baud rate clock signal BRC1 and the second baud rate clock signal BRC2. The case where the first demodulation signal DMS1 is 1 is counted. If the count result is greater than or equal to the reference value, each of the first output signal OS1 and the second output signal OS2 is generated as 1, otherwise, it is generated as 0.

For example, when the carrier frequency is 125 kHz and the baud rate is 1 kHz, each of the plurality of first output modules 470-1 and 470-2 may include a first baud rate clock signal BRC1 and a second baud rate clock signal ( BRC2) The first demodulation signal DMS1 output from the demodulator 440 is counted using a carrier frequency clock signal CFC 'having a frequency of 125 kHz for one clock (1 ms). When the count result is 56 or more times, the first output signal OS1 is generated as 1, otherwise the first output signal OS2 is generated as 0.

Since the structure of each of the plurality of second output modules 472-1 and 472-2 is the same as that of each of the plurality of first output modules 470-1 and 470-2, a description of the same part is omitted.

The first selection module 474 may output a signal having data among the first output signal OS1 and the second output signal OS2 output from each of the plurality of first output modules 470-1 and 470-2. Select and output the first selection signal SS1.

The second selection module 476 may output a signal in which data exists among the third output signal OS3 and the fourth output signal OS4 output from each of the plurality of second output modules 472-1 and 472-2. It selects and outputs it as the 2nd selection signal SS2.

Each of the first selection module 474 and the second selection module 476 receives a plurality of output signals and considers the data to exist if bit 1 is present at least once during a unit frame among the plurality of output signals.

The decoding module 478 outputs a data signal DS ′ that satisfies a preamble condition among the signal SS1 output from the first selection module 474 and the signal SS2 output from the second selection module 476. Will output

The decoding module 478 selects the first selection when the phase of the carrier frequency sinusoidal signal SIN of the magnetic field communication transmitter 300 and the phase of the carrier frequency sinusoidal signal SIN of the magnetic field communication receiver 400 differ by 180 degrees. Any one of the signal SS1 output from the module 474 or the signal SS2 output from the second selection module 476 is reversed by the input signal received from the input device in the magnetic field communication transmitter 300. Since 0 may be output as 1 and 1 may be output as 0, the signal SS1 output from the first selection module 474 and the signal SS2 output from the second selection module 476 when determining the preamble condition. We can also consider a signal in which each bit is reversed.

10 is a circuit diagram of the antenna shown in FIG. 1, 5, or 7, respectively.

1, 5, 7 and 10, the antennas 500-1, 500-2, the transmit antenna 386, and the receive antenna 422 are each loop antennas, and thus may be represented by an inductor 720. It may include a capacitor 740 having a capacitance to configure a resonant circuit at a carrier frequency.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

200: magnetic field communication system
300: magnetic field communication transmitter
400: magnetic field communication receiver
340: FPGA
360: modulator
380: transmitter
420: receiver
440: demodulator
460: FPGA

Claims (11)

In a magnetic field communication system comprising a magnetic field communication transmitter and a magnetic field communication receiver,
The magnetic field communication transmitter,
Encodes a data signal, mixes the encoded signal with a carrier frequency sinusoidal signal to generate a transmission signal, and transmits the transmission signal to an external magnetic field communication system through a magnetic field communication channel using an antenna,
The magnetic field communication receiver,
Receives a magnetic field signal transmitted from the external magnetic field communication system through the magnetic field communication channel using the antenna, demodulates the magnetic field signal using a carrier frequency sinusoidal signal and a carrier frequency cosine wave signal, and demodulates the signal. Decode using each of a plurality of baud rate clock signals having different phases for each of
Each of the carrier frequency sinusoidal signal and the carrier frequency sinusoidal signal is generated by dividing an internal clock signal of a field programmable gate array (FPGA) and converting the divided signal,
And each of the plurality of baud rate clock signals is generated by dividing the internal clock signal of the FPGA. The method of claim 1,
And a phase difference between a phase of the carrier frequency sinusoidal signal and a phase of the carrier frequency sinusoidal signal is 90 degrees, and a phase difference between the plurality of baud rate clock signals is 90 degrees. The method of claim 1,
The magnetic field communication transmitter amplifies and transmits the current of the transmission signal to the magnetic field communication system delete A field programmable gate array (FPGA) for encoding a data signal and outputting an encoded signal and a carrier frequency clock signal;
Regulating the encoded signal, converting the carrier frequency clock signal into a carrier frequency sinusoidal signal, and mixing the regulated encoded signal with the carrier frequency sinusoidal signal to generate a transmission signal, the transmission signal A modulator for outputting a; And
And a transmitter for amplifying the transmission signal and transmitting the amplified transmission signal through a magnetic field communication channel. 6. The method of claim 5,
The FPGA,
A data input module to receive the data signal;
A carrier frequency division module for dividing the internal clock signal of the FPGA at a carrier frequency to generate the carrier frequency clock signal;
A baud rate division module for generating a baud rate clock signal by dividing the internal clock signal of the FPGA at a baud rate; And
And an encoding module for mixing the data signal and the baud rate clock signal to generate the encoded signal. 6. The method of claim 5,
The modulator,
A low pass filter converting the carrier frequency clock signal into the carrier frequency sinusoidal signal;
A voltage level regulator regulating the encoded signal; And
And a mixer for mixing the carrier frequency sinusoidal signal and the regulated encoded signal to generate the transmission signal. 6. The method of claim 5,
The transmitting unit,
A voltage amplifier for amplifying the voltage of the transmission signal;
A current amplifier for amplifying the current of the transmission signal output from the voltage amplifier; And
And a transmission antenna for transmitting the transmission signal output from the current amplifier through the magnetic field communication channel. A receiver which receives a magnetic field signal from a magnetic field communication transmitter through a magnetic field communication channel, removes noise of the magnetic field signal, and outputs an amplified received signal;
Converts a first carrier frequency clock signal into a carrier frequency sinusoidal signal, converts a second carrier frequency clock signal into a carrier frequency sinusoidal signal, mixes the received signal with the carrier frequency sinusoidal signal, and outputs a first demodulated signal; A demodulator for mixing the received signal with the carrier frequency cosine wave signal to output a second demodulated signal; And
A signal in which data exists among signals generated by outputting the first carrier frequency clock signal and the second carrier frequency clock signal, and mixing the first demodulation signal with each of a plurality of baud rate clock signals. Is selected as a first selection signal, and among the signals generated by mixing the second demodulation signal with each of the plurality of baud rate clock signals, a signal having data is selected as a second selection signal, and the first output signal. And a field programmable gate array (FPGA) for outputting at least one of a signal and the second output signal that satisfies a preamble condition as at least one data signal. The method of claim 9,
The demodulation unit,
A plurality of first low pass filters converting the first carrier frequency clock signal into the carrier frequency sinusoidal signal and converting the second carrier frequency clock signal into the carrier frequency sinusoidal signal;
A plurality of mixers for mixing the received signal with the carrier frequency sinusoidal signal to generate a first baseband signal, and for mixing the received signal with the carrier frequency sinusoidal signal to generate a second baseband signal;
A plurality of second low pass filters to remove high frequency noise of each of the first baseband signal and the second baseband signal;
A plurality of second amplifiers each amplifying the first baseband signal and the second baseband signal output from each of the plurality of second lowpass filters;
A plurality of analog-to-digital converters converting the first baseband signal and the second baseband signal output from each of the plurality of second amplifiers into digital signals and outputting the first demodulated signal and the second demodulated signal; Magnetic field communication receiver comprising a. The method of claim 9,
The FPGA,
A first carrier frequency division module for dividing an internal clock signal of the FPGA at a carrier frequency to generate the first carrier frequency clock signal;
A second carrier frequency division module for dividing the internal clock signal of the FPGA at the carrier frequency to generate the second carrier frequency clock signal;
A first baud rate division module for dividing the internal clock signal of the FPGA at a baud rate to generate a first baud rate clock signal;
A second baud rate division module for dividing the internal clock signal of the FPGA at the baud rate to generate a second baud rate clock signal;
A plurality of agents generating a first output signal by mixing the first demodulation signal and the first baud rate clock signal, and generating a second output signal by mixing the first demodulation signal and the second baud rate clock signal; 1 output modules;
A plurality of agents generating a third output signal by mixing the second demodulation signal and the first baud rate clock signal, and generating a fourth output signal by mixing the second demodulation signal and the second baud rate clock signal; 2 output modules;
A first selection module configured to select and output a signal in which data exists among the first output signal and the second output signal;
A second selection module configured to select and output a signal in which data exists among the third output signal and the fourth output signal; And
And a decoding module configured to output, as a data signal, a signal satisfying a preamble condition among a signal output from the first selection module and a signal output from the second selection module.

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