KR101226344B1 - Data Transmission Systems and Driving Mehtod Thereof - Google Patents

Abstract

The present invention relates to a data transmission system that can stably restore data.
The data transmission system of the present invention includes a transmitter for transmitting data and a reference clock; A receiver comprising a plurality of receivers, the receiver receiving the data and the reference clock from the transmitter; Each of the receivers compares a current bit with a previous bit of the data supplied to the receiver and outputs any one of a high signal, a low signal, and a middle signal in response to the comparison result, where j is a natural number of 2 or more. ) Comparators; A data determination unit is connected to an output terminal of each of the comparators and outputs one of the current bit and the previous bit in response to an output signal of the comparator.

Description

Data Transmission Systems and Driving Methods {Data Transmission Systems and Driving Mehtod Thereof}

The present invention relates to a data transmission system and a driving method thereof, and more particularly, to a data transmission system and a driving method thereof capable of stably restoring data.

In general DRAM systems, a multi-drop single-ended signaling scheme is used for communication between a memory controller and a plurality of DRAM chips.

Multi-drop single-ended signaling is a method of connecting a memory controller and a plurality of DRAM chips using one channel. This method has an advantage of minimizing the number of channels for data transmission.

In general, in a multi-drop single-ended signaling scheme, an equalizer or an encoder is used to solve the problem of inter-symbol interference (ISI) and noise of a reference signal. However, when using an equalizer or an encoder, there is a problem in that the circuit mounting area and power consumption are increased.

Accordingly, an object of the present invention is to provide a data transmission system and a method of driving the same, which can stably restore data without using an equalizer or an encoder.

A data transmission system according to an embodiment of the present invention includes a transmitter for transmitting data and a reference clock; A receiver comprising a plurality of receivers, the receiver receiving the data and the reference clock from the transmitter; Each of the receivers compares a current bit with a previous bit of the data supplied to the receiver and outputs any one of a high signal, a low signal, and a middle signal in response to the comparison result, where j is a natural number of 2 or more. ) Comparators; A data determination unit is connected to an output terminal of each of the comparators and outputs one of the current bit and the previous bit in response to an output signal of the comparator.

Preferably, the comparator may determine that the high signal when the current bit is greater than the previous bit, the low signal when the current bit is less than the previous bit, and that the current bit and the previous bit are the same. When the middle signal is output. The comparator sets the voltage of the high signal to 100% and sets the voltage of the low signal to 0%, when the previous bit and the current bit have a voltage difference within ± 20%. It is determined that the previous bit is the same. The receiving unit includes a synchronous loop circuit for generating j first clock signals having a predetermined phase difference sequentially using the reference clock. Each of the first clock signals is set to a 1 / j frequency in comparison with the transmission frequency of the data.

The first clock signals sequentially overlap a high period by one bit supply time of the data. And a pulse generator for generating j second clock signals by performing an AND operation on the first clock signals adjacent to each other. A first capacitor connected to a first input terminal of each of the comparators, a second capacitor connected to a second input terminal of each of the comparators, a connection between each of the second input terminals and the transmitter, and the first capacitor And a first switch that is turned off when either of the two clock signals is supplied. The first switch is turned off when the current bit is input to the first capacitor so that the previous bit can be stored in the second capacitor.

Each of the data determination units includes a first storage unit for storing an output signal of the comparator, a transition detector for outputting a high signal or a low signal corresponding to the output signal of the comparator, and an output signal of the transition detector. A second storage unit, a selection unit for outputting a signal stored in the first storage unit or a previous data determination unit in response to an output signal of the second storage unit, and a third storage unit in which the output signal of the selection unit is stored Equipped. The transition detector outputs a high signal when the high signal and a low signal are input from the comparator, and outputs a low signal when the middle signal is input. The selector outputs a signal stored in the first storage unit when a high signal is input from the second storage unit, and outputs a signal of the previous data determination unit when a low signal is input. And a level shifter positioned between the second storage unit and the selection unit to change a voltage level of a signal stored in the second storage unit. The previous data determiner is a data determiner that outputs the previous bit. The first storage unit and the second storage unit receive the same second clock signal. The first storage unit receives a second clock signal different from the first switch connected to the comparator. The third storage unit receives a second clock signal identical to the first switch connected to the comparator.

The transition detection unit includes a ninth transistor connected between a first power supply and a first node to maintain a turn-on state; An eighth transistor connected between the first power supply and the second node and maintaining a turn-on state; A fourth transistor connected between the first node and a third node, the fourth transistor being turned on and off by a voltage supplied to a first input terminal; A seventh transistor connected between the first node and the fourth node and turned on and off by a voltage supplied to a second input terminal; A second transistor connected between the third node and a fifth node and having a gate electrode connected to the first input terminal; A third transistor connected between the fourth node and a fifth node and having a gate electrode connected to the second input terminal; A first transistor connected between the fifth node and a base power source and configured to flow a predetermined current from the fifth node to the base power source in response to a bias voltage; A fifth transistor connected between the second node and the third node and having a gate electrode connected to a reference power source; And a sixth transistor connected between the second node and the fourth node and having a gate electrode connected to the reference power supply.

The first input terminal receives the output signal of the first comparator. The second input terminal receives a low signal when the high signal is supplied to the first input terminal, receives a high signal when the low signal is supplied, and receives the same middle signal when the middle signal is supplied. When the middle signal is input to the first input terminal and the second input terminal, the reference power source is configured so that the fourth transistor and the seventh transistor are turned off, and the middle and fifth transistors are turned on. And a voltage between the high signal. The previous bit is an i (i is a natural number) bit, and the current bit is an i + 1 th bit.

A method of driving a data transmission system according to an embodiment of the present invention includes the steps of transmitting data from a transmitter to a receiver, storing i (i is a natural number) -1th bit of the data, and i-th bit of the data. And comparing the i-th bit. Outputting the i th bit when it is determined that the i th bit and the i-1 th bit are different; and the i-1 th bit when it is determined that the i th bit and the i-1 th bit are the same. It includes the step of outputting.

According to the data transmission system and driving method thereof of the present invention, the current bit is compared based on the previous bit and the previous bit or the current bit is output in response to the comparison result. There is an advantage to restore. In addition, in the present invention, since no equalizer or encoder is used, chip area and power consumption can be minimized.

1 is a view showing a data transmission system according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an embodiment of the receiver shown in FIG. 1.
3 is a waveform diagram illustrating an operation of the receiver illustrated in FIG. 2.
4 is a circuit diagram illustrating an embodiment of the transition detector shown in FIG. 2.
5 is a diagram illustrating a voltage of the reference power source shown in FIG. 4.
6 is a view showing a simulation result of a data transmission system according to an embodiment of the present invention.
7 is a flowchart schematically illustrating a method of driving a data transmission system of the present invention.

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 to 7 to which a preferred embodiment for easily carrying out the present invention by those skilled in the art.

1 is a view showing a data transmission system according to an embodiment of the present invention.

Referring to FIG. 1, a data transmission system according to an embodiment of the present invention includes a transmitter 100 and a receiver 200.

The transmitter 100 transmits the data Data and the reference clock Ref_CLK to the receiver 200 using the multi-drop channel 110. The transmitting unit 100 may be selected as a memory controller.

The receiver 200 includes a plurality of receivers 210, 220, 230... And a sync loop circuit 202 (PLL circuit). Each of the receivers 210, 220, 230 ... includes j comparators 211a through 214a and data determination units 221b through 224b. In the drawings and description of the present invention, j is set to 4 for convenience, but the present invention is not limited thereto.

The sync loop circuit 202 generates j clock signals (or first clock signals) that are sequentially out of phase using the reference clock Ref_CLK. The clock signal generated by the synchronous loop circuit 202 is set to 1 / j frequency in comparison with the supply frequency of data. Here, when j is set to 4, the synchronous loop circuit 202 sequentially rotates the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock so that a phase difference of 90 degrees occurs. Generate signal CLK4. In this case, clock signals adjacent to each other (that is, CLK1 and CLK2, CLK2 and CLK3, CLK3 and CLK4, CLK4 and CLK1) overlap by one bit supply time of data.

The comparators 211a to 214a compare the previous bit (i (i is a natural number) -1st bit) of the data with the current bit (i-th bit), and correspond to a high, low or Output the middle signal. For example, the comparators 211a to 214a output a high or low signal when it is determined that the previous bit and the current bit are different, and output a middle signal when it is determined that the previous bit and the current bit are the same. Here, the comparators 211a to 214a set the voltage of the high signal to 100% and the voltage of the low signal to 0%, if the previous bit and the current bit have a voltage difference within ± 20%. It is determined that the previous bit is the same.

The data determination units 221b to 224b output one of the previous bit and the current bit in response to the comparison result of the comparators 211a to 214a. To this end, each of the data determination units 221b, 222b, 223b, and 224b is supplied with the outputs of the previous data determination units 224b, 221b, 222b, and 223b and the outputs of the comparators 211a to 214a connected thereto.

FIG. 2 is a diagram illustrating an embodiment of the receiver shown in FIG. 1. In FIG. 2, two comparators 211a and 212a and data determination units 221b and 222b included in the first receiver 210 will be shown for convenience of description.

Referring to FIG. 2, the receiver 210 of the present invention includes a pulse generator 240, comparators 211a and 212a and data determiners 221b and 222b.

The pulse generator 240 generates fifth to eighth clock signals CLK5 to CLK8 (or second clock signals) using the first clock signals CLK1 to CLK4. In practice, the pulse generator 240 performs an AND operation on the adjacent pulses CLK1, CLK2; CLK2, CLK3; CLK3, CLK4; CLK4, CLK1 with overlapping high periods to perform the fifth clock signal to the eighth clock signal ( CLK5 to CLK8). Here, each of the fifth and eighth clock signals CLK5 to CLK8 is set to the same pulse width as the supply time (or period of bits) of one bit.

The first input terminal 300 of the comparators 211a and 212a receives the current bit, and the second input terminal 302 receives the previous bit. To this end, the first input terminal 300 directly receives data via the channel 100, and the second input terminal 302 inputs data via the first switch SW1. Receive. The first switch SW1 is turned off when the clock signal of any one of the fifth clock signal CLK5 to the eighth clock signal CLK8 is supplied.

Meanwhile, first capacitors C1a and Clb for storing current bits are formed between the first input terminal 300 and the electromotive force GND of the comparators 211a and 212a, and the second input terminal 302 Second capacitors C2a and C2b are formed between the electromotive power sources GND to store the previous bit.

The data determining units 221b and 222b include the first storage units 230a and 230b, the selection units 232a and 232b, the transition detectors 234a and 234b, the second storage units 236a and 236b, and the level sheeter. 238a and 238b and third storage parts 240a and 240b.

The first storage units 230a and 230b store the outputs of the first comparators 211a and 212a.

The transition detectors 234a and 234b output high or low in response to the outputs of the first comparators 211a and 212a.

The second storage units 236a and 236b store the outputs of the transition detectors 234a and 234b.

The level shifters 238a and 238b change the voltage levels of the signals stored in the second storage units 236a and 236b and supply them to the selection units 232a and 232b.

The selectors 232a and 232b may be any one of bits stored in the first storage units 230a and 232b or bits inputted from previous data determination units 224b and 221b in response to signals from the level shifters 238a and 238b. It is supplied to the third storage unit (240a, 240b).

The third storage units 240a and 240b store the bits output from the selection units 232a and 232b, and output the stored bits to the output terminals out1 and out2.

3 is a waveform diagram illustrating an operation process of the receiver illustrated in FIG. 2. In FIG. 3, an operation process will be described using a second comparator 212a and a second data determiner 222b for convenience of description.

Referring to FIG. 3, the first switches SW1 respectively connected to the second input terminals 302 of the comparators 211a and 212a are supplied with a clock signal CLK5 or CLK6 (that is, a high level voltage). When it is turned off, otherwise it is turned on.

In fact, when the sixth clock signal CLK6 is supplied, the first switch SW1 connected to the second comparator 212a is turned off. When the first switch SW1 is turned off, the data Dn + 1 of the previous bit is stored in the second capacitor C2b. Meanwhile, when the sixth clock signal CLK6 is supplied, the data Dn + 2 of the current bit is stored in the first capacitor C1b connected to the second comparator 212a.

Thereafter, the comparator 212a compares the data of the previous bit Dn + 1 and the data of the current bit Dn + 2, and corresponds to the comparison result of the high, low, and middld. Output the signal. In fact, the comparator 212a outputs a high signal when it is determined that the data of the current bit Dn + 2 is greater than the data of the previous bit Dn + 1 (that is, the current bit is "1"), When it is determined that the data Dn + 2 is smaller than the data Dn + 1 of the previous bit (that is, when the current bit is "0"), a low signal is output. The comparator 212a outputs a middle signal when it is determined that the data Dn + 2 of the current bit and the data Dn + 1 of the previous bit are the same.

The first storage unit 230b stores the output signal from the first comparator 212a when the seventh clock signal CLK7 is supplied. In FIG. 2, the first storage unit 230b is shown to be driven when the seventh clock signal CLK7 is supplied. However, the present invention is not limited thereto. In practice, the first storage unit 230b may use other pulses CLK7 except for the pulse CLK6 supplied to the first switch SW1 connected to the second second comparator 212a among the pulses generated by the pulse generator 240. , CLK8, CLK5) can be driven when supplied. However, in the present invention, the first storage unit 230b operates when the seventh clock pulse CLK7 supplied immediately after the sixth clock pulse CLK6 is operated to improve the stability of the operation.

The transition detector 234b receives one of a high, low, and middle signals from the first comparator 212a. Here, the transition detector 234b outputs a high signal when the high and low signals are supplied, and outputs a low signal when the middle signal is supplied.

The high or low signal output from the transition detection unit 234b is stored in the second storage unit 236b when the seventh clock signal CLK7 (that is, the same clock signal as the first storage unit 230b) is supplied. .

The level shifter 238b voltage-amplifies a high or low signal stored in the second storage unit 236b and supplies it to the selector 232b. In other words, the level shifter 238b controls the voltage level of the high and / or low signal so that a switch (not shown) included in the selector 232b can be turned on and / or off stably. do.

The selector 232b selectively outputs a bit stored in the first storage 230b or a bit supplied from the previous data determiner 221b in response to a high or low signal supplied from the level shifter 238b. In practice, the selector 232b supplies a signal (ie, the current bit) stored in the first storage unit 230b to the output terminal out2 when the high signal is supplied, and the previous data determiner when the low signal is supplied. The signal (ie, previous bit) supplied from 221b is supplied to the output terminal out2.

4 is a circuit diagram illustrating an embodiment of the transition detector shown in FIG. 2.

Referring to FIG. 4, the transition detector 234 according to an embodiment of the present invention includes an eighth transistor M8 and a ninth transistor M9 having a first electrode connected to a first power source VDD, and a first transistor. A fourth transistor M4 and a seventh transistor M7 having a second electrode connected to the node N1, and a fifth transistor M5 and a sixth transistor having a second electrode connected to the second node N2; M6, the second transistor M2 connected between the third node N3 and the fifth node N5, and the third transistor connected between the fourth node N4 and the fifth node N5. M3) and a first transistor M1 connected between the fifth node N5 and the ground power source GND.

The first input terminal receives high, low and middle signals from the first comparator 212a.

The second input terminal receives a signal inverted from the first input terminal. For example, a low signal is supplied to the second input terminal when the high signal is supplied to the first input terminal, and a high signal is supplied to the second input terminal when the low signal is supplied to the first input terminal. When the middle signal is supplied to the first input terminal, the middle signal is also supplied to the second input terminal.

The first electrode of the eighth transistor M8 is connected to the first power supply VDD set to a voltage higher than the base power supply GND, and the second electrode is connected to the second node N2. The gate electrode of the eighth transistor M8 is connected to the ground power source GND. The eighth transistor M8 maintains the turn-on state.

The first electrode of the ninth transistor M9 is connected to the first power source VDD, and the second electrode is connected to the first node N1. The gate electrode of the ninth transistor M9 is connected to the electromotive power source GND. The ninth transistor M9 maintains a turn-on state.

The second electrode of the fourth transistor M4 is connected to the first node N1, and the first electrode is connected to the third node N3. The gate electrode of the fourth transistor M4 is connected to the first input terminal. The fourth transistor M4 is turned on and off in response to the voltage supplied to the first input terminal to control the voltage of the first node N1.

The second electrode of the seventh transistor M7 is connected to the first node N1, and the first electrode is connected to the fourth node N4. The gate electrode of the seventh transistor M7 is connected to the second input terminal. The seventh transistor M7 controls the voltage of the first node N1 while being turned on and off in response to the voltage supplied to the second input terminal.

The second electrode of the fifth transistor M5 is connected to the second node N2, and the first electrode is connected to the third node N3. The gate electrode of the fifth transistor M5 is connected to the reference power supply Vref. The fifth transistor M5 is turned on when the middle signal is supplied to the first input terminal and the second input terminal to control the voltage of the second node N2. For this purpose, the reference power supply Vref is set to a voltage between the high signal and the middle signal as shown in FIG.

The second electrode of the sixth transistor M6 is connected to the second node N2, and the first electrode is connected to the fourth node N4. The gate electrode of the sixth transistor M6 is connected to the reference power supply Vref. The sixth transistor M6 is turned on when the middle signal is supplied to the first input terminal and the second input terminal to control the voltage of the second node N2.

The second electrode of the second transistor M2 is connected to the third node N3, and the first electrode is connected to the fifth node N5. The gate electrode of the second transistor M2 is connected to the first input terminal. The second transistor M2 controls the voltage of the third node N3 while being turned on and off in response to the voltage supplied to the first input terminal.

The second electrode of the third transistor M3 is connected to the fourth node N3 and the first electrode is connected to the fifth node N5. The gate electrode of the third transistor M3 is connected to the second input terminal. The third transistor M3 controls the voltage of the fourth node N4 while being turned on and off in response to the voltage supplied to the second input terminal.

The first transistor M1 is connected between the fifth node N5 and the base power source GND. The first transistor M1 controls a predetermined current to flow from the fifth node N5 to the base power supply GND in response to the bias voltage Vbias.

1st input terminal Second input terminal Output terminal High Low High Low High High Middle Middle Low

Table 1 shows signals supplied to output terminals corresponding to signals supplied to the first input terminal and the second input terminal.

4 and Table 1, the operation process will be described in detail. First, when the high signal is supplied to the first input terminal, the second transistor M2 and the fourth transistor M4 are turned on. At this time, the fifth transistor M5 and the sixth transistor M6 that receive the reference power Vref lower than the high signal maintain the turn-off state.

When the second transistor M2 and the fourth transistor M4 are turned on, current flows from the first node N1 to the base power supply GND. In this case, the second node N2 maintains the voltage of the first power source VDD, and accordingly, a high signal is output to the output terminal.

When the low signal is supplied to the first input terminal, that is, when the high signal is input to the second input terminal, the third transistor M3 and the seventh transistor M7 are turned on. At this time, the fifth transistor M5 and the sixth transistor M6 that receive the reference power Vref lower than the high signal maintain the turn-off state.

When the third transistor M3 and the seventh transistor M7 are turned on, current flows from the first node N1 to the base power supply GND. In this case, the second node N2 maintains the voltage of the first power source VDD, and accordingly, a high signal is output to the output terminal.

When the middle signal is supplied to the first input terminal and the second input terminal, the fourth transistor M4 and the seventh transistor M7 are turned off. Then, the fifth transistor M5 and the sixth transistor M6 that receive the reference power Vref higher than the middle signal are turned on. When the fifth transistor M5 and the sixth transistor M6 are turned on, current is supplied from the second node N2 to the base power supply GND via the second transistor M2 and the third transistor M3. do. At this time, a low signal is output to the output terminal.

6 is a view showing a simulation result of a data transmission system according to an embodiment of the present invention.

Referring to FIG. 6, when the transmitter supplies data of "01011101 ...", the receiver stably restores data of "01011101 ...". That is, in the present invention, there is an advantage that the data can be stably restored while comparing the previous bit with the current bit regardless of noise.

7 is a flowchart schematically illustrating a method of driving a data transmission system of the present invention.

Referring to FIG. 7, first, data is transmitted from the transmitter 100 to the receiver 210. (S1000) The receiver 210, which has received data in step S1000, stores a previous bit (i−1 bit) of data. Compares the stored previous bit with the current bit (i bit) (S1002, S1004).

If it is determined in step S1004 that the previous bit and the current bit are different, the receiver 210 presents the current bit. (S1006, S1008) If it is determined in step S1004 that the previous bit and the current bit are the same, the receiver 210 transfers the previous bit. Output the bit (S1010).

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various modifications are possible within the scope of the technical idea of the present invention.

100: transmitter 110: channel
200: receiver 202: synchronous loop circuit
210,220,230: Receiver 211a, 212a, 213a, 214a: Comparator
221b, 222b, 223b, 224b: data determination unit
230a, 230b, 236a, 236b, 240a, 240b: storage unit
232a, 232b: selection unit 234a, 234b: transition detection unit
238a, 238b: level shifter 240: pulse generator

Claims (23)

A transmitter for transmitting data and a reference clock;
A receiver comprising a plurality of receivers, the receiver receiving the data and the reference clock from the transmitter;
Each of the receivers
J (j is two or more natural numbers) comparators for comparing the current bit and the previous bit of the data supplied to the self and outputting any one of a high signal, a low signal and a middle signal in response to the comparison result. ;
And a data determination unit connected to an output terminal of each of the comparators and configured to output one of the current bit and the previous bit in response to an output signal of the comparator. The method of claim 1,
The comparator includes the high signal when the current bit is determined to be larger than the previous bit, the low signal when the current bit is determined to be smaller than the previous bit, and the middle when the current bit and the previous bit are determined to be the same. A data transmission system, characterized in that for outputting a signal. The method of claim 2,
The comparator sets the voltage of the high signal to 100% and sets the voltage of the low signal to 0%, when the previous bit and the current bit have a voltage difference within ± 20%. And determine that the previous bit is the same. The method of claim 1,
And the receiver comprises a synchronous loop circuit which generates j first clock signals having a predetermined phase difference sequentially using the reference clock. 5. The method of claim 4,
Each of the first clock signals is set to a frequency 1 / j compared to the transmission frequency of the data. 5. The method of claim 4,
And the first clock signals sequentially overlap a high period by one bit supply time of the data. 5. The method of claim 4,
And a pulse generator for generating the j second clock signals by performing a logical AND operation on the first clock signals adjacent to each other. 8. The method of claim 7,
A first capacitor connected to a first input terminal of each of the comparators;
A second capacitor connected to a second input terminal of each of the comparators;
And a first switch connected between each of the second input terminals and the transmitter and turned off when any one of the second clock signals is supplied. The method of claim 8,
And the first switch is turned off when the current bit is input to the first capacitor so that the previous bit can be stored in the second capacitor. The method of claim 8,
Each of the data determination unit
A first storage unit storing an output signal of the comparator;
A transition detector for outputting a high signal or a low signal in response to an output signal of the comparator;
A second storage unit for storing an output signal of the transition detection unit;
A selection unit for outputting a signal stored in the first storage unit or a signal of a previous data determination unit in response to an output signal of the second storage unit;
And a third storage unit storing the output signal of the selection unit. The method of claim 10,
And the transition detector outputs a high signal when the high signal and the low signal are input from the comparator, and outputs a low signal when the middle signal is input. The method of claim 10,
And the selector outputs a signal stored in the first storage unit when a high signal is input from the second storage unit, and outputs a signal of the previous data determination unit when a low signal is input. The method of claim 10,
And a level shifter positioned between the second storage unit and the selection unit to change a voltage level of a signal stored in the second storage unit. The method of claim 10,
And the previous data determiner is a data determiner that outputs the previous bit. The method of claim 10,
And the first storage unit and the second storage unit receive the same second clock signal. The method of claim 10,
And the first storage unit receives a second clock signal different from the first switch connected to the comparator. The method of claim 10,
And the third storage unit receives a second clock signal identical to the first switch connected to the comparator. The method of claim 10,
The transition detector
A ninth transistor connected between the first power supply and the first node to maintain a turn-on state;
An eighth transistor connected between the first power supply and the second node and maintaining a turn-on state;
A fourth transistor connected between the first node and a third node, the fourth transistor being turned on and off by a voltage supplied to a first input terminal;
A seventh transistor connected between the first node and the fourth node and turned on and off by a voltage supplied to a second input terminal;
A second transistor connected between the third node and a fifth node and having a gate electrode connected to the first input terminal;
A third transistor connected between the fourth node and a fifth node and having a gate electrode connected to the second input terminal;
A first transistor connected between the fifth node and a base power source and configured to flow a predetermined current from the fifth node to the base power source in response to a bias voltage;
A fifth transistor connected between the second node and the third node and having a gate electrode connected to a reference power source;
And a sixth transistor connected between the second node and the fourth node and having a gate electrode connected to the reference power source. 19. The method of claim 18,
And the first input terminal receives an output signal of the first comparator. 20. The method of claim 19,
The second input terminal receives a low signal when the high signal is supplied to the first input terminal, receives a high signal when the low signal is supplied, and receives the same middle signal when the middle signal is supplied. Data transmission system. 19. The method of claim 18,
When the middle signal is input to the first input terminal and the second input terminal, the reference power source is configured so that the fourth transistor and the seventh transistor are turned off, and the middle and fifth transistors are turned on. And a voltage between the high signal. The method of claim 1,
And the previous bit is an i (i is a natural number) th bit and the current bit is an i + 1 th bit. Transmitting data from a transmitter to a receiver;
I (i is a natural number) -1th bit of the data is stored;
Comparing the i th bit of the data and the i-1 th bit;
Outputting the i th bit when it is determined that the i th bit and the i-1 th bit are different;
And outputting the i-1 th bit when it is determined that the i th bit and the i-1 th bit are the same.

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