KR101222092B1 - Data sampling device and data sampling method using the same - Google Patents

Abstract

The data sampling device includes an inverter having an input and an output connected to each other and an inverter module configured to perform active feedback on input signals transmitted to the first and second nodes of the cross-connected inverter and the first of the cross-connected inverters. And a sample and hold module including a first sample and hold circuit and a second sample and hold circuit respectively connected to the node and the second node, wherein the sample and hold module samples the first input signal and the second input signal, Under the control of the clock signal, the sampled input signal and the held signal of the second input signal are transferred to the first node and the second node of the cross-connected inverter, respectively, and the inverter module is connected to the first node and the second node. Active feedback is performed on the transferred held signal, and the value of the held signal on which the active feedback is performed is output as an output signal.

Description

DATA SAMPLING DEVICE AND DATA SAMPLING METHOD USING THE SAME}

The present invention relates to a data sampling apparatus and a data sampling method using the same.

In data transmission / reception applications such as a System on Chip (SoC) or Application Specific Integrated Circuit (ASIC) that require high-speed data transmission, a transmitter transmits high-speed data through a channel to a receiver, and a receiver uses a clock. Read the signal sent from the transmitter. In this case, since the channel has a low pass filter, the output signal of the transmitter that has passed through the channel is greatly deteriorated, resulting in a small amplitude of the signal or a lot of interference between the signals. .

On the other hand, the signal transmitted from the transmitter generally has a differential data structure, and the data sampling circuit of the receiver reads the value of an input signal such as high speed data or small amplitude differential data and outputs it as an output signal. However, conventional data sampling circuits, such as sense-amplifiers and high-speed comparators, are often very complex in their structure, difficult to design, occupy a large area due to the complex structure, and many parasitic capacitors. Since parasitic capacitances occur, there is a problem in that performance decreases when fabricated with an actual chip.

In addition, since the input signal of the differential data structure applied to the input terminal of the data sampling circuit is continuously changing, it is difficult to read the exact value of the applied input signal, and the input that changes while the data sampling circuit determines the value of the input signal. The (voltage) value could affect the data sampling circuit and produce an incorrect output value.

An embodiment of the present invention provides a data sampling apparatus and a data sampling method using the same, which simplifies the structure of a circuit, eliminates generation of a plurality of parasitic components, and effectively discriminates and processes an input signal such as high-speed data or small amplitude differential data. The purpose is to provide.

In addition, one embodiment of the present invention by connecting the sample and hold circuit to the input terminal of the cross-connected inverter, thereby increasing the difference in the value of the held signal received through the sample and hold circuit by the active feedback of the cross-connected inverter It is an object of the present invention to provide a data sampling apparatus and a data sampling method using the same which can more accurately determine each input signal.

As a technical means for achieving the above-described technical problem, the data sampling device according to an embodiment of the present invention includes an inverter connected to the input and the output is connected, the transfer to the first node and the second node of the cross-connected inverter An inverter module for performing active feedback on the input signal and a sample and hold module including a first sample and hold circuit and a second sample and hold circuit respectively connected to the first node and the second node of the cross-connected inverter. However, the sample and hold module samples the first input signal and the second input signal, and according to the control of the clock signal, the first node of the inverter that cross-connects the sampled first input signal and the held signal of the second input signal. And a second node, and the inverter module performs active feedback on the held signals transmitted to the first node and the second node, and performs the active feedback. And it outputs the value of the signal into an output signal.

In addition, the data sampling method according to an embodiment of the present invention (a) the first sample and connected to each of the first node and the second node of the inverter cross-connected the input and output included in the inverter module that performs active feedback A hold circuit and a second sample and hold circuit sampling and storing the first input signal and the second input signal, and (b) the first sample and hold circuit and the second sample and hold circuit comprise the first input signal and the second input signal. Transmitting the held signal value of the input signal to the first node and the second node of the cross-connected inverter, respectively, (c) the first and second input signals transmitted from the inverter module to the first node and the second node, respectively; Performing active feedback on the held signal of the signal, and (d) outputting the value of the held signal on which the active feedback has been performed as an output signal.

According to any one of the problem solving means of the present invention described above, it is possible to simplify the structure of the circuit to eliminate the generation of a number of parasitic components, and to effectively identify and process input signals such as high-speed data or small amplitude differential data.

Further, according to any one of the above-described problem solving means of the present invention, by connecting the sample and hold circuit to the input terminal of the cross-connected inverter, the cross-connected inverter to the difference in the value of the held signal received through the sample and hold circuit It is possible to determine each input signal more accurately by increasing the active feedback.

1 shows an inverter circuit of a conventional cross connected structure.
FIG. 2 shows the voltage characteristics of each of the cross connected inverters of FIG.
3 shows the voltage characteristics of the cross-connected inverter of FIG.
4 is a configuration diagram of a data sampling apparatus according to an embodiment of the present invention.
5 is a diagram illustrating a switch configuration of a data sampling device for sampling and storing an input signal according to an exemplary embodiment.
6 is a diagram illustrating a switch configuration of a data sampling apparatus that performs active feedback on a signal input to each node according to an embodiment of the present invention.
7 illustrates states of switches according to a clock signal and a high / low state of a clock signal according to an exemplary embodiment.
8 is a detailed configuration diagram of the data sampling device of FIG. 4.
FIG. 9 illustrates a change of each node of a cross-connected inverter when a clock signal is changed from a 'low' to a 'high' state according to an embodiment of the present invention.
10 is a table showing experimental result values in various simulation environments of the data sampling apparatus according to an embodiment of the present invention.
11 is a flowchart of a data sampling method according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to be "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

1 shows an inverter circuit of a conventional cross connected structure.

As shown in FIG. 1, since the conventional cross-connected inverters 12 and 14 serve as positive feedback, the input / output states of the respective inverters 12 and 14 are stabilized without being influenced by the outside. Stays in the state.

That is, when setting operating points unstable from each other by external adjustment to the initial state, the input / output states of the inverters 12 and 14 cross-connected by the active feedback characteristics have a characteristic of quickly reaching a stabilized state. As such, when the inputs and outputs of the inverters are configured to cross each other, the voltage characteristics of each of the inverters 12 and 14 which are cross-connected are shown in FIG. 2.

FIG. 2 shows the voltage characteristics of each of the cross connected inverters of FIG.

As shown in FIG. 2A, the output voltage (ie, the voltage at node 1) is changed according to the change in the input voltage (ie, the voltage at node 2) of the inverter 12.

In addition, as shown in FIG. 2B, the output voltage (ie, the voltage at node 2) changes according to the change in the input voltage (ie, the voltage at node 1) of the inverter 14. Accordingly, the cross connected inverters 12 and 14 have the voltage characteristics as shown in FIG. 3 as a result.

3 shows the voltage characteristics of the cross-connected inverter of FIG.

As shown in FIG. 3, since the cross-connected inverters 12 and 14 serve as active feedbacks to each other, the signal (voltage) values of the node 1 and the node 2 are represented by 'a' or 'b' shown in the voltage characteristic curve. Will be in one of the positions of '. Here, when node 1 or node 2 is placed in a position other than 'ga' and 'b' due to an initial state or an external factor, node 1 is in the 'ga' position due to the active feedback of the connected inverters 12 and 14. Node 2 is located in the 'I' position.

In the initial state, when the signal values of the node 1 and the node 2 are located at 'multi' and have a very small difference value, the node reaches a stabilized value through the data sampling apparatus 100 of the present invention, which will be described later. By increasing the difference between 1 and node 2, the value of the signal transmitted to node 1 and node 2 can be read more accurately.

4 is a configuration diagram of a data sampling apparatus according to an embodiment of the present invention.

As shown in FIG. 4, the data sampling device 100 of the present invention includes an inverter module 110 and sample and hold modules 130 and 140 connected to an input terminal of the inverter module 110.

The inverter module 110 connects or disconnects node 1 and node 2 of the cross-connected inverters 112 and 114 under the control of the clock signals and the inverters 112 and 114 cross-connected with the inputs and outputs. 109. In addition, the inverter module 110 may further include a clock generator 3 (see FIG. 8) for generating a clock signal.

The inverter module 110 performs active feedback on the input signal 1 and the input signal 2 transmitted to the node 1 and the node 2 of the inverters 112 and 114 that are cross-connected. Through this, the inverter module 110 increases the difference between the held signal values of the input signal 1 and the input signal 2 transmitted to the node 1 and the node 2 to clearly read each held signal value as an output signal. You can print

The sample and hold modules 130 and 140 may include a first sample and hold circuit 130 and a second sample and hold circuit connected to node 1 and node 2 of the cross-connected inverters 112 and 114, respectively. 140. The sample and hold modules 130 and 140 sample the input signal 1 and the input signal 2 and cross-connect the held signals of the sampled input signal 1 and the input signal 2 under the control of the clock signal. To node 1 and node 2, respectively.

Here, the first sample-and-hold circuit 130 includes a capacitor 105 connected in parallel to store the input signal 1, a first switch 101 and a capacitor 105 and an inverter module transferring the input signal 1 to the capacitor 105. A second switch 103 connecting the nodes of 110, and the second sample and hold circuit 140 comprises a capacitor 106 connected in parallel to store the input signal 2, and an input signal 2 to the capacitor 106; And a first switch 102 for transmitting and a second switch 104 for connecting the capacitor 106 and the node of the inverter module 110. Hereinafter, the present invention will be described in more detail with reference to FIGS. 5 and 6.

5 is a diagram illustrating a switch configuration of a data sampling device for sampling and storing an input signal according to an exemplary embodiment.

As shown in FIG. 5, when the first switches 101 and 102 are closed and the second switches 103 and 104 are opened according to the control of the clock signal, the input signal 1 input to the input terminals 1 and 2 from the outside. And the input signal 2 are sampled and stored in the first capacitor 105 and the second capacitor 106, respectively. Here, the value of the signal (voltage) stored in each of the capacitors 105 and 106 follows the change of the input signal 1 and the input signal 2. At this time, the values of the input signal 1 and the input signal 2 that are changed because the second switches 103 and 104 are open do not affect the node 1 and the node 2.

In addition, according to the control of the clock signal, the third switch 109 connects the node 1 and the node 2 of the data sampling device 100 so that the signal values of the node 1 and the node 2 are equalized. . That is, by connecting the node 1 and the node 2 through the third switch 109 in the initial state of the data sampling device 100, the inverter 112 cross-connected to the 'multi' state of the state curve shown in FIG. , The signal values of Node 1 and Node 2 of 114) are initialized.

6 is a diagram illustrating a switch configuration of a data sampling apparatus that performs active feedback on a signal input to each node according to an embodiment of the present invention.

6, when the first switches 101 and 102 are opened and the second switches 103 and 104 are closed according to the control of the clock signal at a specific point in time, the capacitors 105 and 106 may be removed. The sampled input signal 1 and the held signal value of the input signal 2 at the moment when the two switches 103 and 104 are closed are stored. The held signal values of the input signal 1 and the input signal 2 stored in the capacitors 105 and 106 are transferred to the node 1 and the node 2, respectively.

At this time, when the first switch 101, 102 is opened and the second switch 103, 104 is closed at a specific time point under the control of the clock signal, the third switch 109 is opened to directly connect between the node 1 and the node 2. The connection is released. In addition, the difference between the signals transmitted to the node 1 and the node 2 in the initial state is gradually increased by the active feedback of the cross-connected inverters 112 and 114 to become a state that can be more clearly distinguished.

That is, when the held signal values of the input signal 1 and the input signal 2 having small difference values are transferred to the node 1 and the node 2 by the sample and hold modules 130 and 140, respectively, the inverters 112 and 114 connected to each other are cross-connected. By the active feedback operation of the value of the signal transmitted to the node 1 and the node 2 is in the 'ga' or 'b' state of FIG. 3 described above, the difference value of the signal is increased. Therefore, it is possible to determine the exact value of each signal transmitted to the node 1 and node 2. The inverter module 110 reads each signal and outputs it as an output signal.

As described above, the data sampling apparatus 100 of the present invention connects the sample and hold modules 130 and 140 to the respective input terminals of the inverter module 110 so that the cross-connected inverters 112 and 114 are connected to the sample and hold module ( It is possible to more accurately determine the respective input signals by increasing the difference between the held signal values received through 130 and 140 by active feedback.

In contrast, in the conventional data sampling circuit in which the sample and hold modules 130 and 140 are not configured, it is difficult to read the exact value of the input signal because the input signal applied to the input terminal continuously changes. In addition, the input signal value that changed while the data sampling circuit discriminated the value affected the data sampling circuit to generate an incorrect output value. In particular, the higher the data input speed, the worse the performance of the data sampling circuit.

However, the data sampling apparatus 100 of the present invention can determine the correct value by increasing the difference in a state in which the input signal value that is changed as described above is held at a specific time point, and only the small amplitude differential data is used as the input signal. In addition, it is possible to more accurately reduce the performance degradation even for high-speed data can solve the conventional problems.

On the other hand, the control of the switches 101 to 104 and 109 used in the data sampling apparatus 100 of the present invention is performed by a clock signal. Hereinafter, the state of each switch according to the high / low state of the clock signal and the clock signal will be described in detail with reference to FIG. 7.

7 illustrates states of switches according to a clock signal and a high / low state of a clock signal according to an exemplary embodiment.

As illustrated in FIG. 7, the states of the switches 101 to 104 and 109 according to the clock signal and the clock state are shown. When the clock signal is in the 'low' state, the first switches 101 and 102 are closed, the second switches 103 and 104 are opened, and the third switch 109 is in the closed state. At this time, the input signal 1 and the input signal 2 are stored in the capacitors 105 and 106, respectively, and the signal value held in each capacitor 105 and 106 is a node when the clock signal goes from the 'low' to the 'high' state. Passed to 1 and 2 respectively.

At this time, the first switches 101 and 102 are opened, the second switches 103 and 104 are closed, and the third switch 109 is in an open state. In addition, the difference between the signals transmitted to the node 1 and the node 2 by the cross-connected inverters 112 and 114 increases. Through this, it is possible to determine an accurate value for the input signal, and to operate while reducing the performance degradation accurately even for a high speed input signal.

Meanwhile, the data sampling apparatus 100 of FIG. 4 may be configured of a PMOS transistor and an NMOS transistor as shown in FIG. 8.

8 is a detailed configuration diagram of the data sampling device of FIG. 4.

As shown in FIG. 8, the PMOS transistors 201 and 202 correspond to the first switches 101 and 102, respectively, and the PMOS transistor 209 corresponds to the third switch 109. The first inverter 112 described above includes a PMOS transistor 207 and an NMOS transistor 205, and the second switch 103 corresponds to the NMOS transistor 203.

In addition, the above-described second inverter 114 includes a PMOS transistor 208 and an NMOS transistor 206, and the second switch 104 corresponds to the NMOS transistor 204. Here, the capacitors 105 and 106 described above can be omitted by the parasitic capacitor component.

In addition, the clock signal generated by the clock generator 3 may control the transistors 201 to 204 and 209, and the transistors 201 and 202 may satisfy the relationship between the clock signal and the switch of FIG. 7 described above. 209 may be in the form of a PMOS, and the transistors 203 and 204 may be configured in the form of an NMOS.

In addition, the data sampling apparatus 100 described above may include a slave latch 210 and a fourth inverter 215 and 216 formed of the third inverters 211 and 212 and the NORs 213 and 214. In this case, the held signals transmitted to the node 1 and the node 2 are transferred to the slave latch 210 through the third inverters 211 and 212, and the fourth inverters 215 and 216 respectively correct the polarity of the corresponding signals. Output signals 1 and 2 can be output through the output terminals 4 and 5, respectively. The change of node 1 and node 2 according to the state change of the clock signal will be described in detail later with reference to FIG. 8.

FIG. 9 illustrates a change of each node of a cross-connected inverter when a clock signal is changed from a 'low' to a 'high' state according to an embodiment of the present invention.

As shown in FIG. 9, when the clock signal is 'low', the transistor 209 is turned on to connect the node 1 and the node 2. This results in voltage equalization with the same signal values at node 1 and node 2. At this time, an input signal is input through the transistors 201 and 202.

When the clock signal is in the 'high' state, the transistor 209 is turned off to disconnect the node 1 and the node 2 from each other. At this time, input signals are transmitted to the nodes 1 and 2 through the transistors 203 and 204. In addition, the value of the input signal transmitted to each of the node 1 and the node 2 is gradually increased by the active feedback, so that the value of each input signal can be clearly identified.

10 is a table showing experimental result values in various simulation environments of the data sampling apparatus according to an embodiment of the present invention.

As shown in FIG. 10, in the experimental result table, 'VCM' represents the center voltages of the input signal 1 and the input signal 2, and 'Vswing' represents the width of the signal around the 'VCM' of the input signal 1 and the input signal 2. Indicates. In the experiment result table, the 'P' notation clearly reads the values of the held signals of the input signal 1 and the input signal 2 transmitted by the data sampling device 100 to the node 1 and the node 2, and the output signal 1 and the output signal. It shows the case of 2 output.

11 is a flowchart of a data sampling method according to an embodiment of the present invention.

As illustrated in FIG. 11, a first sample-and-hold circuit connected to node 1 and node 2 of inverters 112 and 114 cross-connected with inputs and outputs included in inverter module 110 that performs active feedback ( The sample and hold modules 130 and 140 including the 130 and the second sample and hold circuit 140 sample and store the input signal 1 and the input signal 2, respectively (S1101).

Here, the first sample and hold circuit 130 and the second sample and hold circuit 140 may include capacitors 105 and 106 storing an input signal and a first switch transferring the input signal to the capacitors 105 and 106. 101 and 102, and second switches 103 and 104 connecting the capacitors 105 and 106 and the nodes of the inverter module 110 may be included.

In addition, the sample and hold modules 130 and 140 close the first switches 101 and 102 and open the second switches 103 and 104 to control input signals to the respective capacitors 105 and 106 under the control of the clock signal. Can be stored. At this time, the third switch 109 is closed under the control of the clock signal to connect the node 1 and the node 2.

Here, the first switch 101, 102 and the second switch 103, 104 may be composed of a PMOS transistor and an NMOS transistor, respectively. In addition, the cross-connected inverters 112 and 114 may be composed of PMOS transistors and NMOS transistors, and the third switch 109 may be composed of PMOS transistors. For a detailed description thereof, see FIG. 8.

Next, the sample and hold modules 130 and 140 respectively transmit the held signal values of the stored input signal 1 and the input signal 2 to the node 1 and the node 2 of the inverters 112 and 114 cross-connected under the control of the clock signal. Transfer (S1111). At this time, the third switch 109 is opened under the control of the clock signal to disconnect the node 1 and the node 2.

Next, the inverter module 110 performs active feedback on the held signals of the input signal 1 and the input signal 2 transmitted to the node 1 and the node 2 (S1121).

The difference between the held signals on which active feedback is performed is read and output as an output signal (S1131).

On the other hand, the above description of the present invention is for the purpose of illustration, and those skilled in the art to which the present invention pertains that it can be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. Could be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

101-104, 109: switch
105, 106 capacitors
110: inverter module
112, 114: inverter
130, 140: sample and hold circuit

Claims (12)

In the data sampling device,
An inverter module including an inverter having an input and an output connected to each other and performing an active feedback on an input signal transmitted to a first node and a second node of the cross connected inverter;
A sample and hold module including a first sample and hold circuit and a second sample and hold circuit respectively connected to a first node and a second node of the cross-connected inverter,
The sample and hold module samples the first input signal and the second input signal, and controls the first and second input signals of the sampled first and second input signals under the control of a clock signal. To each node and to the second node,
The inverter module performs the active feedback on the held signal transmitted to the first node and the second node, and outputs the value of the held signal on which the active feedback is performed as an output signal.
Data sampling device.
The method of claim 1,
Each of the first sample and hold circuit and the second sample and hold circuit is
A capacitor for storing an input signal,
A first switch transferring the input signal to the capacitor;
A second switch connecting the capacitor and a node of the inverter module
Data sampling device comprising a.
The method of claim 2,
And wherein the first switch is a PMOS transistor and the second switch is an NMOS transistor.
The method of claim 2,
The sample and hold module
Close the first switch under the control of the clock signal, open the second switch to store the input signal in the capacitor, open the first switch under the control of the clock signal, and close the second switch to close the capacitor. And transmitting the value of the held signal stored in each node of the inverter module.
The method of claim 2,
The inverter module
And a third switch for connecting or disconnecting the first node and the second node according to the control of the clock signal.
The method of claim 5, wherein
The inverter module
When the input signal is stored in the capacitor according to the control of the clock signal, the third switch is closed to connect the first node and the second node so that the voltages of the first node and the second node are equalized. And when the held signal value of the input signal stored in the capacitor is transferred to the first node and the second node of the cross-connected inverter according to the control of the clock signal, opening the third switch to open the first switch. Disconnecting the node from the second node.
The method of claim 5, wherein
And said cross-connected inverter comprises a PMOS transistor and an NMOS transistor, and said third switch comprises a PMOS transistor.
8. The method according to any one of claims 1 to 7,
And a clock signal generator for generating the clock signal.
In the data sampling method using a data sampling device,
(a) a first sample and hold circuit and a second sample and hold circuit connected to a first node and a second node of an inverter in which an input and an output included in an inverter module performing active feedback are cross-connected, respectively; Sampling and storing the second input signal;
(b) the first sample and hold circuit and the second sample and hold circuit deliver the held signal values of the first input signal and the second input signal to the first node and the second node of the cross-connected inverter, respectively. Steps,
(c) the inverter module performing the active feedback on the held signals of the first input signal and the second input signal transmitted to the first node and the second node;
(d) outputting a value of the held signal on which the active feedback is performed as an output signal;
Data sampling method comprising a.
The method of claim 9,
Each of the first sample and hold circuit and the second sample and hold circuit is
A capacitor for storing an input signal,
A first switch transferring the input signal to the capacitor;
A second switch connecting the capacitor and a node of the inverter module
Including,
The step (a)
And closing the first switch and opening the second switch under the control of a clock signal to store the input signal in the capacitor.
The method of claim 9,
The inverter module
A third switch connecting or disconnecting the first node and a second node;
The step (a)
Closing the third switch by the inverter module to control the clock signal to connect the first node and the second node to equalize voltages of the first node and the second node; Data sampling method.
The method of claim 11,
The step (b)
And disconnecting the first node from the second node by opening the third switch under the control of the clock signal.

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