KR101218292B1 - Dc-dc converting circuit - Google Patents

Abstract

The present invention relates to a DC-DC converter circuit that can significantly reduce the size of the pumping unit by reducing the number of switches, and in advance, the input voltage input to the input terminal according to the first to twelfth switch control signals from the outside. And a pumping part configured to generate a gate high voltage and a gate low voltage by pumping the set multiple, output the gate high voltage through the high potential output terminal, and output the gate low voltage through the low potential output terminal.

Description

DC-DC CONVERTING CIRCUIT}

The present invention relates to a DC-DC converter circuit, and more particularly to a DC-DC converter circuit that can significantly reduce the size of the pumping unit by reducing the number of switches.

The pumping unit provided in the conventional DC-DC conversion circuit requires a large number of switches to pump an input voltage. In addition, since these switches are all composed of large area high voltage MOS transistors, the size of the pumping part is inevitably large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. The present invention provides a pumping unit using only 12 switches and 12 control signals for controlling the 12 switches, thereby reducing costs and using high voltage transistors. An object of the present invention is to provide a DC-DC converter circuit which can minimize the size of the pumping unit and significantly reduce the size of the pumping unit.

DC-DC conversion circuit according to the present invention for achieving the above object, the gate high voltage and the gate low voltage by pumping the input voltage input to the input terminal to a predetermined multiple in accordance with the first to twelfth switch control signal from the outside And a pumping unit configured to output the gate high voltage through the high potential output terminal, and output the gate low voltage through the low potential output terminal.

The pumping unit alternately outputs the gate high voltage and the gate low voltage.

The pumping unit outputs the gate high voltage during the high voltage output period, and then maintains the output gate high voltage during the high voltage sustain period; Then, the gate low voltage is output during the low voltage output period, and the output gate low voltage is then maintained during the low voltage sustain period.

The pumping unit may include: a first switch controlled by the first switch control signal to electrically connect or disconnect the input terminal and the first node from each other; A second switch controlled by the second switch control signal to electrically connect or disconnect the first node and the second node from each other; A third switch controlled by the third switch control signal to electrically connect or disconnect the second node and the high potential output terminal from each other; A fourth switch controlled by the fourth switch control signal to electrically connect or disconnect the third node and the base power source from each other; A fifth switch controlled by the fifth switch control signal to electrically connect or disconnect the third node and the input terminal from each other; A sixth switch controlled by the sixth switch control signal to electrically connect or disconnect the fourth node and the input terminal from each other; A seventh switch controlled by the seventh switch control signal to electrically connect or disconnect the fourth node and the fifth node from each other; An eighth switch controlled by the eighth switch control signal to electrically connect or disconnect the second node and the fifth node from each other; A ninth switch controlled by the ninth switch control signal to electrically connect or disconnect the fourth node and the low potential output terminal from each other; A tenth switch controlled by the tenth switch control signal to electrically connect or disconnect the fifth node and the low potential power source from each other; An eleventh switch controlled by the eleventh switch control signal to electrically connect or disconnect the fifth node from the base power source; A twelfth switch controlled by the twelfth switch control signal to electrically connect or disconnect the fifth node from the reference power source; A first capacitor connected between the first node and a third node; A second capacitor connected between the second node and a fourth node; A third capacitor connected between the high potential output terminal and a base power source; And a fourth capacitor connected between the low potential output terminal and the base power supply.

And a switch control unit for generating and outputting first to twelfth switch control signals for controlling the first to twelfth switches.

The switch control unit may include an output control signal having an enabled state for a continuous high voltage output period and a high voltage sustain period, and having a disable state for a subsequent low voltage output period and a low voltage sustain period; A high voltage output control signal having an enable state for the high voltage output period and having a disable state for a period other than the high voltage output period; A high voltage maintenance control signal having an enable state during the high voltage maintenance period and having a disable state for a period other than the high voltage maintenance period; A low voltage output control signal having an enable state for the low voltage output period and having a disable state for the rest of the period except the low voltage output period; A low voltage maintenance control signal having an enable state during the low voltage maintenance period and having a disable state for a period other than the low voltage maintenance period; And the first to twelfth switch control signal based on a logic control signal for controlling a logic state of the first to twelfth switch control signal during the high voltage output period, the high voltage sustain period, the low voltage output period, and the low voltage sustain period. Characterized in that generates.

The switch control unit may control a logic value of the first to twelfth switch control signals to pump the gate high voltage and the gate low voltage in a preset multiple according to the logic value of the logic control signal.

The logic control signal is characterized in that the digital data of three bits.

When the digital code of the logic control signal is 000, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are four times and three times larger than the input voltage, respectively. Control the value; When the digital code of the logic control signal is 001, the switch control unit controls the logic values of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are four times larger than the input voltage, respectively. To; When the digital code of the logic control signal is 010, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 5 times and 3 times larger than the input voltage, respectively. Control the value; When the digital code of the logic control signal is 011, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 5 times and 4 times larger than the input voltage, respectively. Control the value; When the digital code of the logic control signal is 100, the switch control unit controls the logic values of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are five times larger than the input voltage, respectively. To; When the digital code of the logic control signal is 101, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 6 times and 3 times larger than the input voltage, respectively. Control the value; When the digital code of the logic control signal is 110, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 6 times and 4 times larger than the input voltage, respectively. Control the value; And, when the digital code of the logic control signal is 111, the switch control unit the first to twelfth switch control signal so that the gate high voltage and the gate low voltage has a magnitude of 6 times and 5 times the input voltage, respectively It is characterized by controlling the logical value of.

When the digital code of the logic control signal is 000, during the high voltage output period, the first, third, fourth, seventh and eleventh switch control signals are kept active, and the remaining switch control signals are inactive. Remain state; During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage output period, the first, fourth, eighth, ninth and twelfth switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage holding period, the switch control unit is configured such that the second, fifth, seventh, and eleventh switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. And a logic value of the twelfth switch control signal.

When the digital code of the logic control signal is 001, the first, third, fourth, seventh and eleventh switch control signals remain active during the high voltage output period, and the remaining switch control signals are inactive. Remain state; During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage output period, the first, fourth, eighth, ninth and eleventh switch control signals remain active and the remaining switch control signals remain inactive; During the low voltage holding period, the switch control unit is configured such that the second, fifth, seventh, and eleventh switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. And a logic value of the twelfth switch control signal.

When the digital code of the logic control signal is 010, during the high voltage output period, the first, third, fourth, seventh and twelfth switch control signals remain active and the remaining switch control signals are inactive. Remain state; During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage output period, the first, fourth, eighth, ninth and twelfth switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage holding period, the switch control unit is configured such that the second, fifth, seventh, and eleventh switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. And a logic value of the twelfth switch control signal.

When the digital code of the logic control signal is 011, during the high voltage output period, the first, third, fourth, seventh and twelfth switch control signals remain active, and the remaining switch control signals are inactive. Remain state; During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage output period, the first, fourth, eighth, ninth and eleventh switch control signals remain active and the remaining switch control signals remain inactive; During the low voltage holding period, the switch control unit is configured such that the second, fifth, seventh, and eleventh switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. And a logic value of the twelfth switch control signal.

When the digital code of the logic control signal is 100, the first, third, fourth, seventh and twelfth switch control signals remain active during the high voltage output period, and the remaining switch control signals are inactive. Remain state; During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage output period, the first, fourth, eighth, ninth and tenth switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage holding period, the switch control unit is configured such that the second, fifth, seventh, and eleventh switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. And a logic value of the twelfth switch control signal.

When the digital code of the logic control signal is 101, during the high voltage output period, the first, third, fourth and sixth switch control signals remain active and the remaining switch control signals remain inactive. Become; During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage output period, the first, fourth, eighth, ninth and twelfth switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage holding period, the switch control unit is configured such that the second, fifth, seventh, and eleventh switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. And a logic value of the twelfth switch control signal.

When the digital code of the logic control signal is 110, during the high voltage output period, the first, third, fourth and sixth switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. Become; During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage output period, the first, fourth, eighth, ninth and eleventh switch control signals remain active and the remaining switch control signals remain inactive; During the low voltage holding period, the switch control unit is configured such that the second, fifth, seventh, and eleventh switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. And a logic value of the twelfth switch control signal.

When the digital code of the logic control signal is 111, during the high voltage output period, the first, third, fourth, and sixth switch control signals remain active, and the remaining switch control signals remain inactive. Become; During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage output period, the first, fourth, eighth, ninth and tenth switch control signals remain active, and the remaining switch control signals remain inactive; During the low voltage holding period, the switch control unit is configured such that the second, fifth, seventh, and eleventh switch control signals are kept in an active state, and the remaining switch control signals are kept in an inactive state. And a logic value of the twelfth switch control signal.

The first to third switches and the sixth to ninth switches each comprise a high voltage transistor; And the fourth to fifth switches and the tenth to twelfth switches each comprise a medium voltage transistor; The medium voltage transistor occupies a smaller area than the high voltage transistor.

The first to third, fifth, sixth and twelfth switches are P-type transistors, respectively; The fourth switch and the seventh to eleventh switches are N type transistors, respectively.

The switch control unit may include: a high voltage output control signal having an enable state for a high voltage output period and having a disable state for a period other than the high voltage output period; A high voltage maintenance control signal having an enable state during the high voltage maintenance period and having a disable state for the rest of the period except the high voltage maintenance period; A low voltage output control signal having an enable state for the low voltage output period and having a disable state for the rest of the period except the low voltage output period; A low voltage maintenance control signal having an enable state during the low voltage maintenance period and having a disable state for the rest of the period except the low voltage maintenance period; And controlling the first to twelfth switch control signals based on a logic control signal for controlling the logic states of the first to twelfth switch control signals during the high voltage output period, the high voltage sustain period, the low voltage output period, and the low voltage sustain period. Characterized in that generated.

The switch control unit may include an output control signal having an enabled state for a continuous high voltage output period and a high voltage sustain period, and having a disable state for a subsequent low voltage output period and a low voltage sustain period; A high / low output control signal having an enable state during the high voltage output period and the low voltage output period, and having a disable state for a period other than the high voltage output period and the low voltage output period; A high / low maintenance control signal having an enable state during the high voltage holding period and the low voltage holding period, and having a disable state for the remaining periods except for the high voltage holding period and the low voltage holding period; And the first to twelfth switch control signal based on a logic control signal for controlling a logic state of the first to twelfth switch control signal during the high voltage output period, the high voltage sustain period, the low voltage output period, and the low voltage sustain period. Characterized in that generates.

An input voltage supplied to the input terminal has a voltage level twice that of a reference voltage; The reference power supply provides a reference voltage having a voltage level of 2.8 to 3.3 [V]; The base power supply provides a base voltage of 0 [V]; The low potential power supply is characterized by providing a low voltage having a voltage level of -3.3 to -2.8 [V] to the reference voltage.

The DC-DC converter circuit according to the present invention having such a configuration has the following effects.

First, it is possible to reduce costs by reducing the number of switches by configuring a pumping unit using only 12 switches and 12 control signals for controlling the 12 switches.

Second, the size of the pumping unit can be significantly reduced by minimizing the use of the high voltage transistor.

Third, gate high voltages and gate low voltages of various sizes can be generated, and thus, they can be used in various devices (eg, display devices) requiring a DC-DC converter circuit.

1 is a diagram showing a DC-DC converter circuit according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating various signals supplied to the switch control unit of FIG. 1. FIG.
3 is a diagram illustrating each waveform of an output control signal, a high voltage output control signal, a high voltage maintenance control signal, a low voltage output control signal, and a low voltage maintenance control signal supplied to the switch control unit of FIG. 2;
Fig. 4 is a table showing the pumping multiples of the gate high voltage and the gate low voltage according to the digital code of the 3-bit logic control signal.
Fig. 5 is a diagram showing a first timing diagram of first to twelfth switch control signals output from the switch control unit when the digital code of the logic control signal supplied to the switch control unit is 000;
6A to 6D are diagrams for describing an operation of the first to twelfth switches according to the first to twelfth switch control signals of FIG. 5.
Fig. 7 is a diagram showing a second timing diagram of the first to twelfth switch control signals output from the switch control unit when the digital code of the logic control signal supplied to the switch control unit is 001.
8A to 8D are diagrams for describing operations of the first to twelfth switches according to the first to twelfth switch control signals of FIG. 7.
Fig. 9 is a view showing a third timing diagram of the first to twelfth switch control signals output from the switch control unit when the digital code of the logic control signal supplied to the switch control unit is 010;
10A to 10D are diagrams for describing operations of the first to twelfth switches according to the first to twelfth switch control signals of FIG. 9.
Fig. 11 is a view showing a fourth timing diagram of first to twelfth switch control signals outputted from the switch control unit when the digital code of the logic control signal supplied to the switch control unit is 011;
12A to 12D are diagrams for describing operations of the first to twelfth switches according to the first to twelfth switch control signals of FIG. 11.
FIG. 13 is a view showing a fifth timing diagram of first to twelfth switch control signals output from the switch control unit when the digital code of the logic control signal supplied to the switch control unit is 100; FIG.
14A to 14D are diagrams for describing operations of the first to twelfth switches according to the first to twelfth switch control signals of FIG. 13.
Fig. 15 is a diagram showing a sixth timing diagram of the first to twelfth switch control signals outputted from the switch control unit when the digital code of the logic control signal supplied to the switch control unit is 101;
16A to 16D are diagrams for describing operations of the first to twelfth switches according to the first to twelfth switch control signals of FIG. 15.
FIG. 17 is a view showing a seventh timing diagram of the first to twelfth switch control signals output from the switch control unit when the digital code of the logic control signal supplied to the switch control unit is 110; FIG.
18A to 18D are diagrams for describing operations of the first to twelfth switches according to the first to twelfth switch control signals of FIG. 17.
Fig. 19 is a view showing an eighth timing diagram of first to twelfth switch control signals outputted from the switch control unit when the digital code of the logic control signal supplied to the switch control unit is 111;
20A to 20D are diagrams for describing operations of the first to twelfth switches according to the first to twelfth switch control signals of FIG. 19.
FIG. 21 is yet another diagram of various signals supplied to the switch control unit of FIG. 1; FIG.
FIG. 22 is a view showing respective waveforms of the high voltage output control signal, the high voltage holding control signal, the low voltage output control signal, and the low voltage holding control signal supplied to the switch control unit of FIG.
FIG. 23 is yet another diagram of various signals supplied to the switch control unit of FIG. 1; FIG.
FIG. 24 is a view showing respective waveforms of an output control signal, a high / low output control signal, and a high / low maintenance control signal supplied to the switch control unit of FIG. 23; FIG.
FIG. 25 is a diagram illustrating an example in which the first through twelfth switches of FIG. 1 are configured as MOS transistors. FIG.
26 is a view for comparing the switches provided in the pumping unit and the switch provided in the conventional pumping unit according to the present invention.

1 is a view showing a DC-DC converter circuit according to an embodiment of the present invention.

As shown in FIG. 1, a DC-DC converter according to an exemplary embodiment of the present invention includes a pumping unit PB for pumping an input voltage DDVDH input to an input terminal IT, and the pumping unit ( It includes a switch control unit (SCB) for controlling the operation of the first to twelfth switches (SW1 to SW12) provided in the PB.

The pumping unit PB generates the gate high voltage VGH and the gate low voltage VGL by pumping the input voltage DDVDH in a preset multiple according to the first to twelfth switch control signals SCS1 to SCS12. The gate high voltage VGH is output through the high potential output terminal HT, and the gate low voltage VGL is output through the low potential output terminal LT.

At this time, the pumping part PB alternately outputs the gate high voltage VGH and the gate low voltage VGL.

The pumping unit PB operates as follows for each of the high voltage output period, the high voltage holding period, the low voltage output period, and the low voltage holding period which are sequentially generated.

That is, during the high voltage output period, the pumping part PB outputs the gate high voltage VGH. The output gate high voltage VGH is then maintained during the high voltage holding period.

Subsequently, during the low voltage output period, the pumping part PB outputs the gate low voltage VGL. The output gate low voltage VGL is then maintained during the low voltage sustain period.

The pumping part PB sequentially outputs the gate high voltage VGH and the gate low voltage VGL during one period including the high voltage output period, the high voltage sustain period, the low voltage output period, and the low voltage sustain period. At this time, the pumping unit PB repeats the above-described operation every cycle. That is, every cycle, the gate high voltage VGH is output and maintained, and then the gate low voltage VGL is output and maintained.

The pumping unit PB includes the first to twelfth switches SW1 to SW12 whose operation is controlled by the first to twelfth switch control signals SCS1 to SCS12, and the first to fourth capacitors C4. It includes.

Here, the first to twelfth switch control signals SCS1 to SCS12 have an active state or an inactive state, and the active state of the switch control signal means a voltage level of a state in which any switch supplied with the switch can be turned on. The inactive state of a signal means a voltage level of a state in which any switch supplied with the signal can be turned off. In the present invention, an example in which all of the above-described switches are used as transistors composed of N types will be described. Therefore, the active state of the switch control signal means the high level voltage state of the switch control signal, and the inactive state means the low level voltage state of the switch control signal.

The first switch SW1 is controlled by the first switch control signal SCS1 to electrically connect or disconnect the input terminal IT and the first node N1 from each other. For example, the first switch SW1 electrically connects the input terminal IT and the first node N1 to each other in response to the first switch control signal SCS1 in the active state. The input terminal IT may be applied with an input voltage DDVDH having a level twice that of the reference voltage VCI. The reference voltage VCI may have a voltage level of 2.8 to 3.3 [V].

The second switch SW2 is controlled by the second switch control signal SCS2 to electrically connect or disconnect the first node N1 and the second node N2 from each other. For example, the second switch SW2 electrically connects the first node N1 and the second node N2 to each other in response to the second switch control signal SCS2 in the active state.

The third switch SW3 is controlled by the third switch control signal SCS3 to electrically connect or disconnect the second node N2 and the high potential output terminal HT from each other. For example, the third switch SW3 electrically connects the second node N2 and the high potential output terminal HT to each other in response to the third switch control signal SCS3 in the active state.

The fourth switch SW4 is controlled by the fourth switch control signal SCS4 to electrically connect or disconnect the third node N3 from the base power source. For example, the fourth switch SW4 electrically connects the third node N3 and the base power source to each other in response to the fourth switch control signal SCS4 in the active state. Here, the base power source provides a base voltage VSS. This base voltage VSS may have a voltage level of 0 [V].

The fifth switch SW5 is controlled by the fifth switch control signal SCS5 to electrically connect or disconnect the third node N3 and the input terminal IT from each other. For example, the fifth switch SW5 electrically connects the third node N3 and the input terminal IT to each other in response to the fifth switch control signal SCS5 in the active state.

The sixth switch SW6 is controlled by the sixth switch control signal SCS6 to electrically connect or disconnect the fourth node N4 and the input terminal IT from each other. For example, the sixth switch SW6 electrically connects the fourth node N4 and the input terminal IT to each other in response to the sixth switch control signal SCS6 in the active state.

The seventh switch SW7 is controlled by the seventh switch control signal SCS7 to electrically connect or disconnect the fourth node N4 and the fifth node N5 from each other. For example, the seventh switch SW7 electrically connects the fourth node N4 and the fifth node N5 to each other in response to the seventh switch control signal SCS7 in the active state.

The eighth switch SW8 is controlled by the eighth switch control signal SCS8 to electrically connect or disconnect the second node N2 and the fifth node N5 from each other. For example, the eighth switch SW8 electrically connects the second node N2 and the fifth node N5 to each other in response to an eighth switch control signal SCS8 in an active state.

The ninth switch SW9 is controlled by the ninth switch control signal SCS9 to electrically connect or disconnect the fourth node N4 and the low potential output terminal LT from each other. For example, the ninth switch SW9 electrically connects the fourth node N4 and the low potential output terminal LT to each other in response to the ninth switch control signal SCS9 in an active state.

The tenth switch SW10 is controlled by the tenth switch control signal SCS10 to electrically connect or disconnect the fifth node N5 and the low potential power source from each other. For example, the tenth switch SW10 electrically connects the fifth node N5 and the low potential power to each other in response to the tenth switch control signal SCS10 in the active state. Here, the low potential power source provides a low voltage VCL. The low voltage VCL is a voltage having a polarity opposite to that of the reference voltage VCI. For example, the low voltage VCL may have a voltage level of -3.3 to -2.8 [V].

The eleventh switch SW11 is controlled by the eleventh switch control signal SCS11 to electrically connect or disconnect the fifth node N5 and the base power source from each other. For example, the eleventh switch SW11 electrically connects the fifth node N5 and the base power source to each other in response to the eleventh switch control signal SCS11 in an active state.

The twelfth switch SW12 is controlled by the twelfth switch control signal SCS12 to electrically connect or disconnect the fifth node N5 from the reference power source. For example, the twelfth switch SW12 electrically connects the fifth node N5 and the reference power source in response to the twelfth switch control signal SCS12 in an active state.

The first capacitor C1 is connected between the first node N1 and the third node N3.

The second capacitor C2 is connected between the second node N2 and the fourth node N4.

The third capacitor C3 is connected between the high potential output terminal HT and the base power supply.

The fourth capacitor C4 is connected between the low potential output terminal LT and the base power supply.

The switch control unit SCB generates the above-described first to twelfth switch control signals SCS1 to SCS12. Then, these first to twelfth switch control signals SCS1 to SCS12 are supplied to the first to twelfth switches SW1 to SW12, respectively.

FIG. 2 is a diagram illustrating various signals supplied to the switch control unit SCB of FIG. 1.

As shown in FIG. 2, the switch control unit SCB includes an output control signal OCS, a high voltage output control signal HOCS, a high voltage maintenance control signal HOMS, a low voltage output control signal LOCS, The first to twelfth switch control signals SCS1 to SCS12 described above are generated based on the low voltage holding control signal LOMS and the logic control signal LCS.

3 is an output control signal OCS, a high voltage output control signal HOCS, a high voltage maintenance control signal HOMS, a low voltage output control signal LOCS, and a low voltage maintenance control signal supplied to the switch control unit SCB of FIG. A diagram showing each waveform of LOMS).

The output control signal OCS has an enabled state during the continuous high voltage output period T_HO and the high voltage sustain period T_HM, as shown in FIG. On the other hand, it has a disabled state during successive low voltage output periods T_LO and low voltage sustain periods T_LM. Here, the enable state of the signal corresponds to a section in which the signal is kept high, and the disable state refers to a section in which the signal is kept low.

The high voltage output control signal HOCS has an enabled state during the high voltage output period T_HO, as shown in FIG. On the other hand, it has a disabled state for the remaining period except for the high voltage output period T_HO.

The high voltage holding control signal HOMS has an enabled state during the high voltage holding period T_HM, as shown in FIG. On the other hand, it has a disabled state for the rest of the period except for the high voltage holding period T_HM.

The low voltage output control signal LOCS has an enabled state during the low voltage output period T_LO, as shown in FIG. On the other hand, it has a disabled state for the remaining period except the low voltage output period T_LO.

The low voltage holding control signal LOMS has an enabled state during the low voltage holding period T_LM, as shown in FIG. On the other hand, it has a disabled state for the rest of the period except the low voltage holding period T_LM.

The output control signal OCS is kept enabled every half of the first half of one cycle 1T, and the output control signal OCS remains disabled every half of the second half of one cycle. . During the period in which the output control signal OCS is maintained in the enabled state, the high voltage output control signal HOCS and the high voltage holding control signal HOMS are sequentially enabled to output and maintain the gate high voltage VGH. The first through twelfth switch control signals SCS1 through SCS12 are selected. On the other hand, during the period in which the output control signal OCS is maintained in the disabled state, the low voltage output control signal LOCS and the low voltage holding control signal LOMS are sequentially enabled to output and maintain the gate low voltage VGL. The first to twelfth switch control signals SCS1 to SCS12 having conditions are selected.

The logic control signal LCS includes the first to twelfth switch control signals SCS1 to SCS12 during the high voltage output period T_HO, the high voltage sustain period T_HM, the low voltage output period T_LO, and the low voltage sustain period T_LM. Control the logic state.

The switch control unit SCB may include the first through twelfth switch control signals SCS1 through D so that the gate high voltage VGH and the gate low voltage VGL can be pumped in a preset multiple according to the logic value of the logic control signal LCS. The logic value of SCS12) is controlled.

This logic control signal LCS can be digital data of 3 bits. Of course, this logic control signal LCS can be digital data exceeding 3 bits.

The operation of the switch control unit SCB when the logic control signal LCS is 3-bit digital data will be described as follows.

4 is a table showing the pumping multiples of the gate high voltage VGH and the gate low voltage VGL according to the digital code of the 3-bit logic control signal LCS.

When the logic control signal LCS is three bits, the logic control signal LCS may have any one of eight digital codes from 000 to 111 in total. BT [2] in FIG. 3 means a logic value of the highest weighted bit among the three bits, BT [1] means a logic value of the middle weighted next to the most significant bit, and BT [0] means the logical value of the least significant bit with the lowest weight.

When the digital code of the logic control signal LCS is 000, as shown in FIG. 3, the switch control unit SCB has four times the gate high voltage VGH and the gate low voltage VGL with respect to the reference voltage VCI, respectively. And a logic value of the first to twelfth switch control signals SCS1 to SCS12 so as to have a size three times larger.

When the digital code of the logic control signal LCS is 001, as shown in FIG. 3, the switch controller SCB has four times the gate high voltage VGH and the gate low voltage VGL with respect to the reference voltage VCI, respectively. The logic values of the first to twelfth switch control signals SCS1 to SCS12 are controlled to have a magnitude of.

When the digital code of the logic control signal LCS is 010, as shown in FIG. 3, the switch control unit SCB has a gate high voltage VGH and a gate low voltage VGL 5 times the reference voltage VCI, respectively. And a logic value of the first to twelfth switch control signals SCS1 to SCS12 so as to have a size three times larger.

When the digital code of the logic control signal LCS is 011, as shown in FIG. 3, the switch controller SCB has five times the gate high voltage VGH and the gate low voltage VGL with respect to the reference voltage VCI, respectively. And a logic value of the first to twelfth switch control signals SCS1 to SCS12 so as to have a size four times as large.

When the digital code of the logic control signal LCS is 100, as shown in FIG. 3, the switch control unit SCB has five times the gate high voltage VGH and the gate low voltage VGL with respect to the reference voltage VCI, respectively. The logic values of the first to twelfth switch control signals SCS1 to SCS12 are controlled to have a magnitude of.

When the digital code of the logic control signal LCS is 101, as shown in FIG. 3, the switch control unit SCB has a gate high voltage VGH and a gate low voltage VGL 6 times the reference voltage VCI, respectively. And a logic value of the first to twelfth switch control signals SCS1 to SCS12 so as to have a size three times larger.

When the digital code of the logic control signal LCS is 110, as shown in FIG. 3, the switch controller SCB has a gate high voltage VGH and a gate low voltage VGL that are six times the reference voltage VCI, respectively. And a logic value of the first to twelfth switch control signals SCS1 to SCS12 so as to have a size four times as large.

When the digital code of the logic control signal LCS is 111, as shown in FIG. 3, the switch control unit SCB has a gate high voltage VGH and a gate low voltage VGL 6 times the reference voltage VCI, respectively. And a logic value of the first to twelfth switch control signals SCS1 to SCS12 so as to have a size of five times.

The pumping unit PB configured as described above supplies the gate driver with the gate high voltage VGH pumped in any one of 4 times, 5 times, and 6 times through the high potential output terminal HT. In addition, the pumping part PB supplies the gate driver with the gate low voltage VGL pumped in any one of three, four, and five times through the low potential output terminal LT.

The operation of the pumping unit PB according to the embodiment of the present invention configured as described above will be described in detail as follows.

1) Logic control signal LCS ) According to 000

FIG. 5 shows the first of the first to twelfth switch control signals SCS1 to SCS12 outputted from the switch control unit SCB when the digital code of the logic control signal LCS supplied to the switch control unit SCB is 000. FIG. It is a figure which shows a timing diagram. 6A to 6D are diagrams for describing operations of the first to twelfth switches SW1 to SW12 according to the first to twelfth switch control signals SCS1 to SCS12 of FIG. 5.

During the high voltage output period T_HO, as shown in Fig. 5A, the first, third, fourth, seventh and eleventh switch control signals SSC1, SSC3, SSC4, SSC7 and SCS11 are active. State, while the remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage output period T_HO, the first to twelfth switches in the high voltage output period T_HO in the manner as shown in Fig. 5A. Control signals SCS1 to SCS12 are output.

During the high voltage holding period T_HM, as shown in Fig. 5A, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage holding period T_HM, the first to twelfth switches are operated during the high voltage holding period T_HM in the manner as shown in Fig. 5A. Control signals SCS1 to SCS12 are output.

During the low voltage output period T_LO, as shown in FIG. 5B, the first, fourth, eighth, ninth and twelfth switch control signals SSC1, SSC4, SSC8, SSC9, and SCS12 are active. State, and the remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in an inactive state during this low voltage output period T_LO, the first to twelfth to the low voltage output period T_LO in the manner as shown in Fig. 5B. The switch control signals SCS1 to SCS12 are output.

During the low voltage holding period T_LM, as shown in FIG. 5B, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage holding period T_LM, the first to twelfth times in this low voltage holding period T_LM in the manner as shown in Fig. 5B. The switch control signals SCS1 to SCS12 are output.

Referring to FIGS. 5A and 6A, the operation of the pumping unit PB during the high voltage output period T_HO will be described as follows.

The first, third, fourth, seventh, and eleventh switch control signals SSC1, SSC3, SSC4, SSC7, and SCS11 remain active during the high voltage output period T_HO, so that the first and third receiving them are supplied. , Fourth, seventh and eleventh switches SW1, SW3, SW4, SW7, and SW11 are all turned on. On the other hand, all the switches except the others are turned off.

Then, the first node N1 is charged to the input voltage DDVDH level by the turned-on first switch SW1. Here, the input voltage DDVDH is twice the reference voltage VCI.

In addition, the third node N3 is charged to the ground voltage VSS level by the turned-on fourth switch SW4. Here, the ground voltage VSS may be a voltage of 0 [V].

In addition, the fifth and fourth nodes N5 and N4 are charged to the ground voltage VSS level by the turned-on eleventh and seventh switches SW11 and SW7, respectively.

On the other hand, the second node N2 is charged to the four times the reference voltage (4 * VCI) level applied during the low voltage holding period (T_LM) of the previous period. If this high voltage output period T_HO is included in the first period, the voltage level of this second node N2 depends on the capacity of the second capacitor C2. However, in the high voltage output period T_HO of this second period after the first period, the second node N2 is stabilized to 4 times the reference voltage 4 * VCI.

At this time, the high potential output terminal HT is charged to the reference voltage 4 * VCI of 4 times by the turned-on third switch SW3.

As a result, four times the reference voltage 4 * VCI is output as the gate high voltage VGH through the high potential output terminal HT during this high voltage output period T_HO.

Next, referring to FIGS. 5A and 6B, the operation of the pumping unit PB during the high voltage sustain period T_HM will be described.

The second, fifth, seventh, and eleventh switch control signals SSC2, SSC5, SSC7, and SCS11 remain active during the high voltage sustain period T_HM, so that the second, fifth, seventh, and seventh to receive them. 11 The switches SW2, SW5, SW7, and SW11 are all turned on. On the other hand, all the switches except the others are turned off.

Then, the first and second nodes N1 and N2 remain in a floating state with each other.

At this time, as the input voltage DDVDH is supplied to the third node N3 through the turned-on fifth switch SW5, the voltage level of the third node N3 is increased from the base voltage VSS level. DDVDH) level rises, and the voltage level of the 1st and 2nd nodes N1 and N2 in a floating state also raises by the voltage rise of this 3rd node N3. In other words, the voltage levels of the first and second nodes N1 and N2 rise to four times the reference voltage (4 * VCI) level from the input voltage DDVDH level.

Meanwhile, the fifth and fourth nodes N5 and N4 are maintained at the base voltage VSS level by the turned-on eleventh and seventh switches SW7.

In addition, as the third switch SW3 is turned off in this period, the quadrature reference voltage 4 * VCI, which has been supplied to the high potential output terminal HT during the high voltage output period T_HO, becomes the third capacitor ( Maintained by C3).

As a result, four times the reference voltage 4 * VCI is maintained as the gate high voltage VGH in the high potential output terminal HT during this high voltage holding period T_HM.

Next, the operation of the pumping unit PB during the low voltage output period T_LO will be described with reference to FIGS. 5B and 6C as follows.

During the low voltage output period T_LO, the first, fourth, eighth, ninth and twelfth switch control signals SSC1, SSC4, SSC8, SSC9, and SCS12 remain in an active state, so that the first and fourth receiving them are supplied. , The eighth, ninth and twelfth switches SW1, SW4, SW8, SW9, and SW12 are all turned on. On the other hand, all the switches except the others are turned off.

Then, the first node N1 is charged to the input voltage DDVDH level by the turned-on first switch SW1.

In addition, the third node N3 is discharged to the ground voltage VSS level by the turned-on fourth switch SW4.

In addition, the fourth node N4 and the low potential output terminal LT are maintained in a floating state.

Meanwhile, the fourth node N4 may be maintained in the floating state for a short time when the ninth switch SW9 changes from the turn-off state to the turn-on state. To this end, in the low voltage output period T_LO, the ninth switch SW9 is set to be turned on later than the first, fourth, eighth and twelfth switches SW1, SW4, SW8, SW9, and SW12. Can be.

At this time, as the low voltage VCL is supplied to the fifth and second nodes N5 and N2 through the turned-on twelfth and eighth switches SW12 and SW8, the fifth and second nodes N5 and N2. The voltage level of V is lowered from 4 times the reference voltage (4 * VCI) level to 1 times the reference voltage (VCI) level, and the floating state is lowered by the voltage drop of the fifth and second nodes N5 and N2. The voltage level of the four nodes N4 also falls. That is, the voltage level of the fourth node N4 drops to the reference voltage (-3 * VCI) level of -3 times from the base voltage VSS level. Here, the low voltage VCL has a polarity opposite to that of the reference voltage VCI. For example, if the reference voltage 4 * VCI is a positive voltage of 2.8 [V], this low voltage VCL is a negative voltage of -2.8 [V].

At this time, the low potential output terminal LT is discharged to the reference voltage (−3 * VCI) of −3 times by the turned-on ninth switch SW9. This -3 times the reference voltage (-3 * VCI) is a negative voltage.

As a result, a reference voltage (-3 * VCI) of -3 times is output as the gate low voltage VGL through the low potential output terminal LT during this low voltage output period T_LO.

Next, referring to FIGS. 5B and 6D, the operation of the pumping unit PB during the low voltage holding period T_LM will be described as follows.

The second, fifth, seventh, and eleventh switch control signals SSC2, SSC5, SSC7, and SCS11 remain active during the low voltage holding period T_LM. 11 The switches SW2, SW5, SW7, and SW11 are all turned on. On the other hand, all the switches except the others are turned off.

Then, the first and second nodes N1 and N2 remain in a floating state.

At this time, as the input voltage DDVDH is supplied to the third node N3 through the turned-on fifth switch SW5, the voltage level of the third node N3 is increased from the base voltage VSS level. DDVDH) level rises, and the voltage level of the 1st and 2nd nodes N1 and N2 in a floating state also raises by the voltage rise of this 3rd node N3. That is, the voltage levels of the first and second nodes N2 increase from the double reference voltage (2 * VCI) level to the four times reference voltage (4 * VCI) level.

In addition, the fifth and fourth nodes N4 are charged to the ground voltage VSS level by the turned-on eleventh and seventh switches SW11 and SW7.

In addition, as the ninth switch SW9 is turned off in this period, the -3 times the reference voltage (-3 * VCI) supplied to the low potential output terminal LT in the low voltage output period T_LO becomes the fourth. Held by capacitor C4.

As a result, a reference voltage (-3 * VCI) of -3 times is maintained as the gate low voltage VGL at the low potential output terminal LT during this low voltage holding period T_LM.

2) Logic control signal LCS ) In accordance with 001

FIG. 7 shows the second of the first to twelfth switch control signals SCS1 to SCS12 outputted from the switch control unit SCB when the digital code of the logic control signal LCS supplied to the switch control unit SCB is 001. It is a figure which shows a timing diagram. 8A to 8D are diagrams for describing operations of the first to twelfth switches SW1 to SW12 according to the first to twelfth switch control signals SCS1 to SCS12 of FIG. 7.

During the high voltage output period T_HO, as shown in Fig. 7A, the first, third, fourth, seventh and eleventh switch control signals SSC1, SSC3, SSC4, SSC7 and SCS11 are active. State, while the remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage output period T_HO, the first to twelfth switches in the high voltage output period T_HO in the manner as shown in Fig. 7A. Control signals SCS1 to SCS12 are output.

During the high voltage holding period T_HM, as shown in FIG. 7A, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7, and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in the active state during the high voltage holding period T_HM, the first to twelfth switches are operated in this high voltage holding period T_HM in the manner as shown in Fig. 7A. Control signals SCS1 to SCS12 are output.

During the low voltage output period T_LO, as shown in Fig. 7B, the first, fourth, eighth, ninth and eleventh switch control signals SSC1, SSC4, SSC8, SSC9, and SCS11 are active. State, and the remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage output period T_LO, the first to twelfth times in this low voltage output period T_LO in the manner as shown in Fig. 7B. The switch control signals SCS1 to SCS12 are output.

During the low voltage holding period T_LM, as shown in FIG. 7B, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in an inactive state during the low voltage holding period T_LM, the first to twelfth times in this low voltage holding period T_LM in the manner as shown in Fig. 7B. The switch control signals SCS1 to SCS12 are output.

The operation of the pumping unit PB during the high voltage output period T_HO according to FIGS. 7A and 8A is similar to the operation of the high voltage output period T_HO in FIGS. 5A and 6A described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the high voltage holding period T_HM according to FIGS. 7A and 8B is similar to the operation of the high voltage holding period T_HM in FIGS. 5A and 6B described above. Since it is the same, it is omitted here.

Next, referring to FIGS. 7B and 8C, the operation of the pumping unit PB during the low voltage output period T_LO will be described as follows.

During the low voltage output period T_LO, the first, fourth, eighth, ninth and eleventh switch control signals SSC1, SSC4, SSC8, SSC9, and SCS11 are kept in an active state, so that they are supplied with the first and fourth parts. , The eighth, ninth, and eleventh switches SW1, SW4, SW8, SW9, and SW11 are all turned on. On the other hand, all the switches except the others are turned off.

Then, the first node N1 is charged to the input voltage DDVDH level by the turned-on first switch SW1.

In addition, the third node N3 is discharged to the ground voltage VSS level by the turned-on fourth switch SW4.

In addition, the fourth node N4 and the low potential output terminal LT are maintained in a floating state.

Meanwhile, the fourth node N4 may be maintained in the floating state for a short time when the ninth switch SW9 changes from the turn-off state to the turn-on state. To this end, in the low voltage output period T_LO, the ninth switch SW9 may be set to be turned on later than the first, fourth, eighth and twelfth switches SW1, SW4, SW8, and SW12. .

At this time, as the base voltage VSS is supplied to the fifth and second nodes N5 and N2 through the turned-on eleventh and eighth switches SW8, the fifth and second nodes N5 and N2 are connected. The fourth node N4 in a floating state is lowered from the voltage level of 4 times the reference voltage (4 * VCI) level to the base voltage (VSS) level and the voltage drop of the fifth and second nodes N5 and N2. ) Will also fall. In other words, the voltage level of the fourth node N4 falls to the reference voltage (-4 * VCI) level of -4 times from the base voltage VSS level.

At this time, the low potential output terminal LT is discharged to the reference voltage (-4 * VCI) of -4 times by the turned-on ninth switch SW9. This -4 times the reference voltage (-4 * VCI) level is a negative voltage.

As a result, during the low voltage output period T_LO, the reference voltage (-4 * VCI) of -4 times is output as the gate low voltage VGL through the low potential output terminal LT.

The operation of the pumping unit PB during the low voltage holding period T_LM according to FIGS. 7B and 8D is similar to the operation of the high voltage holding period T_HM in FIGS. 5B and 6D described above. Since it is the same, it is omitted here.

3) Logic control signal LCS ) According to 010

FIG. 9 shows the third of the first to twelfth switch control signals SCS1 to SCS12 outputted from the switch control unit SCB when the digital code of the logic control signal LCS supplied to the switch control unit SCB is 010. It is a figure which shows a timing diagram. 10A to 10D are diagrams for describing operations of the first to twelfth switches SW1 to SW12 according to the first to twelfth switch control signals SCS1 to SCS12 of FIG. 9.

During the high voltage output period T_HO, as shown in Fig. 9A, the first, third, fourth, seventh and twelfth switch control signals SSC1, SSC3, SSC4, SSC7, and SCS12 are active. State, while the remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage output period T_HO, the first to twelfth switches in the high voltage output period T_HO in the manner as shown in Fig. 9A. Control signals SCS1 to SCS12 are output.

During the high voltage holding period T_HM, as shown in Fig. 9A, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage holding period T_HM, the first to twelfth switches are operated during the high voltage holding period T_HM in the manner as shown in Fig. 9A. Control signals SCS1 to SCS12 are output.

During the low voltage output period T_LO, as shown in Fig. 9B, the first, fourth, eighth, ninth and twelfth switch control signals SSC1, SSC4, SSC8, SSC9 and SCS12 are active. State, and the remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during this low voltage output period T_LO, the first to twelfth to the low voltage output period T_LO in the manner as shown in Fig. 9B. The switch control signals SCS1 to SCS12 are output.

During the low voltage holding period T_LM, as shown in FIG. 9B, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage holding period T_LM, the first to twelfth times in this low voltage holding period T_LM in the manner as shown in Fig. 9B. The switch control signals SCS1 to SCS12 are output.

Referring to FIGS. 9A and 10A, the operation of the pumping unit PB during the high voltage output period T_HO will be described as follows.

During the high voltage output period T_HO, the first, third, fourth, seventh and twelfth switch control signals SSC1, SSC3, SSC4, SSC7, and SCS12 remain active, so that the first and third receiving them are supplied. , Fourth, seventh and twelfth switches SW1, SW3, SW4, SW7, SW12 are all turned on. On the other hand, all the switches except the others are turned off.

Then, the first node N1 is charged to the input voltage DDVDH level by the turned-on first switch SW1.

In addition, the third node N3 is charged to the ground voltage VSS level by the turned-on fourth switch SW4. Here, the ground voltage VSS may be a voltage of 0 [V].

In addition, the fifth and fourth nodes N5 and N4 are charged to the low voltage VCL level by the turned on twelfth and seventh switches SW12 and SW7, respectively.

On the other hand, the second node N2 is charged to the four times the reference voltage (4 * VCI) level applied during the low voltage holding period (T_LM) of the previous period. If this high voltage output period T_HO is included in the first period, the voltage level of this second node N2 depends on the capacity of the second capacitor C2. However, in the high voltage output period T_HO of this second period after the first period, the second node N2 is stabilized to 4 times the reference voltage 4 * VCI.

In addition, the second node N2 and the high potential output terminal HT remain in a floating state.

Meanwhile, the second node N2 may be maintained in the floating state for a short time when the third switch SW3 changes from the turn-off state to the turn-on state. To this end, the third switch SW3 may be set to be turned on later than the first, fourth, seventh and twelfth switches SW1, SW4, SW7, and SW12 in the high voltage output period T_HO.

At this time, as the reference voltage VCI is supplied to the fifth and fourth nodes N5 and N4 through the turned-on twelfth and seventh switches SW12 and SW7, the fifth and fourth nodes N5 and N4. ) Increases from the base voltage (VSS) level to the reference low voltage level, and increases the voltage level of the second node (N2) in the floating state by the voltage increase of the fifth and fourth nodes (N5, N4). do. That is, the voltage level of the second node N2 rises from four times the reference voltage (4 * VCI) level to five times the reference voltage (5 * VCI) level.

At this time, the high potential output terminal HT is charged to the reference voltage 5 * VCI 5 times by the turned-on third switch SW3.

As a result, five times the reference voltage 5 * VCI is output as the gate high voltage VGH through the high potential output terminal HT during this high voltage output period T_HO.

The operation of the pumping unit PB during the high voltage holding period T_HM according to FIGS. 9A and 10B is similar to the operation of the high voltage holding period T_HM in FIGS. 5A and 6B described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage output period T_LO according to FIGS. 9B and 10C is similar to the operation of the low voltage output period T_LO in FIGS. 5B and 6C described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage holding period T_LM according to FIGS. 9B and 10D is similar to the operation of the low voltage holding period T_LM in FIGS. 5B and 6D described above. Since it is the same, it is omitted here.

4) Logic control signal LCS ) According to 011

FIG. 11 shows the fourth of the first to twelfth switch control signals SCS1 to SCS12 outputted from the switch control unit SCB when the digital code of the logic control signal LCS supplied to the switch control unit SCB is 011. It is a figure which shows a timing diagram. 12A to 12D are diagrams for describing operations of the first to twelfth switches SW1 to SW12 according to the first to twelfth switch control signals SCS1 to SCS12 of FIG. 11.

During the high voltage output period T_HO, as shown in FIG. 11A, the first, third, fourth, seventh and twelfth switch control signals SSC1, SSC3, SSC4, SSC7, and SCS12 are active. State, while the remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage output period T_HO, the first to twelfth switches in the high voltage output period T_HO in the manner as shown in Fig. 11A. Control signals SCS1 to SCS12 are output.

During the high voltage holding period T_HM, as shown in Fig. 11A, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in the active state during the high voltage holding period T_HM, the first to twelfth switches are operated in this high voltage holding period T_HM in the manner as shown in Fig. 11A. Control signals SCS1 to SCS12 are output.

During the low voltage output period T_LO, as shown in Fig. 11B, the first, fourth, eighth, ninth and eleventh switch control signals SSC1, SSC4, SSC8, SSC9 and SCS11 are active. State, and the remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage output period T_LO, the first to twelfth times in this low voltage output period T_LO in the manner as shown in Fig. 11B. The switch control signals SCS1 to SCS12 are output.

During the low voltage holding period T_LM, as shown in FIG. 11B, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage holding period T_LM, the first to twelfth times in this low voltage holding period T_LM in the manner as shown in Fig. 11B. The switch control signals SCS1 to SCS12 are output.

The operation of the pumping unit PB during the high voltage output period T_HO according to FIGS. 11A and 12A is similar to the operation of the high voltage output period T_HO in FIGS. 9A and 10A described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the high voltage holding period T_HM according to FIGS. 11A and 12B is similar to the operation of the high voltage holding period T_HM in FIGS. 9A and 10B described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage output period T_LO according to FIGS. 11B and 12C is similar to the operation of the low voltage output period T_LO in FIGS. 7B and 8C described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage holding period T_LM according to FIGS. 11B and 12D is similar to the operation of the low voltage holding period T_LM in FIGS. 7B and 8D described above. Since it is the same, it is omitted here.

5) Logic control signal LCS ) According to 100

FIG. 13 shows the fifth of the first to twelfth switch control signals SCS1 to SCS12 outputted from the switch control unit SCB when the digital code of the logic control signal LCS supplied to the switch control unit SCB is 100. FIG. It is a figure which shows a timing diagram. 14A to 14D are diagrams for describing operations of the first to twelfth switches SW1 to SW12 according to the first to twelfth switch control signals SCS1 to SCS12 of FIG. 13.

During the high voltage output period T_HO, as shown in Fig. 13A, the first, third, fourth, seventh and twelfth switch control signals SSC1, SSC3, SSC4, SSC7, and SCS12 are active. State, while the remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in the active state during the high voltage output period T_HO, the first to twelfth switches in the high voltage output period T_HO in the manner as shown in Fig. 13A. Control signals SCS1 to SCS12 are output.

During the high voltage holding period T_HM, as shown in FIG. 13A, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in the active state during the high voltage holding period T_HM, the first to twelfth switches are operated in this high voltage holding period T_HM in the manner as shown in Fig. 13A. Control signals SCS1 to SCS12 are output.

During the low voltage output period T_LO, as shown in FIG. 13B, the first, fourth, eighth, ninth and tenth switch control signals SSC1, SSC4, SSC8, SSC9, and SCS10 are active. State, and the remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in an inactive state during the low voltage output period T_LO, the first to twelfth to the low voltage output period T_LO in the manner as shown in Fig. 13B. The switch control signals SCS1 to SCS12 are output.

During the low voltage holding period T_LM, as shown in FIG. 13B, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage holding period T_LM, the first to twelfth to the low voltage holding period T_LM in the manner as shown in Fig. 13B. The switch control signals SCS1 to SCS12 are output.

The operation of the pumping unit PB during the high voltage output period T_HO according to FIGS. 13A and 14A is similar to the operation of the high voltage output period T_HO in FIGS. 9A and 10A described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the high voltage holding period T_HM according to FIGS. 13A and 14B is similar to the operation of the high voltage holding period T_HM in FIGS. 9A and 10B described above. Since it is the same, it is omitted here.

Next, referring to FIGS. 13B and 14C, the operation of the pumping unit PB during the low voltage output period T_LO will be described.

The first, fourth, eighth, ninth, and tenth switch control signals SSC1, SSC4, SSC8, SSC9, and SCS10 remain active during the low voltage output period T_LO, and thus the first and fourth receiving them are supplied. , The eighth, ninth, and tenth switches SW1, SW4, SW8, SW9, and SW10 are all turned on. On the other hand, all the switches except the others are turned off.

Then, the first node N1 is charged to the input voltage DDVDH level by the turned-on first switch SW1.

In addition, the third node N3 is discharged to the ground voltage VSS level by the turned-on fourth switch SW4.

In addition, the fourth node N4 and the low potential output terminal LT are maintained in a floating state.

Meanwhile, the fourth node N4 may be maintained in the floating state for a short time when the ninth switch SW9 changes from the turn-off state to the turn-on state. To this end, in the low voltage output period T_LO, the ninth switch SW9 may be set to be turned on later than the first, fourth, eighth and tenth switches SW1, SW4, SW8, and SW10. have.

At this time, as the low voltage VCL is supplied to the fifth and second nodes N5 and N2 through the turned-on tenth and eighth switches SW10 and SW8, the fifth and second nodes N5 and N2. The voltage level of V is lowered from 4 times the reference voltage (4 * VCI) level to 1 times the reference voltage level (VCI), and the floating state is lowered by the voltage drop of the fifth and second nodes N5 and N2. The voltage level of the four nodes N4 also falls. That is, the voltage level of the fourth node N4 drops to the reference voltage (-5 * VCI) level of -5 times from the base voltage VSS level.

At this time, the low potential output terminal LT is discharged to the reference voltage (-5 * VCI) of -5 times by the turned-on ninth switch SW9.

As a result, during the low voltage output period T_LO, the reference voltage (-5 * VCI) of -5 times is output as the gate low voltage VGL through the low potential output terminal LT.

The operation of the pumping unit PB during the low voltage holding period T_LM according to FIGS. 13B and 14D is similar to the operation of the low voltage holding period T_LM in FIGS. 5B and 6D described above. Since it is the same, it is omitted here.

6) Logic control signal LCS ) According to 101

FIG. 15 shows the sixth of the first to twelfth switch control signals SCS1 to SCS12 outputted from the switch control unit SCB when the digital code of the logic control signal LCS supplied to the switch control unit SCB is 101. FIG. It is a figure which shows a timing diagram. 16A to 16D are diagrams for describing operations of the first to twelfth switches SW1 to SW12 according to the first to twelfth switch control signals SCS1 to SCS12 of FIG. 15.

During the high voltage output period T_HO, as shown in Fig. 15A, the first, third, fourth and sixth switch control signals SCS1, SCS3, SCS4 and SCS6 remain active. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage output period T_HO, the first to twelfth switches in the high voltage output period T_HO in the manner as shown in Fig. 15A. Control signals SCS1 to SCS12 are output.

During the high voltage holding period T_HM, as shown in FIG. 15A, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage holding period T_HM, the first to twelfth switches are operated in this high voltage holding period T_HM in the manner as shown in Fig. 15A. Control signals SCS1 to SCS12 are output.

During the low voltage output period T_LO, as shown in Fig. 15B, the first, fourth, eighth, ninth and twelfth switch control signals SSC1, SSC4, SSC8, SSC9 and SCS12 are active. State, and the remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage output period T_LO, the first to twelfth to the low voltage output period T_LO in the manner as shown in Fig. 15B. The switch control signals SCS1 to SCS12 are output.

During the low voltage holding period T_LM, as shown in FIG. 15B, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in an inactive state during the low voltage holding period T_LM, the first to twelfth to the low voltage holding period T_LM in the manner as shown in Fig. 15B. The switch control signals SCS1 to SCS12 are output.

Referring to FIGS. 15A and 16A, the operation of the pumping unit PB during the high voltage output period T_HO will be described as follows.

During the high voltage output period T_HO, the first, third, fourth and sixth switch control signals SCS1, SCS3, SCS4, and SCS6 remain in an active state, and thus the first, third, fourth and fourth to receive them. 6 Switches SW1, SW3, SW4, and SW6 are all turned on. On the other hand, all the switches except the others are turned off.

Then, the first node N1 is charged to the input voltage DDVDH level by the turned-on first switch SW1.

In addition, the third node N3 is charged to the ground voltage VSS level by the turned-on fourth switch SW4. here,

In addition, the fourth node N4 is increased from the base voltage VSS level to the input voltage DDVDH level by the turned-on sixth switch.

On the other hand, the second node N2 is charged to the four times the reference voltage (4 * VCI) level applied during the low voltage holding period (T_LM) of the previous period. If this high voltage output period T_HO is included in the first period, the voltage level of this second node N2 depends on the capacity of the second capacitor C2. However, in the high voltage output period T_HO of this second period after the first period, the second node N2 is stabilized to 4 times the reference voltage 4 * VCI.

In addition, the second node N2 and the high potential output terminal HT remain in a floating state.

Meanwhile, the second node N2 may be maintained in the floating state for a short time when the third switch SW3 changes from the turn-off state to the turn-on state. To this end, the third switch SW3 may be set to be turned on later than the first, fourth and sixth switches SW1, SW4 and SW6 in the high voltage output period T_HO.

At this time, as the input voltage DDVDH is supplied to the fourth node N4 through the turned-on sixth switch SW6, the voltage level of the fourth node N4 is increased from the base voltage VSS level. The voltage level of the second node N2 in the floating state is also increased by the voltage rise of the fourth node N4. That is, the voltage level of the second node N2 rises from four times the reference voltage (4 * VCI) level to six times the reference voltage (6 * VCI) level.

At this time, the high potential output terminal HT is charged to the reference voltage 6 * VCI of 6 times by the turned-on third switch SW3.

As a result, six times the reference voltage 6 * VCI is output as the gate high voltage VGH through the high potential output terminal HT during this high voltage output period T_HO.

The operation of the pumping unit PB during the high voltage holding period T_HM according to FIGS. 15A and 16B is similar to the operation of the high voltage holding period T_HM in FIGS. 5A and 6B described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage output period T_LO according to FIGS. 15B and 16C is similar to the operation of the low voltage output period T_LO in FIGS. 5B and 6C described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage holding period T_LM according to FIGS. 15B and 16D is similar to the operation of the low voltage holding period T_LM in FIGS. 5B and 6D described above. Since it is the same, it is omitted here.

7) Logic control signal LCS ) According to 110

FIG. 17 shows seventh of first to twelfth switch control signals SCS1 to SCS12 outputted from the switch control unit SCB when the digital code of the logic control signal LCS supplied to the switch control unit SCB is 110. FIG. It is a figure which shows a timing diagram. 18A to 18D are diagrams for describing operations of the first to twelfth switches SW1 to SW12 according to the first to twelfth switch control signals SCS1 to SCS12 of FIG. 17.

During the high voltage output period T_HO, as shown in Fig. 17A, the first, third, fourth and sixth switch control signals SCS1, SCS3, SCS4 and SCS6 remain active. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage output period T_HO, the first to twelfth switches in the high voltage output period T_HO in the manner as shown in Fig. 17A. Control signals SCS1 to SCS12 are output.

During the high voltage sustain period T_HM, as shown in FIG. 17A, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage holding period T_HM, the first to twelfth switches in the high voltage holding period T_HM in the manner as shown in Fig. 17A. Control signals SCS1 to SCS12 are output.

During the low voltage output period T_LO, as shown in FIG. 17B, the first, fourth, eighth, ninth and eleventh switch control signals SSC1, SSC4, SSC8, SSC9 and SCS11 are active. State, and the remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in an inactive state during this low voltage output period T_LO, the first to twelfth to the low voltage output period T_LO in the manner as shown in Fig. 17B. The switch control signals SCS1 to SCS12 are output.

During the low voltage holding period T_LM, as shown in FIG. 17B, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage holding period T_LM, the first to twelfth to the low voltage holding period T_LM in the manner as shown in Fig. 17B. The switch control signals SCS1 to SCS12 are output.

The operation of the pumping unit PB during the high voltage output period T_HO according to FIGS. 17A and 18A is similar to the operation of the high voltage output period T_HO in FIGS. 15A and 16A described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the high voltage holding period T_HM according to FIGS. 17A and 18B is similar to the operation of the high voltage holding period T_HM in FIGS. 5A and 6B described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage output period T_LO according to FIGS. 17B and 18C is similar to the operation of the low voltage output period T_LO in FIGS. 7B and 8C described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage holding period T_LM according to FIGS. 17B and 18D is similar to the operation of the low voltage holding period T_LM in FIGS. 7B and 8D described above. Since it is the same, it is omitted here.

8) Logic control signal LCS ) According to 111

FIG. 19 shows the eighth of the first to twelfth switch control signals SCS1 to SCS12 outputted from the switch control unit SCB when the digital code of the logic control signal LCS supplied to the switch control unit SCB is 111; It is a figure which shows a timing diagram. 20A to 20D are diagrams for describing operations of the first to twelfth switches SW1 to SW12 according to the first to twelfth switch control signals SCS1 to SCS12 of FIG. 19.

During the high voltage output period T_HO, as shown in Fig. 19A, the first, third, fourth and sixth switch control signals SCS1, SCS3, SCS4, and SCS6 remain active. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage output period T_HO, the first to twelfth switches in the high voltage output period T_HO in the manner as shown in Fig. 19A. Control signals SCS1 to SCS12 are output.

During the high voltage holding period T_HM, as shown in FIG. 19A, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is kept in the active state during the high voltage holding period T_HM, the first to twelfth switches are operated during the high voltage holding period T_HM in the manner as shown in Fig. 19A. Control signals SCS1 to SCS12 are output.

During the low voltage output period T_LO, as shown in Fig. 19B, the first, fourth, eighth, ninth and tenth switch control signals SSC1, SSC4, SSC8, SSC9 and SCS10 are active. State, and the remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage output period T_LO, the first to twelfth times in this low voltage output period T_LO in the manner as shown in Fig. 19B. The switch control signals SCS1 to SCS12 are output.

During the low voltage holding period T_LM, as shown in FIG. 19B, the second, fifth, seventh and eleventh switch control signals SSC2, SSC5, SSC7 and SCS11 are kept in an active state. The remaining switch control signals remain inactive. That is, since the output control signal OCS is maintained in an inactive state during the low voltage holding period T_LM, the first to twelfth to the low voltage holding period T_LM in the manner as shown in Fig. 19B. The switch control signals SCS1 to SCS12 are output.

The operation of the pumping unit PB during the high voltage output period T_HO according to FIGS. 19A and 20A is similar to the operation of the high voltage output period T_HO in FIGS. 15A and 16A described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the high voltage holding period T_HM according to FIGS. 19A and 20B is similar to the operation of the high voltage holding period T_HM in FIGS. 5A and 6B described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage output period T_LO according to FIGS. 19B and 20C is similar to the operation of the low voltage output period T_LO in FIGS. 13B and 14C described above. Since it is the same, it is omitted here.

The operation of the pumping unit PB during the low voltage holding period T_LM according to FIGS. 19B and 20D is similar to the operation of the low voltage holding period T_LM in FIGS. 5B and 6D described above. Since it is the same, it is omitted here.

On the other hand, the switch control unit (SCB) may be supplied with the following signals instead of the signals as shown in FIG.

FIG. 21 is another diagram illustrating various signals supplied to the switch control unit SCB of FIG. 1.

As shown in Fig. 21, this switch control unit SCB has a high voltage output control signal HOCS, a high voltage holding control signal HOMS, a low voltage output control signal LOCS, and a low voltage holding control signal LOMS supplied thereto. And the first to twelfth switch control signals SCS1 to SCS12 described above based on the logic control signal LCS.

FIG. 22 shows waveforms of the high voltage output control signal HOCS, the high voltage holding control signal HOMS, the low voltage output control signal LOCS, and the low voltage holding control signal LOMS supplied to the switch control unit SCB of FIG. Drawing.

The high voltage output control signal HOCS has an enabled state during the high voltage output period T_HO, as shown in FIG. On the other hand, it has a disabled state for the remaining period except for the high voltage output period T_HO, that is, during the high voltage holding period T_HM, the low voltage output period T_LO and the low voltage holding period T_LM.

The high voltage holding control signal HOMS has an enabled state during the high voltage holding period T_HM, as shown in FIG. On the other hand, it has a disabled state for the remaining period except for the high voltage holding period T_HM, that is, during the high voltage output period T_HO, the low voltage output period T_LO, and the low voltage holding period T_LM.

The low voltage output control signal LOCS has an enabled state during the low voltage output period T_LO, as shown in FIG. On the other hand, it has a disabled state for the remaining period except the low voltage output period T_LO, that is, during the high voltage output period T_HO, the high voltage holding period T_HM and the low voltage holding period T_LM.

The low voltage holding control signal LOMS has an enabled state during the low voltage holding period T_LM, as shown in FIG. On the other hand, it has a disabled state for the remaining period except the low voltage holding period T_LM, that is, the high voltage output period T_HO, the high voltage holding period T_HM, and the low voltage output period T_LO.

FIG. 23 is another diagram illustrating various signals supplied to the switch control unit SCB of FIG. 1.

As shown in Fig. 23, this switch control unit SCB has an output control signal OCS, a high / low output control signal H / LOCS, a high / low maintenance control signal H / LOMS and a logic supplied thereto. The above-described first to twelfth switch control signals SCS1 to SCS12 are generated based on the control signal LCS.

FIG. 24 is a view showing waveforms of the output control signal OCS, the high / low output control signal OCS and the high / low maintenance control signal supplied to the switch control unit SCB of FIG.

The output control signal OCS has an enabled state during the continuous high voltage output period T_HO and the high voltage holding period T_HM, as shown in FIG. 24, and the continuous low voltage output period T_LO and low voltage holding subsequent. It has a disabled state for a period T_LM.

The high / low output control signal H / LOCS has an enable state during the high voltage output period T_HO and the low voltage output period T_LO in Fig. 24, and the high / low output control signal H / LOCS It has a disabled state for the rest of the period.

The high / low maintenance control signal H / LOMS has an enabled state during the high voltage holding period T_HM and the low voltage holding period T_LM, as shown in FIG. 24, and the high voltage holding period T_HM and the low voltage. It has a disabled state for the remaining period except for the sustain period T_LM.

The output control signal OCS is maintained in the enabled state every half of a period of one cycle, and the output control signal OCS is maintained in a disabled state every second half of a cycle. The first to twelfth switch control signals SCS1 to SCS12 having a condition for outputting and maintaining the gate high voltage VGH are selected during the period in which the output control signal OCS is maintained in the enabled state, while the output The first to twelfth switch control signals SCS1 to SCS12 having a condition for outputting and maintaining the gate low voltage VGL are selected while the control signal OCS is maintained in the disabled state.

When a signal is configured as shown in FIG. 24, only three types of signals are required, so that the number of signal transmission lines through which these signals are transmitted can be reduced.

Meanwhile, each of the first to twelfth switches SW1 to SW12 of FIG. 1 may be formed of a metal oxide semiconductor transistor (MOS transistor).

FIG. 25 is a diagram illustrating an example in which the first to twelfth switches SW1 to SW12 of FIG. 1 are configured as MOS transistors.

The first to third switches SW3, the fifth switch SW5, the sixth switch SW6, and the twelfth switch SW12 are each composed of P-type MOS transistors. The fourth switch SW4 and the seventh to eleventh switches SW7 to SW11 are each composed of N-type MOS transistors.

In this case, the first to third switches SW1 to SW3 and the sixth to ninth switches SW6 to SW9 may be formed of high-voltage MOS transistors, respectively. The fourth to fifth switches SW4 and SW5 and the tenth to twelfth switches SW10 to SW12 may be formed of MOS transistors having a medium voltage, respectively.

Medium voltage MOS transistors occupy much smaller area than high voltage MOS transistors. Thus, the use of medium voltage MOS transistors rather than high voltage MOS transistors is much more sustained in area reduction.

The use of high, medium and low voltage transistors is determined by the magnitude of the voltage between the source and drain electrodes of the MOS transistor (hereinafter referred to as source-drain voltage) and the voltage between the gate and bulk (hereinafter referred to as the gate-bulk voltage). do.

That is, when the source-drain voltage and the gate-bulk voltage of a transistor are both 1.5 to 6.6 [V], the transistor can be configured as a medium voltage transistor. On the other hand, when both the source-drain voltage and the gate-bulk voltage are less than 1.5 [V], the transistor can be configured as a low voltage transistor. In addition, when both the source-drain voltage and the gate-bulk voltage exceed 1.5 [V], this transistor should be configured as a high voltage transistor.

In the present invention, when the reference voltage VCI is 2.8 to 3.3 [V] and the base voltage VSS is 0 [V], the fourth to fifth switches SW4 and SW5 and the tenth to twelfth switches SW10. SW12) Each of the source-drain voltage and the gate-bulk voltage both fall in the range of 1.5 to 6.6 [V]. Therefore, in the present invention, the fourth to fifth switches SW4 and SW5 and the tenth to twelfth switches SW10 to SW12 can be configured as low voltage MOS transistors.

FIG. 26 is a view for comparing the switches provided in the pumping unit PB according to the present invention and the switches provided in the conventional pumping unit PB.

As shown in Fig. 26A, a total of 14 switches were conventionally required, but in the present invention, only 12 switches are required. In addition, although all 14 switches have to be configured as high voltage MOS transistors (HV_NMOS and HV_PMOS), in the present invention, only 7 switches smaller than this can be configured as high voltage MOS transistors (HV_NMOS and HV_PMOS). That is, as shown in FIG. 26B, the present invention requires seven high voltage MOS transistors HV_NMOS and HV_PMOS, and also requires five medium voltage MOS transistors MV_NMOS and MV_PMOS. On the other hand, conventionally, 14 high voltage MOS transistors (HV_NMOS, HV_PMOS) are required. The present invention requires 7 medium voltage transistors (MV_NMOS, MV_PMOS) more than in the prior art, but the present invention requires much smaller number of high voltage MOS transistors (HV_NMOS, HV_PMOS) than the conventional method. It has the advantage that the size can be significantly reduced compared to the conventional. In addition, the present invention is smaller than the conventional one in terms of the total number of switches, and therefore, the present invention is advantageous over the conventional one in terms of manufacturing cost.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

SCB: switch control part PB: pumping part
IT: Input terminal HT: High potential output terminal
LT: Low potential output terminal VCI: Reference voltage
VSS: Base Voltage DDVDH: Input Voltage
VCL: low voltage SCSm: m switch control signal
SWm: mth switch Nn: nth node
Cp: p-th capacitor VGH: gate high voltage
VGL: Gate Low Voltage

Claims (22)

In response to the first to twelfth switch control signals from the outside, pumping the input voltage input to the input terminal to a predetermined multiple to generate a gate high voltage and a gate low voltage, outputting the gate high voltage through the high potential output terminal, and A pumping part configured to output the gate low voltage through a low potential output terminal;
The pumping unit alternately outputs the gate high voltage and the gate low voltage;
The pumping unit outputs the gate high voltage during the high voltage output period, and then maintains the output gate high voltage during the high voltage sustain period; And then outputting the gate low voltage during the low voltage output period, and then maintaining the output gate low voltage during the low voltage sustain period;
The pumping unit includes first to twelfth switches and first to fourth capacitors to receive the first to twelfth switch control signals;
The first switch is controlled by the first switch control signal to electrically connect or disconnect the input terminal and the first node from each other;
The second switch is controlled by the second switch control signal to electrically connect or disconnect the first node and the second node from each other;
The third switch is controlled by the third switch control signal to electrically connect or disconnect the second node and the high potential output terminal from each other;
The fourth switch is controlled by the fourth switch control signal to electrically connect or disconnect a third node and a base power source from each other;
The fifth switch is controlled by the fifth switch control signal to electrically connect or disconnect between the third node and the input terminal;
The sixth switch is controlled by the sixth switch control signal to electrically connect or disconnect a fourth node and the input terminal from each other;
The seventh switch is controlled by the seventh switch control signal to electrically connect or disconnect the fourth node and the fifth node from each other;
The eighth switch is controlled by the eighth switch control signal to electrically connect or disconnect the second node and the fifth node from each other;
The ninth switch is controlled by the ninth switch control signal to electrically connect or disconnect the fourth node and the low potential output terminal from each other;
The tenth switch is controlled by the tenth switch control signal to electrically connect or disconnect the fifth node and the low potential power source from each other;
The eleventh switch is controlled by the eleventh switch control signal to electrically connect or disconnect the fifth node and the base power source from each other;
The twelfth switch is controlled by the twelfth switch control signal to electrically connect or disconnect the fifth node from the reference power source;
The first capacitor is connected between a first node and a third node;
The second capacitor is connected between the second node and a fourth node;
The third capacitor is connected between the high potential output terminal and a ground power source;
And said fourth capacitor is connected between said low potential output terminal and a ground power supply. delete delete delete The method of claim 1,
And a switch control unit for generating and outputting first to twelfth switch control signals for controlling the first to twelfth switches. The method of claim 5, wherein
The switch control unit,
An output control signal having an enable state for a continuous high voltage output period and a high voltage sustain period, and having a disable state for a subsequent low voltage output period and a low voltage sustain period;
A high voltage output control signal having an enable state for the high voltage output period and having a disable state for a period other than the high voltage output period;
A high voltage maintenance control signal having an enable state during the high voltage maintenance period and having a disable state for a period other than the high voltage maintenance period;
A low voltage output control signal having an enable state for the low voltage output period and having a disable state for the rest of the period except the low voltage output period;
A low voltage maintenance control signal having an enable state during the low voltage maintenance period and having a disable state for a period other than the low voltage maintenance period; And,
Generating the first to twelfth switch control signals based on a logic control signal for controlling the logic states of the first to twelfth switch control signals during the high voltage output period, the high voltage sustain period, the low voltage output period, and the low voltage sustain period; DC-DC converter circuit characterized in that. The method according to claim 6,
The switch control unit,
And a logic value of the first to twelfth switch control signals is controlled to pump the gate high voltage and the gate low voltage in a preset multiple according to the logic value of the logic control signal. The method of claim 7, wherein
And said logic control signal is 3-bit digital data. The method of claim 8,
When the digital code of the logic control signal is 000, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are four times and three times larger than the input voltage, respectively. Control the value;
When the digital code of the logic control signal is 001, the switch control unit controls the logic values of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are four times larger than the input voltage, respectively. To;
When the digital code of the logic control signal is 010, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 5 times and 3 times larger than the input voltage, respectively. Control the value;
When the digital code of the logic control signal is 011, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 5 times and 4 times larger than the input voltage, respectively. Control the value;
When the digital code of the logic control signal is 100, the switch control unit controls the logic values of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are five times larger than the input voltage, respectively. To;
When the digital code of the logic control signal is 101, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 6 times and 3 times larger than the input voltage, respectively. Control the value;
When the digital code of the logic control signal is 110, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 6 times and 4 times larger than the input voltage, respectively. Control the value; And,
When the digital code of the logic control signal is 111, the switch control unit logic of the first to twelfth switch control signals such that the gate high voltage and the gate low voltage are 6 times and 5 times larger than the input voltage, respectively. DC-DC converter circuit, characterized in that to control the value. The method of claim 9,
When the digital code of the logic control signal is 000,
During the high voltage output period, the first, third, fourth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the low voltage output period, the first, fourth, eighth, ninth and twelfth switch control signals remain active, and the remaining switch control signals remain inactive; And,
During the low voltage holding period, the switch control unit is further configured to maintain the second, fifth, seventh and eleventh switch control signals in an active state and the remaining switch control signals in an inactive state. DC-DC converter circuit for controlling the logic value of the switch control signal. The method of claim 9,
When the digital code of the logic control signal is 001,
During the high voltage output period, the first, third, fourth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the low voltage output period, the first, fourth, eighth, ninth and eleventh switch control signals remain active and the remaining switch control signals remain inactive; And,
During the low voltage holding period, the switch control unit is further configured to maintain the second, fifth, seventh and eleventh switch control signals in an active state and the remaining switch control signals in an inactive state. DC-DC converter circuit for controlling the logic value of the switch control signal. The method of claim 9,
When the digital code of the logic control signal is 010,
During the high voltage output period, the first, third, fourth, seventh and twelfth switch control signals remain active, and the remaining switch control signals remain inactive;
During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the low voltage output period, the first, fourth, eighth, ninth and twelfth switch control signals remain active, and the remaining switch control signals remain inactive; And,
During the low voltage holding period, the switch control unit is further configured to maintain the second, fifth, seventh and eleventh switch control signals in an active state and the remaining switch control signals in an inactive state. DC-DC converter circuit for controlling the logic value of the switch control signal. The method of claim 9,
When the digital code of the logic control signal is 011,
During the high voltage output period, the first, third, fourth, seventh and twelfth switch control signals remain active, and the remaining switch control signals remain inactive;
During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the low voltage output period, the first, fourth, eighth, ninth and eleventh switch control signals remain active and the remaining switch control signals remain inactive; And,
During the low voltage holding period, the switch control unit is further configured to maintain the second, fifth, seventh and eleventh switch control signals in an active state and the remaining switch control signals in an inactive state. DC-DC converter circuit for controlling the logic value of the switch control signal. The method of claim 9,
When the digital code of the logic control signal is 100,
During the high voltage output period, the first, third, fourth, seventh and twelfth switch control signals remain active, and the remaining switch control signals remain inactive;
During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the low voltage output period, the first, fourth, eighth, ninth and tenth switch control signals remain active, and the remaining switch control signals remain inactive; And,
During the low voltage holding period, the switch control unit is further configured to maintain the second, fifth, seventh and eleventh switch control signals in an active state and the remaining switch control signals in an inactive state. DC-DC converter circuit for controlling the logic value of the switch control signal. The method of claim 9,
When the digital code of the logic control signal is 101,
During the high voltage output period, the first, third, fourth and sixth switch control signals remain active and the remaining switch control signals remain inactive;
During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the low voltage output period, the first, fourth, eighth, ninth and twelfth switch control signals remain active, and the remaining switch control signals remain inactive; And,
During the low voltage holding period, the switch control unit is further configured to maintain the second, fifth, seventh and eleventh switch control signals in an active state and the remaining switch control signals in an inactive state. DC-DC converter circuit for controlling the logic value of the switch control signal. The method of claim 9,
When the digital code of the logic control signal is 110,
During the high voltage output period, the first, third, fourth and sixth switch control signals remain active and the remaining switch control signals remain inactive;
During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the low voltage output period, the first, fourth, eighth, ninth and eleventh switch control signals remain active and the remaining switch control signals remain inactive; And,
During the low voltage holding period, the switch control unit is further configured to maintain the second, fifth, seventh and eleventh switch control signals in an active state and the remaining switch control signals in an inactive state. DC-DC converter circuit for controlling the logic value of the switch control signal. The method of claim 9,
When the digital code of the logic control signal is 111,
During the high voltage output period, the first, third, fourth and sixth switch control signals remain active and the remaining switch control signals remain inactive;
During the high voltage holding period, the second, fifth, seventh and eleventh switch control signals remain active, and the remaining switch control signals remain inactive;
During the low voltage output period, the first, fourth, eighth, ninth and tenth switch control signals remain active, and the remaining switch control signals remain inactive; And,
During the low voltage holding period, the switch control unit is further configured to maintain the second, fifth, seventh and eleventh switch control signals in an active state and the remaining switch control signals in an inactive state. DC-DC converter circuit for controlling the logic value of the switch control signal. The method of claim 1,
The first to third switches and the sixth to ninth switches each comprise a high voltage transistor; And,
The fourth to fifth switches and the tenth to twelfth switches each include a medium voltage transistor;
And the medium voltage transistor occupies a smaller area than the high voltage transistor. The method of claim 1,
The first to third, fifth, sixth and twelfth switches are P-type transistors, respectively; And,
And the fourth switch and the seventh to eleventh switches are N-type transistors, respectively. The method of claim 5, wherein
The switch control unit,
A high voltage output control signal having an enable state for a high voltage output period and having a disable state for a period other than the high voltage output period;
A high voltage maintenance control signal having an enable state during the high voltage maintenance period and having a disable state for the rest of the period except the high voltage maintenance period;
A low voltage output control signal having an enable state for the low voltage output period and having a disable state for the rest of the period except the low voltage output period;
A low voltage maintenance control signal having an enable state during the low voltage maintenance period and having a disable state for the rest of the period except the low voltage maintenance period; And,
Generating the first to twelfth switch control signals based on a logic control signal for controlling the logic states of the first to twelfth switch control signals during the high voltage output period, the high voltage sustain period, the low voltage output period, and the low voltage sustain period; DC-DC converter circuit characterized in that. The method of claim 5, wherein
The switch control unit,
An output control signal having an enable state for a continuous high voltage output period and a high voltage sustain period, and having a disable state for a subsequent low voltage output period and a low voltage sustain period;
A high / low output control signal having an enable state during the high voltage output period and the low voltage output period, and having a disable state for a period other than the high voltage output period and the low voltage output period;
A high / low maintenance control signal having an enable state during the high voltage holding period and the low voltage holding period, and having a disable state for the remaining periods except for the high voltage holding period and the low voltage holding period; And,
Generating the first to twelfth switch control signals based on a logic control signal for controlling the logic states of the first to twelfth switch control signals during the high voltage output period, the high voltage sustain period, the low voltage output period, and the low voltage sustain period; DC-DC converter circuit characterized in that. The method of claim 1,
An input voltage supplied to the input terminal has a voltage level twice that of a reference voltage;
The reference power supply provides a reference voltage having a voltage level of 2.8 to 3.3 [V];
The base power supply provides a base voltage of 0 [V]; And,
And the low potential power supply provides a low voltage having a voltage level of -3.3 to -2.8 [V] to the reference voltage.

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