KR101209914B1 - Semiconductor storage device memory disk unit with programmable host interface - Google Patents

Abstract

PURPOSE: A semiconductor storage device memory disk unit having a programmable host interface is provided to control synchronization of a data signal transmitted/received between a host and a memory disk, thereby supporting a low speed data processing speed of the host. CONSTITUTION: An adaptive host interface controller unit(308) is connected to a programmable host interface unit(202) connected to a host. A dynamic memory access controller(302) is connected to the adaptive host interface controller unit. An error check and corrector controller(304) is connected to the dynamic memory access controller. A memory controller(306) is connected to the error check and corrector controller. A memory array(602) is connected to the memory controller and includes a semiconductor storage device memory block set. [Reference numerals] (202) Programmable host interface; (302) DMA controller; (304) ECC controller; (306) Memory controller; (308) Adaptive host interface controller; (312) H/W host; (600A) Backup storage; (602) Memory; (700) Backup controller

Description

Semiconductor storage device memory disk unit with programmable host interface {SMICONDUCTOR STORAGE DEVICE MEMORY DISK UNIT WITH PROGRAMMABLE HOST INTERFACE}

Embodiments of the present invention relate to a semiconductor storage device (SSD) of the PCI-Express (PCI-e) type. In particular, embodiments of the present invention relate to an SSD memory disk unit having a programmable host interface unit.

Cross Reference of Related Application

This application is filed on April 13, 2010, entitled “SEMICONDUCTOR STORAGE DEVICE,” and is a continuing application of some of the commonly owned and co-pending US Application No. 12 / 758,937, all of which is hereby incorporated by reference. The application is also filed on Feb. 17, 2011, entitled “SEMICONDUCTOR STORAGE DEVICE-BASED CACHE STORAGE SYSTEM,” and relates to some embodiments of commonly owned and co-pending US application No. 13 / 029,476, all of which are hereby incorporated by reference. This is incorporated here by reference. This application is also referred to as "SEMICONDUCTOR STORAGE DEVICE MEMORY DISK UNIT WITH MULTIPLE HOST INTERFACE," and relates to some embodiments of the US application under the co-owned, co-pending agent control number SSD-0026, all of which is incorporated herein by reference. Merged by reference (the application number and application date will be provided later).

As the need for more computer storage increases, more efficient solutions are being sought. As is known, there are various hard disk solutions for storing / reading data in a mechanical manner as data storage media. Unfortunately, the data processing speed associated with hard disks is often slow. In addition, existing solutions still use interfaces that cannot keep up with the data processing speed of memory with high speed data input / output capability as an interface between the data storage medium and the host. Therefore, there is a problem in the existing area that the performance of the memory disk is not properly utilized.

The present invention supports the slow data processing speed for the host by adjusting the synchronization of data signals transmitted / received between the host and the memory disk in data communication between the host and the memory disk via the PCI-Express interface, while simultaneously supporting the memory disk. It provides a high speed data processing speed for a serial connected small computer system interface / serial advanced technology access (PCI-Express) type of storage device that supports the performance to enable maximum high speed data processing in the existing interface environment. It aims to provide.

In general, embodiments of the present invention provide a semiconductor storage device (SSD) memory disk unit having a programmable host interface (unit). In particular, in an exemplary embodiment the SSD-based memory disk unit comprises: a programmable host interface unit for connecting the SSD-based memory disk unit to at least one host; An adaptive host interface controller unit coupled to the programmable host interface unit; A DMA controller coupled to the adaptive host interface controller unit; An ECC controller coupled to the DMA controller; A memory controller coupled to the ECC controller; And a memory array connected to the memory controller, the memory array including at least one SSD memory block.

A first embodiment of the invention is a semiconductor storage device (SSD) memory disk unit having a programmable host interface unit, which is an adaptive host interface controller unit coupled to a programmable host interface unit configured to be connected to a host. ; A DMA controller coupled to the adaptive host interface controller unit; An ECC controller coupled to the DMA controller; A memory controller coupled to the ECC controller; And a memory array connected to the memory controller and including an SSD memory block set.

A second embodiment of the present invention is a semiconductor storage device (SSD) memory disk unit, comprising: a programmable host interface unit for connecting an SSD memory disk unit to at least one host; An adaptive host interface controller unit coupled to the programmable host interface unit; A DMA controller coupled to the adaptive host interface controller unit; An ECC controller coupled to the DMA controller; A memory controller coupled to the ECC controller; And a memory array connected to the memory controller and including a set of SSD memory blocks.

A third embodiment of the present invention provides a method of manufacturing a semiconductor storage device (SSD) memory, comprising: providing a programmable host interface unit for connecting an SSD memory disk unit to at least one host; Coupling an adaptive host interface controller unit to the programmable host interface unit; Coupling a DMA controller to the adaptive host interface controller unit; Coupling an ECC controller to the DMA controller; Coupling a memory controller to the ECC controller; And connecting a memory array including a set of SSD memory blocks to the memory controller.

According to an embodiment, a serially connected small computer system interface / serial-type advanced technology access (PCI-Express) type of storage device transmits / receives between a host and a memory disk in data communication between the host and the memory disk via a PCI-Express interface. By adjusting the synchronization of incoming data signals, it supports low data processing speeds for the host, and at the same time high data processing speeds for the memory disks, thereby enabling maximum high speed data processing in existing interface environments. do.

These and other features of the present invention will be more readily understood from the following detailed description of various embodiments of the invention in conjunction with the accompanying drawings.
1 is a diagram schematically illustrating a configuration of a PCI-e type (PCI-e) type storage device according to an embodiment of the present invention.
2 is a diagram schematically illustrating a configuration of the fast SSD of FIG. 1 according to an embodiment of the present invention.
3 is a diagram schematically illustrating a configuration of a controller in FIG. 1 having a programmable interface unit according to an embodiment of the present invention.
The drawings do not need to be scaled. The figures do not represent the specific parameters of the invention, but only represent schematically. The drawings illustrate only typical embodiments of the invention and are therefore not to be understood as limiting the scope of the invention. In the drawings, like reference numerals refer to like elements.

Exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the present disclosure may be embodied in many other forms and should not be construed as limited to the following example embodiments. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In the detailed description, detailed descriptions of well-known structures and techniques are omitted to avoid unnecessary ambiguity in the embodiments shown.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, the use of the terms "one", "one" and the like does not imply a limitation on the quantity, but rather means that at least one of the referenced items exists. As used herein, the terms “comprises” and / or “comprising”, or “consists of” and / or “consists of” refer to features, regions, integers, steps, actions, components, and / or described features. It is intended to specify the presence of a component and not to disable the presence or addition of one or more other features, regions, integers, steps, actions, components, components, and groups thereof. In addition, the term RAID used herein means a plurality of array independent disks (initially, a plurality of array low cost disks). In general, RAID technology is a method of storing the same data (and therefore unnecessarily) in different spaces of multiple hard disks. By placing data on multiple disks, input / output (I / O) operations can overlap in a balanced way to improve performance. Since multiple disks increase the Mean Time Between Failure (MTBF), unnecessarily stored data also increases fault tolerance. The term SSD refers to a semiconductor storage device. The term DDR means double data rate. The term HDD means a hard disk drive.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries are to be interpreted to have a meaning consistent with the meanings in the relevant description and context of the present disclosure, and are not to be interpreted as idealizing or as a whole in a formal sense unless expressly defined herein. Will be understood.

Hereinafter, a PCI-e type (PCI-e) type storage device according to an embodiment will be described in detail with reference to the accompanying drawings.

In general, embodiments of the present invention provide a semiconductor storage device (SSD) memory disk unit having a programmable host interface (unit). In particular, in an exemplary embodiment, the SSD-based memory disk unit comprises: a programmable host interface unit for connecting the SSD-based memory disk unit to at least one host; An adaptive host interface controller unit coupled to the programmable host interface unit; A DMA controller coupled to the adaptive host interface controller unit; An ECC controller coupled to the DMA controller; A memory controller coupled to the ECC controller; And a memory array connected to the memory controller and including at least one SSD memory block.

Serial-connected small computer system interface / serial-type advanced technology-connected (PCI-Express) -type storage devices synchronize the data signals transmitted / received between the host and the memory disk during data communication between the host and the memory disk via the PCI-Express interface. By adjusting the speed, it supports low data processing speeds for the host and at the same time high speed data processing speeds for the memory disk, thereby supporting the performance to enable maximum high speed data processing in the existing interface environment. Although PCI-Express technology will be utilized in conventional embodiments, it is understood in advance that other variations are possible. For example, the present invention may utilize Small Computer System Interface (SAS) / Serial Advanced Technology Advancement (SATA) technology provided with a SAS / SATA type storage device utilizing a SAS / SATA interface.

Referring to FIG. 1, there is shown a schematic illustration of a configuration of a PCI-Express type, RAID control semiconductor storage device (e.g., providing storage for a serially connected computer device) in accordance with one embodiment of the present invention. Shown. As shown, FIG. 1 includes a plurality of memory disks having a plurality of volatile semiconductor memories (herein referred to as high speed SSD memory disk units 100); A RAID controller 800 coupled to the SSD memory disk unit 100; An interface unit 200 (eg, PCI-Express host) that interfaces between the memory disk unit and the host; Controller unit 300; An auxiliary power source unit 400 that is charged to maintain predetermined power using power transmitted from the host through the PCI-Express host interface unit; When the power transmitted from the host through the PCI-Express host interface unit is interrupted or an error occurs in the power transmitted from the host, the controller unit 300 and the SSD memory disk unit 100 from the host through the PCI-Express host interface unit A power source control unit 500 for supplying power transmitted to the backup storage unit, the backup control unit, receiving power from the auxiliary power source unit, and supplying power to the SSD memory disk unit through the controller unit; A backup storage unit 600A-B for storing data of the SSD memory disk unit; And a backup control unit 700 for backing up data stored in the SSD memory disk unit of the backup storage unit in response to an instruction from the host or when an error occurs in power transmitted from the host. And a multi-array independent disk (RAID) controller 800 coupled to the SSD memory disk unit 100, the controller 300, and the internal backup controller 700, wherein the SSD memory disk unit 100 is a SSD memory disk. RAID control PCI-Express type storage device 110 according to an embodiment of the present invention, which is comprised of a unit, an SSD, and / or an SSD memory disk unit.

The SSD memory disk unit 100 is composed of a plurality of memory disks including a plurality of volatile semiconductor memories (eg, DDR, DDR2, DDR3, SDRAM, etc.) for high speed data input / output, Input and output data according to the control. The SSD memory disk unit 100 may have a configuration in which memory disks are arranged in parallel.

The PCI-Express host interface unit 200 interfaces between the host and the SSD memory disk unit 100. The host may be a computer system or the like that includes a PCI-express interface and a power source supply.

The control unit 300 adjusts the synchronization of data signals transmitted / received between the PCI-express host interface unit 200 and the SSD memory disk unit 100 to control the PCI-express host interface unit 200 and the SSD memory disk unit. Control data transmission / reception speed between 100.

As shown, the PCI-e type RAID controller 800 may be directly coupled to any number of SSD memory disk units 100. In particular, this allows for optimized control of the SSD memory disk unit 100. In particular, the use of the RAID controller 800,

1. Supports current backup / recovery operation.

2. Provide additional and improved backup capabilities by doing the following:

a) the internal backup controller 700 determines the backup (the user's request order or status monitor detects a power supply problem);

b) the internal backup controller 700 requests data backup to the SSD memory disk unit;

c) the internal backup controller 700 requests the internal backup device to immediately back up the data;

d) the internal backup controller 700 monitors the backup status for the SSD memory disk unit and the internal backup controller;

e) the internal backup controller 700 reports the status and end-op of the internal backup controller;

3. Provide additional and improved recovery capabilities by doing the following:

a) the internal backup controller 700 determines the recovery (the user's request order or status monitor detects a power supply problem);

b) the internal backup controller 700 requests data recovery to the SSD memory disk unit;

c) the internal backup controller 700 requests the internal backup device to immediately restore data;

d) the internal backup controller 700 monitors the recovery status for the SSD memory disk unit and the internal backup controller;

e) The internal backup controller 700 reports the status and end-op of the internal backup controller.

Referring to FIG. 2, a diagram schematically illustrating a configuration of the high speed SSD 100 is shown. As shown, SSD memory disk unit 100 includes a programmable host interface unit 202 coupled to a host 312 (eg, a hardware host); An adaptive host interface controller 308 coupled to (and controlling) the programmable host interface unit 308; Direct memory access (DMA) controller 302; An ECC controller 304; And a memory controller 306 for controlling one or more blocks 604 of the memory 602 used for fast storage. In addition, as shown, the backup controller 700 may be connected to the DMA controller 302, and the backup storage unit 600A may be connected to the backup controller 700.

In general, the design shown in FIG. 2 reduces board layout space by using one interface, thus reducing the cost of components. Still, both interface switching and automatic detection enable automatic control. Hardware host connection 312 enables proper interface connection based on an external host interface. Adaptive host interface controller 310 enables host control based on analysis of hardware host connection 312 signals. Programmable host interface 308 allows the host interface to be changed.

In general, DMA is a feature of modern computers and microprocessors that allow certain hardware subsystems within a computer to access system memory for independent reading and / or writing of a central processing unit. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards, and sound cards. DMA is also used for intra-chip data transfer within multi-core processors, particularly multiprocessor system on chips, where its processing elements include local memory (primarily referred to as scratchpad memory), and DMA between local memory and main memory Used for data transfer. A computer with a DMA channel can transfer data to / from a device with much less CPU overhead than a computer without a DMA channel. Similarly, processing elements within a multi-core processor can transfer data to / from local memory and perform computations and data transfers simultaneously without occupying processor time.

Without DMA, using Program Input / Output (PIO) mode for communication with peripherals, or instruction load / store in the case of a multi-core chip, the CPU is typically fully occupied for the entire time of a read or write operation, As a result, no other work can be done. If DMA is included, the CPU initiates the transfer, performs other operations while the transfer is in progress, and receives an interrupt from the DMA controller once the operation is complete. This is especially useful for real-time computing applications where no interruptions in concurrent operations are critical.

Referring to FIG. 3, the controller unit 300 of FIG. 1 may include a memory control module 310 that controls data input / output of the SSD memory disk unit 100; According to the instruction received from the host through the PCI-Express host interface unit 200, the data is read from the SSD memory disk unit 100 and provided to the host, or the memory control module 310 is controlled to control the SSD. A direct memory access (DMA) control module 320 for storing data in the memory disk unit 100; A buffer 330 for buffering data according to the control of the DMA control module 320; Synchronization of the data signal when receiving a data signal corresponding to the data read from the SSD memory disk unit 100 through the DMA control module 320 and the memory control unit 310 by the control of the DMA control module 320 By adjusting the control unit to transmit the synchronized data signal to the PCI-express host interface unit 200 at a communication speed corresponding to the PCI-express communication protocol, and transmits the data signal from the host through the PCI-express host interface unit 200. When receiving, by adjusting the synchronization of the data signal, the DMA control module (at a transmission rate corresponding to the communication protocol (eg, PCI, PCI-x or PCI-e, etc.) used by the SSD memory disk unit 100 ( 320 and through the memory control module 310, the synchronization to transmit the synchronized data signal to the SSD memory disk unit 100 Control module 340; It consists of a high speed interface module 350 for processing data transmitted / received at high speed between the synchronization control module 340 and the DMA control module 320. Here, the high speed interface module 350 is composed of a buffer having a double buffer structure and a buffer having a circular queue structure, and the synchronization control module 340 and the DMA at high speed without loss by buffering the data and adjusting the data clock. Processes data transmitted / received between the control module 320.

Referring back to FIG. 1, the auxiliary power source unit 400 is configured of a rechargeable battery, and the like, and maintains a predetermined power using power normally charged and transmitted from the host through the PCI-express host interface unit 200. The charged power may be supplied to the power source control unit 500 according to the control of the power source control unit 500.

The power source control unit 500 transmits power from the host to the controller unit 300, the SSD memory disk unit 100, the backup storage unit 600A-B, and the backup control unit 700 via the PCI-Express host interface. To supply.

In addition, when the power transmitted from the host through the PCI-Express host interface unit 200 is cut off, when an error occurs in the power source of the host, or the power transmitted from the host is out of the threshold, the power source control unit 500 ) Receives power from the auxiliary power source unit 400 and supplies power to the SSD memory disk unit 100 through the controller unit 300.

The backup storage unit 600A-B is configured of a low speed nonvolatile storage device such as a hard disk and stores data of the SSD memory disk unit 100.

The backup control unit 700 backs up the data stored in the SSD memory disk unit 100 of the backup storage unit 600A-B by controlling the data input / output of the backup storage unit 600A-B and responds to instructions from the host. Therefore, when an error occurs in the power source of the host as the power transmitted from the host is out of the threshold value, the data stored in the SSD memory disk unit 100 of the backup storage unit 600A-B is backed up.

Serial connection Small computer system interface / serial advanced technology access (PCI-Express) type of storage device synchronizes data signals transmitted / received between the host and the memory disk during data communication between the host and the memory disk via the PCI-Express interface. By adjusting the speed, it supports low data processing speeds for the host and at the same time high speed data processing speeds for the memory disk, thereby supporting the performance to enable maximum high speed data processing in the existing interface environment.

Illustrative embodiments have been shown and described, and those skilled in the art will understand that various modifications in form and detail are possible without departing from the spirit and scope of the disclosure as defined by the appended claims. In addition, various modifications may be made and specific circumstances or materials may be applied to the teachings of the present disclosure without departing from the essential scope. Accordingly, the present disclosure is not limited to the specific exemplary embodiments disclosed as the best mode contemplated for carrying out the present disclosure, and the disclosure includes all embodiments falling within the scope of the appended claims.

The foregoing description of various embodiments of the invention has been presented for purposes of explanation. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible. Such modifications and variations apparent to those skilled in the art are within the scope of the invention as defined by the appended claims.

100: SSD memory disk unit
200: interface unit
300: controller
400: auxiliary power source unit
500: power source control unit
600A-B: Backup Storage Unit
700: backup control unit
800: RAID controller

Claims (20)

A semiconductor storage device (SSD) memory disk unit having a programmable host interface unit,
An adaptive host interface controller unit coupled to the programmable host interface unit configured to be coupled to the host;
A DMA controller coupled to the adaptive host interface controller unit;
An ECC controller coupled to the DMA controller;
A memory controller coupled to the ECC controller;
A memory array coupled to the memory controller and including a set of SSD memory blocks;
A redundant array of independent disks (RAID) controller connected to the SSD memory disk unit;
A controller unit connected to the RAID controller; And
A semiconductor storage device (SSD) memory disk unit having a programmable host interface unit comprising a system interface unit coupled to the controller unit. delete The method of claim 1,
The controller unit,
A memory control module for controlling data input / output of the SSD memory disk unit;
A DMA control module for controlling the memory control module to read data from the SSD memory disk unit to store data in the SSD memory disk unit or to provide data to the host according to an instruction received from the host through the host interface unit;
A buffer for buffering data according to the control of the DMA control module;
When receiving the data signal corresponding to the data read from the SSD memory disk unit through the DMA control module and the memory control unit by the control of the DMA control module, the synchronization of the data signal is adjusted to correspond to the PCI-Express communication protocol. Enables the transmission of synchronized data signals to the PCI-Express host interface unit at speed, and adjusts the synchronization of the data signals for use by the SSD memory disk unit when receiving data signals from the host through the PCI-Express host interface unit. A synchronization control module for transmitting the synchronized data signal to the SSD memory disk unit through the DMA control module and the memory control module at a transmission rate corresponding to the communication protocol; And
Synchronization control module by processing data transmitted / received at high speed between synchronization control module and DMA control module, including buffer with double buffer structure and circular queue structure, using buffer and adjusting data clock And a high speed interface module for processing data transmitted / received between the synchronous control module and the DMA control at high speed by buffering data communicated between the DMA control module and the DMA control module. Device (SSD) memory disk unit. The method of claim 1,
A backup storage unit set connected to said controller unit for storing data of an SSD memory disk unit;
According to at least one of the following, that is, when an error occurs in the instruction from at least one host or the power transmitted from the at least one host, backup stored in the SSD memory disk unit, And a backup control unit coupled to the semiconductor storage device (SSD) memory disk unit having a programmable host interface unit. The method of claim 4, wherein
An auxiliary power source unit coupled to the backup control unit and charged to maintain a preset power using power transmitted from at least one host through a system interface; And
Connected to the auxiliary power source unit and supplying power transmitted from at least one host through a system interface to a controller unit, a memory disk unit, a backup storage unit, and a backup control unit, the power being transmitted from the host through the host interface unit. And a power source control unit that receives power from the auxiliary power source unit through the controller unit and supplies power to the memory disk unit when the power is cut off or an error occurs in the power transmitted from the host. A semiconductor storage device (SSD) memory disk unit having a. The method of claim 1,
And a status monitor coupled to said SSD memory disk unit. The method of claim 1,
And wherein the set of SSD memory blocks is volatile and the programmable host interface unit is a PCI-Express host interface unit. A semiconductor storage device (SSD) memory disk unit,
A programmable host interface unit for connecting the SSD memory disk unit to at least one host;
An adaptive host interface controller unit coupled to the programmable host interface unit;
A DMA controller coupled to the adaptive host interface controller unit;
An ECC controller coupled to the DMA controller;
A memory controller coupled to the ECC controller;
A set of SSD memory blocks connected to the memory controller;
A redundant array of independent disks (RAID) controller connected to the SSD memory disk unit;
A controller unit connected to the RAID controller; And
A semiconductor storage device (SSD) memory disk unit comprising a system interface unit coupled to the controller unit. delete The method of claim 8,
The controller unit,
A memory control module for controlling data input / output of the SSD memory disk unit;
A DMA control module for controlling the memory control module to read data from the SSD memory disk unit to store data in the SSD memory disk unit or to provide data to the host according to an instruction received from the host through the host interface unit;
A buffer for buffering data according to the control of the DMA control module;
When receiving the data signal corresponding to the data read from the SSD memory disk unit through the DMA control module and the memory control unit by the control of the DMA control module, the synchronization of the data signal is adjusted to correspond to the PCI-Express communication protocol. Enables the transmission of synchronized data signals to the PCI-Express host interface unit at speed, and adjusts the synchronization of the data signals for use by the SSD memory disk unit when receiving data signals from the host through the PCI-Express host interface unit. A synchronization control module for transmitting the synchronized data signal to the SSD memory disk unit through the DMA control module and the memory control module at a transmission rate corresponding to the communication protocol; And
Synchronization control module by processing data transmitted / received at high speed between synchronization control module and DMA control module, including buffer with double buffer structure and circular queue structure, using buffer and adjusting data clock And a high speed interface module for processing data transmitted / received between the synchronous control module and the DMA control at high speed without buffering data communicated between the DMA control module and the semiconductor storage device (SSD) memory disk unit. . The method of claim 8,
A backup storage unit set connected to said controller unit for storing data of an SSD memory disk unit; And
According to at least one of the following, that is, when an error occurs in the instruction from at least one host or power transmitted from at least one host, the data stored in the SSD memory disk unit is backed up, and the SSD memory disk And a backup control unit coupled to the unit. The method of claim 11,
An auxiliary power source unit coupled to the backup control unit and charged to maintain a preset power using power transmitted from at least one host through a system interface; And
Connected to the auxiliary power source unit and supplying power transmitted from at least one host through a system interface to a controller unit, a memory disk unit, a backup storage unit, and a backup control unit, the power being transmitted from the host through the host interface unit. The semiconductor storage device further comprising: a power source control unit receiving power from the auxiliary power source unit through the controller unit to supply power to the memory disk unit when the power is cut off or an error occurs in the power transmitted from the host. ) Memory disk unit. The method of claim 8,
And a status monitor coupled to the SSD memory disk unit. The method of claim 8,
The set of SSD memory blocks is volatile and the programmable host interface unit is a PCI-Express host interface unit. delete delete delete delete delete delete

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