KR101204923B1 - Nonvolatile memory device - Google Patents

Abstract

The present invention provides a nonvolatile memory device capable of reducing the time required for precharging. The nonvolatile memory device of the present invention is connected to a bit line, and after precharging the sensing output node to an ambient voltage, electrically connecting the sensing output node and the sensing amplification node in response to the clamping control signal delayed by a predetermined time. And a write / reader comprising a precharging unit for precharging the sense output node to a sense voltage, and a current driver for providing a bias current to the sense amplification node to develop a voltage of the sense amplification node. do.

Description

Nonvolatile Memory Device

One embodiment of the present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device that reads data through current sensing.

Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices. The nonvolatile memory device may be a memory device that retains data even when power is cut off, and may include a flash memory device.

Recently, in order to increase the integration of semiconductor memory devices, an integrated circuit is designed in three dimensions or a research on a nonvolatile memory device using a resistance material has been made. The nonvolatile memory device using a resistor may include a phase change random access memory (PCRAM), a ferroelectric memory (FeRAM), and a magnetic RAM (MRAM).

Dynamic memory devices (DRAMs) or flash memory devices use charge to store data, while nonvolatile memory devices that use resistors are in the state of phase change materials such as chalcogenide alloys. Data is stored using change (PCRAM), resistance change (RRAM) of the variable resistor, resistance change (MRAM) of the magnetic tunnel junction (MTJ) thin film according to the magnetization state of the ferromagnetic material, and the like.

An object of the present invention is to provide a nonvolatile memory device capable of reducing the time required to read data written to nonvolatile memory cells.

Another object of the present invention is to provide a nonvolatile memory device that can be miniaturized by minimizing a read circuit for reading data written to nonvolatile memory cells.

A nonvolatile memory device according to an embodiment of the present invention is connected to a bit line, and after precharging a sensing output node to an ambient voltage, sense sensing amplification with the sensing output node in response to a clamping control signal delayed by a predetermined time. A precharging unit that electrically connects the nodes to precharge the sense output node to a sensing voltage, and provides a bias current to the sense amplification node to develop a voltage of the sense amplification node. And a write / reader including a driver.

In the nonvolatile memory device according to example embodiments, an operating speed may be improved by improving a current driving capability of a precharge circuit.

In addition, the nonvolatile memory device according to the embodiments of the present invention can easily implement a precharge circuit required when reading data, thereby improving portability.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a diagram illustrating a write driver and sense amplifier according to an embodiment of the present invention.
2 and 3 are diagrams illustrating a write / driver according to an embodiment of the present invention.
4 is a timing diagram illustrating an operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.
5 is a block diagram illustrating a nonvolatile memory device having a write / reader according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a write driver and sense amplifier according to an embodiment of the present invention.

Referring to FIG. 1, the write / reader 10 may be electrically connected to a plurality of memory cells through a bit line BL. Each memory cell may include a phase change element VR1 and a diode D1 connected between the bit line BL and the word line WL. In FIG. 1, only one memory cell is illustrated for convenience of description, but may include a plurality of memory cells, and a configuration of a nonvolatile memory device including the plurality of memory cells will be described later with reference to FIG. 5.

The write / reader 10 may include a precharging unit 100 and a current driver 200 that provide a sense current ILD to a memory cell.

The precharging unit 100 precharges the sensing output node SIO connected to the bit line BL with a sensing voltage. The sensing voltage is a voltage level at which the bit line BL is charged to a predetermined voltage level before the sensing operation to determine data written in the memory cell. In some embodiments, the sensing voltage may have a voltage level higher than a driving voltage, such as the peripheral voltage used by the peripheral circuits. Although the sensing voltage has a voltage level higher than the peripheral voltage, the data read voltage margin of the memory cells may be secured, but it may take a long time to precharge the bit line BL from the peripheral voltage to the sensing voltage.

The time for reading data stored in the memory cell includes a time for precharging the bit line and a time for developing the voltage of the sense output node by applying a sense current to the bit line to output data. Therefore, when the time for precharging the bit line BL is shortened, the read time required for the plurality of memory cells can be shortened. As the read time of each memory cell is shortened, an operating speed of the entire nonvolatile memory device may be improved.

The write / reader 10 according to an embodiment of the present invention first precharges the sensing output node SIO to an ambient voltage to sense data of a memory cell connected to the bit line BL, and then to a sensing voltage. Secondary precharging may prevent excessive driving that may occur when the bit line BL is precharged to a suddenly high voltage level.

The current driver 200 is electrically connected to the precharging unit 100 by the sense amplification node SAN. The current driver 200 may generate a bias current and provide the bias current to the precharging unit 100. The bias current may be provided to the memory cell connected to the bit line BL through the precharging unit 100, and the voltage value of the sensing amplification node SAN may be different according to the resistance value of the phase change element VR1. have. The voltage of the sense amplification node SAN may be provided as a sense amplification voltage SAI.

2 illustrates a write / driver according to an embodiment of the present invention.

Referring to FIG. 2, the write / driver 10a may include a precharging unit 100 and a current driver 200. Since the same reference numerals as those of FIG. 1 denote substantially the same components, detailed descriptions thereof will be omitted.

The precharging unit 100 may include a first precharge unit 110, a clamping unit 120, and a second precharge unit 130.

The first precharge unit 110 may include a first NMOS transistor MN1 and a first precharge control unit 115.

The first precharge control unit 115 may generate a first precharge control signal CLMPRE and provide the first precharge control signal CLMPRE to the gate of the first NMOS transistor MN1. The first NMOS transistor MN1 includes a gate to which the first precharge control signal CLMPRE is applied, a first terminal to which the peripheral voltage VPERI is applied, and a second terminal to the sensing output node SIO. The peripheral voltage VPERI may be provided to the sensing output node SIO in response to the first precharge control signal CLMPRE.

The first precharge control unit 115 may operate in response to the first precharge control signal CLMPRE regardless of the clamping control signal CLMBL. For example, the precharging circuit may further include a separate PMOS transistor that operates in response to the clamping control signal CLMBL when the primary precharging is performed, and thus the sensing voltage VPPSA by the secondary precharging. The circuit can be prevented from being damaged by being provided to the first NMOS transistor MN1 or the like. However, when a separate PMOS transistor is included, the current driving capability of the transistor required for primary precharging is lowered and space for the PMOS transistor is required, thereby increasing the size of the precharging circuit.

Therefore, the write / reader 10a according to the exemplary embodiment of the present invention includes the single first NMOS transistor MN1 to configure the first precharge unit 110, thereby reducing the overall size of the precharge circuit. In addition, the current driving capability for performing the primary precharging can be improved, so that the time required for the primary precharging can be shortened.

The clamping unit 120 may include a second NMOS transistor MN2 and a clamping controller 125. The clamping controller 125 may generate the clamping control signal CLMBL and provide the clamping control signal CLMBL to the second NMOS transistor MN2. The second NMOS transistor MN2 includes a gate to which the clamping control signal CLMBL is applied, a first terminal connected to the sensing output node SIO, and a second terminal connected to the sensing amplification node SAN.

The second NMOS transistor MN2 electrically connects the sensing output node SIO and the sensing amplification node SAN in response to the clamping control signal CLMBL. In some embodiments, the clamping control signal CLMBL is provided from the second precharge unit 130 to the sensing output node SIO precharged by the first precharging controller 115 to the peripheral voltage VPERI. The sensing output node SIO may be boosted by providing a sensing voltage VPPSA.

However, the clamping unit 120 may prevent the sensing voltage VPPSA from flowing into the first precharge unit 110 while the first precharge is performed in the first precharge unit 110. CLMBL) may be provided by delaying a predetermined time. The PMOS transistor that was required to prevent the sensing voltage VPPSA from flowing into the first precharge unit 110 may not be included in the write / driver 10a because the clamping control signal CLMBL is provided with a delay. .

The second precharge unit 130 may include a first PMOS transistor MP1 and a second precharge control unit 135. The second precharge control unit 135 may generate a second precharge control signal SAIPRE and provide it to the first PMOS transistor MP1. The first PMOS transistor MP1 includes a gate to which the second precharge control signal SAIPRE is applied, a first terminal to which the sensing voltage VPPSA is applied, and a second terminal connected to the sensing amplification node SAN. The sensing voltage VPPSA is provided to the sensing amplification node SAN in response to the second precharge control signal SAIPRE.

The current driver 200 may include a current driving controller 210 and a second PMOS transistor MP2. The current driving controller 210 may generate a current driving control signal SAILD and provide it to the second PMOS transistor MP2. The second PMOS transistor MP2 may include a gate to which the current driving control signal SAILD is applied, a first terminal to which the sensing voltage VPPSA is applied, and a second terminal connected to the sensing amplification node SAN. The second PMOS transistor MP2 may provide a bias current to the sense amplification node SAN in response to the current driving control signal SAILD. The bias current may have a preset current value and may correspond to the sense current according to an embodiment.

When a bias current having a preset current value from the current driver 200 is provided to the sensing output node SIO, the bias current is connected to the bit line BL through the sensing output node SIO precharged with the sensing voltage VPPSA. Different voltage values may be generated according to the resistance value of the memory cell. Therefore, after the first and second precharging is completed, the voltage of the sense amplification node SAN generated based on the bias current may correspond to the sense amplification voltage SAI.

The sense amplification voltage SAI may have a different voltage level depending on the resistance value of the memory cell.

3 illustrates a write / driver according to an embodiment of the present invention.

Compared with the write / driver 10a of FIG. 2, the write / driver 10b of FIG. 3 may further include a sense amplifier 300. In FIG. 3, the same reference numerals as FIG. 2 denote substantially the same components, and thus a detailed description thereof will be omitted.

The clamping controller 125 may include a clamping timing controller 121 and a delayer 123. The clamping timing controller 121 generates the clamping timing signal CLMTM and provides it to the delayer 123. The delayer 123 delays the clamping timing signal CLMTM by a predetermined time to clamp the control signal CLMBL. To provide. For example, the clamping timing signal CLMTM may generally correspond to the clamping control signal of the clamping controller 125.

According to an embodiment, the clamping timing signal CLMTM may be activated at the time when primary precharging is completed. For example, the clamping unit 120 operates to turn on the second NMOS transistor MN2 at the time when the primary precharging is completed, so that the sensing amplification node SAN is passed through the second NMOS transistor MN2. The sensing voltage VPPSA is provided to the sensing output node SIO, and the sensing voltage VPPSA may flow into the first NMOS transistor MN1 when the first precharge control signal CLMPRE is deactivated. have. The write / reader 10b according to an embodiment of the present invention provides a clamping control signal CLMBL that is activated by being delayed by a predetermined time to prevent the sensing voltage VPPSA from flowing in.

Referring to FIG. 2, the sense amplifier 300 compares a sense amplification voltage SAI of a sense amplification node SAN with a reference voltage VREF to provide a sense output signal SOUT. The sense output signal SOUT may have a voltage level corresponding to the logic state 'high' or 'low', for example, when the sense amplification voltage SAI is greater than the reference voltage VREF, the sense amplifier 300. ) May provide a sense output signal SOUT corresponding to a logic state 'high'.

Although not shown, the write / drivers 10a and 10b of FIGS. 2 and 3 according to an embodiment of the present invention may further include a discharge unit. In order to read specific data into the memory cell and read the data, the specific voltage value is precharged to the sensing output node SIO connected to the bit line BL, and the predetermined bias current is provided through the precharged node to sense the data. A constant sense amplification voltage SAI may be provided through the amplification node SAN. Therefore, the sense amplification node SAN and the sense output node SIO in which the read operation is completed may have a value dependent on data written in a predetermined memory cell connected to the bit line BL. Therefore, when an operation of reading data written in another memory cell connected to the same bit line BL is performed, the voltages of the sense amplification node SAN and the sensing output node SIO are converted to the ground voltage GND. After the discharge to the same voltage value, the read operation should be performed. Therefore, the nonvolatile memory device according to an embodiment of the present invention may further include a discharge unit.

In addition, the write / driver 10, 10a, 10b according to an embodiment of the present invention may further include a write current generator for writing data to the memory cells through the bit line BL. The write current may have a different value based on the data to be written to the memory cells.

4 is a timing diagram illustrating an operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, WL is a voltage applied to a word line, SAIPRE is a second precharge control signal, CLMPRE is a first precharge control signal, CLMBL is a clamping control signal, SIO is a voltage level of a sensing output node, and SAI. Represents the sense amplification voltage. Each can represent a voltage level.

At a time t1, a voltage corresponding to the logic state 'low' is applied to the word line WL to activate the word line. Among the memory cells connected to the activated word line, data of the memory cell connected to the bit line BL may be read. When the first precharge control signal CLMPRE is activated, the first NMOS transistor MN1 included in the first precharge unit 110 of FIGS. 2 and 3 is turned on to sense the output node. (SIO) gradually rises to the ambient voltage VPERI. Since the second precharge control signal SAIPRE is activated to the logic state 'low', the sense amplification voltage SAI maintains the sensing voltage VPPSA.

At time t2, the first precharge control signal CLMPRE is deactivated to turn off the first NMOS transistor MN1 to complete the first precharging. The time point at which the first precharging is completed may be a time point at which the sensing output node SIO has a voltage level substantially the same as the peripheral voltage VPERI. The nonvolatile memory device 10 according to an embodiment of the present invention may improve the current supply capability by providing a peripheral voltage VPERI through a single transistor to precharge the sensing output node SIO, thereby providing a sensing output node. It is possible to shorten the time for the SIO to reach the peripheral voltage VPERI. That is, the execution time of the first precharging can be reduced.

The clamping control signal CLMBL is activated after a predetermined time delay from the time t2 at which the first precharging is completed. When the clamping control signal CLMBL is activated at a time t2 that is substantially the same as when the first precharging is completed, the sensing voltage VPPSA provided through the second NMOS transistor MN2 is transferred to the first NMOS transistor MN1. Can be introduced. The first NMOS transistor MN1, which operates at an ambient voltage VPERI smaller than the sensing voltage VPPSA, may be damaged by the sensing voltage VPPSA. Accordingly, damage to the first precharge unit 110 may be prevented by delaying the clamping control signal CLMBL by a predetermined time.

The clamping control signal CLMBL is activated at a time t3 after a predetermined delay time from the time t2. The sensing output node SIO and the sensing amplification node SAN are electrically connected by the clamping control signal CLMBL, so that a sensing voltage VPPSA equal to the voltage level of the sensing amplification voltage SAI is detected. Is provided).

At time t4, as the second precharge control signal SAIPRE transitions to the logic state 'high' and is deactivated, the second precharge is completed. As the current driving control signal SAILD is activated and the sense current is provided to the bit line BL, the sense amplification voltage according to the resistance value of the memory cell connected to the bit line BL and the deactivated word line WL. The value of (SAI) is developed differently.

When the sense amplification voltage SAI is greater than the reference voltage VREF, the memory cell may be determined to be in a reset state, and when the sense amplification voltage SAI is less than the reference voltage VREF, the memory cell Can be determined to be in the Set state.

Therefore, the nonvolatile memory device according to the embodiment of the present invention can reduce the time required for the first precharging, thereby reducing the overall read time.

5 is a block diagram illustrating a nonvolatile memory device having a write / reader according to an embodiment of the present invention.

Referring to FIG. 5, the nonvolatile memory device 1 may include a row decoder 20, a memory cell array 30, a global column decoder 40, and a write / reader 10.

The row decoder 20 may receive the row address RADDR to provide a row driving voltage to the word lines WL0, WL1,..., WLn-1. According to an embodiment, the row decoder 20 may further include a voltage generator, and based on the row address RADDR, the row decoder 20 may select a voltage suitable for the plurality of word lines WL0, WL1,..., WLn-1. Can provide.

The memory cell array 30 includes a plurality of memory cells. Each of the memory cells may be a resistive memory cell as described above, and may write data based on a driving current provided from the write / reader 10 or write / read different sensing amplification voltages according to the written data. 10) can be provided.

According to an embodiment, the memory cell array 30 may further include a local column decoder. When the memory cell array 30 includes a local column decoder, a local column address may be provided to the memory cell array, and may be a combination of the global column address GCADDR and the local column address provided through the global word line GBL. One bit line BL may be selected.

The global column decoder 40 may receive the column address CADDR and establish a connection relationship between the plurality of global word lines GBL0, GBL1,..., GBLm-1 of the memory cell array 30.

The write / reader 10 may include the configuration of the write / readers 10a and 10b of FIGS. 2 and 3, and according to embodiments, respectively, on the bit lines BL of the memory cell array 30. Or a global bit line (GBL).

During the read operation of the nonvolatile memory device 1, the write / reader 10 may precharge the bit line BL or the global bit line GBL to the sensing voltage VPPSA, and during the write operation, Drive current can be provided.

The write / reader 10 according to an embodiment of the present invention may simply implement a first precharge unit for boosting the sensing output node SIO of the bit line BL to the peripheral voltage VPERI. The time required for primary precharging can be shortened.

Therefore, not only the size of the nonvolatile memory device 1 including the plurality of write / readers 10 can be reduced, but also the time required for the read operation is reduced to increase the operation speed of the nonvolatile memory device 1. Can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

Claims (9)

The sensing output node is connected to a bit line, and the sensing output node is electrically sensed by electrically connecting the sensing output node and the sensing amplification node in response to a clamping control signal delayed by a predetermined time after precharging the sensing output node to an ambient voltage. Precharging unit for precharging with; And
And a write / reader including a current driver for providing a bias current to the sense amplification node to develop a voltage of the sense amplification node. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
The precharging unit,
A first precharge unit connected to the bit line to precharge the sensing output node to the peripheral voltage in response to a first precharge control signal;
A clamping unit electrically connecting the sensing output node and the sensing amplifying node in response to the clamping control signal; And
And a second precharge unit configured to precharge the sense amplifier node to the sensing voltage in response to a second precharge control signal. Claim 3 has been abandoned due to the setting registration fee. The method according to claim 2,
The first precharge unit,
A first transistor configured to provide the peripheral voltage to the sensing output node in response to the first precharge control signal; And
And a first precharge controller configured to generate the first precharge control signal. Claim 4 has been abandoned due to the setting registration fee. The method according to claim 2,
The clamping portion,
A delay unit configured to delay the clamping timing signal by a predetermined time to provide the clamping control signal; And
And a second transistor configured to connect the sensing output node and the sensing amplifier node to boost the voltage level of the sensing output node to the sensing voltage in response to the clamping control signal. Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 2,
And the first precharge unit operates independently from the bit line clamping signal. delete Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 1,
And a sense amplifier configured to provide a sensed output signal by comparing a sensed voltage corresponding to a voltage of the sensed amplified node with a reference voltage. Claim 8 was abandoned when the registration fee was paid. The method according to claim 1,
And a resistive memory cell coupled between the bit line and the word line crossing the bit line. A memory cell array including a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines, respectively; And
The sensing output node and the sensing amplification node are electrically connected to each other in response to a clamping control signal which is connected to the plurality of bit lines, respectively, and precharges a sensing output node to an ambient voltage. And a plurality of write / readers for precharging an output node to a sensing voltage to develop a voltage of the sense amplification node.

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