KR101186574B1 - method of forming channel layer in electric device and method of manufacturing electric device using the same - Google Patents

Abstract

Disclosed is a method of forming a channel layer of an electric device, according to an embodiment. First, a conductive substrate having an insulating layer thereon is provided. Electroplating is performed in an electrolyte solution using the conductive substrate and the metal to be plated as electrodes. In this case, a metal channel layer is formed on the insulating layer by combining electrons provided by the tunneling current passing through the insulating layer from the conductive substrate with ions of the metal in the electrolyte solution.

Description

Method of forming channel layer in electric device and method of manufacturing electric device using same {method of forming channel layer in electric device and method of manufacturing electric device using the same}

The present application relates generally to a method of manufacturing an electric device, and more particularly, to a channel layer forming method of an electric device and a method of manufacturing the electric device using the same.

Electrical device technology, as an example, semiconductor device technology has made significant progress to date. In particular, memory devices that require high integration, such as DRAM, have required active and passive devices with smaller feature sizes, and semiconductor devices and process technologies have responded to shrinking feature sizes.

However, when a channel layer having a length of 50 nm or less is implemented in a transistor device, a short channel effect occurs and thus the device implementation is difficult. Up to now, this is temporarily solved by increasing the doping concentration of the channel layer, but when the feature size is further reduced, there is a need for a fundamental solution. Some studies have proposed a Recess Channel Array Transistor (RCAT) device with a recessed channel region under the gate of a transistor to increase the effective gate length or lower the threshold voltage compared to the RCAT. Channel Array Transisor) device is proposed. Some other work suggests a vertical transistor in which the gate is completely wrapped around the channel between the vertically oriented source and drain. As described above, the short channel effect is overcome by changing the structure of the transistor, but the manufacturing process is complicated.

Recently, a transistor structure having a metal channel layer has been proposed as a method for overcoming the performance degradation of transistors due to such feature size reduction. By forming the channel layer of the transistor with a metal, it is possible to improve the mobility of charge in the channel layer and thus to reduce the leakage current caused by the short channel effect. As such, as the interest in the transistor structure including the metal channel layer increases, research on a method of manufacturing the metal channel layer transistor with reliability is also requested.

It is an object of the present invention to provide a method of forming a metal channel layer in an electrical device having a sufficiently small length, width and thickness.

Another technical problem to be solved by the present invention is to provide a method for manufacturing an electric device including a metal channel layer having a sufficiently small length, width and thickness.

Provided is a method of forming a channel layer of an electric device according to an aspect of the present application for achieving the above technical problem. In the method for forming a channel layer of the electric device, a conductive substrate having an insulating layer thereon is first provided. Electroplating is performed in an electrolyte solution using the conductive substrate and the metal to be plated as electrodes. In this case, a metal channel layer is formed on the insulating layer by combining electrons provided by the tunneling current passing through the insulating layer from the conductive substrate with ions of the metal in the electrolyte solution.

According to one embodiment, the metal may be gold, silver, platinum, aluminum, lead, hafnium, tantalum, titanium, copper, tin or palladium.

According to another embodiment, in the step of performing the electroplating, a voltage may be applied such that the metal has a positive polarity and the conductive substrate has a negative polarity in the electrolyte solution.

In another embodiment, in the electroplating, the electrolyte solution may include a surface active agent, and the surface active agent may allow the metal channel layer in atomic layer units to be formed on the insulating layer. .

Provided is a method of manufacturing an electrical device according to another aspect of the present application for achieving the above technical problem. In the method of manufacturing the electric element, an insulating layer is first formed on a conductive substrate. The source electrode layer and the drain electrode layer are formed on the insulating layer to be spaced apart from each other. The conductive substrate including the insulating layer, the source electrode layer, and the drain electrode layer is dipped in an electrolyte solution. Electroplating is performed using the conductive substrate and the metal to be plated as electrodes. In this case, a metal channel layer is formed between the source electrode layer and the drain electrode layer by combining electrons of the tunneling current passing through the insulating layer from the conductive substrate with ions of the metal in the electrolyte solution.

In some embodiments, the electroplating may include applying an electric voltage between the source electrode layer and the drain electrode layer and measuring a current flowing between the source electrode layer and the drain electrode layer to form the channel metal layer. It may be determined whether the plating process is completed.

According to another embodiment, the method of manufacturing the electric device may further include forming an upper gate dielectric layer on the channel metal layer and forming an upper gate electrode layer on the upper gate dielectric layer.

According to another embodiment, the electrolyte solution may include a surface active agent, and the surface active agent may allow the channel metal layer in atomic layer units to be formed on the insulating layer.

Provided is a method of manufacturing an electrical device according to another aspect of the present application for achieving the above technical problem. In the method of manufacturing the electric element, first, an insulating layer is formed on a conductive substrate. The source electrode layer and the drain electrode layer are formed on the insulating layer to be spaced apart from each other. A base metal layer is formed on the conductive substrate including the insulating layer, the source electrode layer, and the drain electrode layer. A photoresist is applied onto the conductive substrate and a photoresist pattern is formed to expose a portion of the base metal layer through a lithography process. The portion of the exposed base metal layer is removed to expose a portion of the insulating layer. Electroplating is performed using the conductive substrate and the metal to be plated as electrodes in an electrolyte solution. In this case, a metal channel layer is formed on the portion of the insulating layer by combining electrons of the tunneling current passing through the insulating layer from the conductive substrate and ions of the metal in the electrolyte solution.

According to one embodiment, the photoresist pattern may determine the length and width of the metal channel layer formed by the electroplating.

In another embodiment, in the process of removing the portion of the exposed base metal layer, an electrolyte solution may be first provided to the conductive substrate on which the photoresist pattern is formed. The electrolyte solution may be electrolyzed by applying a voltage to the electrolyte solution and the conductive substrate. In this case, the part of the exposed base metal layer may be etched by ionizing the metal of the exposed base metal layer into the electrolyte solution by the oxidation reaction of the electrolysis.

In another embodiment, in the electroplating, a voltage is applied between the source electrode layer and the drain electrode layer, and a current flowing between the source electrode layer and the drain electrode layer is measured to determine the metal channel layer. It may be determined whether the electroplating process to be formed is completed.

According to another embodiment, the method of manufacturing the electric device may further include forming an upper gate dielectric layer on the metal channel layer and forming an upper gate electrode layer on the upper gate dielectric layer.

In another embodiment, in the electroplating, the electrolyte solution may include a surface active agent, and the surface active agent may allow the metal channel layer in atomic layer units to be formed on the insulating layer. .

 According to another aspect of the present application for achieving the above technical problem is provided an electric device. The electric device is extended from a substrate including a gate electrode layer therein, a gate insulating layer positioned on the substrate, a source electrode layer and a drain electrode layer spaced apart from each other on the gate insulating layer, and the source electrode layer and the drain electrode layer, respectively. A source extension layer and a drain extension layer disposed to face each other and an electroplated metal channel layer disposed between the source extension layer and the drain extension layer.

In example embodiments, the source extension layer, the drain extension layer, and the metal channel layer may be made of the same metal.

According to the present application, by applying the electroplating method using the tunneling current, it is possible to form a metal channel layer having a sufficiently thin thickness.

In addition, according to the present application, the electrolysis method of the electrolyte solution may be applied to the channel layer patterning method, and the electroplating method using the tunneling current may be applied to the metal channel layer forming method. This makes it possible to fabricate electrical devices having metal channel layers of sufficiently small length, width and thickness as required by the industry.

1 is a schematic view of an electrical device according to an embodiment of the present application.
2 is a schematic view of an electrical device according to another embodiment of the present application.
3A to 3C are cross-sectional views illustrating a method of forming a channel layer of an electric device according to an embodiment of the present application.
4A to 4G are cross-sectional views illustrating a method of manufacturing an electrical device according to an embodiment of the present application.
5A to 5C are cross-sectional views illustrating a method of manufacturing an electrical device according to another embodiment of the present application.
6A to 6F are cross-sectional views illustrating a method of manufacturing an electrical device according to an embodiment of the present application.
7A to 7C are cross-sectional views illustrating a method of manufacturing an electrical device according to another embodiment of the present application.

Hereinafter, exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings. However, the technology disclosed in the present application is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete, and that the spirit of the present application is sufficiently conveyed to those skilled in the art. In the drawings, the width and thickness of the layers (or layers) and regions are slightly enlarged in order to clearly represent the various layers (or layers) and regions. When described in the drawings as a whole, at the point of view of the observer, and when one element is referred to as being positioned on another element or substrate, it may be said that the one element is placed directly on another element or substrate or an additional element may be interposed between them. It includes everything that it is. In addition, one of ordinary skill in the art may implement the spirit of the present application in various other forms without departing from the technical spirit of the present application. Wherein like reference numerals refer to like elements throughout the several views.

1 is a schematic view of an electrical device according to an embodiment of the present application. Referring to FIG. 1, the electrical device 100 is disposed apart from each other on a substrate 110 including a gate electrode layer 130, an insulating layer 120 disposed on the substrate 110, and an insulating layer 120. And a metal channel layer 160 positioned between the source electrode layer 140 and the drain electrode layer 150, and between the source electrode layer 140 and the drain electrode layer 150. The electric device 100 may be, for example, a switching device. A voltage may be applied between the source electrode layer 140 and the drain electrode layer 150 to conduct charge through the metal channel layer 160. The gate voltage applied to the gate electrode layer 130 may form an electric field in the metal channel layer 160 to control the movement of the charge. When the metal channel layer 160 of the electric device 100 has a thickness of several nm, the metal channel layer 160 may operate similar to the channel layer of the MOS field effect transistor. That is, according to a voltage applied from the outside, depletion, accumulation, and inversion may occur in the metal channel layer 160, and thus electrons or holes having a charge may conduct. The electrical device 100 may be, for example, a transistor operating in a depletion mode. In the turn-on operation of the transistor, when a predetermined voltage is applied between the device electrode layer 140 and the drain electrode layer 150, electrons or holes having charge along the metal channel layer 160 may conduct. . In the turn-off operation of the transistor, when a predetermined gate voltage is applied to the gate electrode layer 130, an electric field may be formed in the metal channel layer 160 to generate a depletion of the charge. Accordingly, the electrons or the holes moving along the metal channel layer 160 may be blocked. As another example, the electrical device 100 may be a transistor that operates in an enhancement mode. Applying a voltage only between the device electrode layer 140 and the drain electrode layer 150 maintains a turn-off state without electrons or holes being conducted along the metal channel layer 160. In the turn-on operation of the transistor, when a predetermined gate voltage is applied to the gate electrode layer 130, a charge accumulation layer or an inversion layer is formed on the metal channel layer 160, and the accumulation layer Alternatively, the electrons or the holes may move between the source electrode layer 140 and the drain electrode layer 150 along the inversion layer. In addition, in the turn-off operation of the transistor, the accumulation layer or the inversion layer formed on the metal channel layer 160 may be removed by removing the predetermined gate voltage applied to the gate electrode layer 130. Accordingly, the electrons or holes flowing between the source electrode layer 140 and the drain electrode layer 150 may be blocked. As such, the electrical device 100 may operate as a switching device. Regarding the theory of the switching element using the above-described metal channel layer 160, as an example, it is disclosed in WO 2005/093868, which forms part of the content of the present application.

In the electric device 100, the substrate 110 may be a conductive substrate. In the present specification, the conductive substrate may be defined to include both when the entire substrate is conductive, or when a portion of the substrate is conductive by a conductive pattern or a conductive circuit formed in the substrate. . The substrate 110 may be, for example, a doped semiconductor substrate, a metal substrate, a conductive metal oxide, or a conductive polymer substrate. As another example, the substrate 110 may be manufactured by forming a conductive pattern in an insulating substrate or a semiconductor substrate. The semiconductor substrate may be, for example, silicon, germanium, gallium arsenide, indium phosphorus, or the like. The insulating substrate may be, for example, silicon oxide, aluminum oxide, diamond, or the like.

The substrate 110 may include an integrated circuit (not shown) therein to transmit and receive electrical signals. The substrate 110 may include a gate electrode layer 130. The gate electrode layer 130 may receive a gate voltage from the outside to form an electric field in the metal channel layer 160. The electric field may cause depletion, accumulation, and inversion of the charge in the metal channel layer 160. The gate electrode layer 130 may be formed of a conductive pattern, and may be formed from a doped semiconductor, a metal, a metal silicide, or a conductive metal oxide.

The insulating layer 120 is disposed on the substrate 110. The insulating layer 120 may function as the gate insulating layer corresponding to the gate electrode layer 130. For example, the insulating layer 120 may be formed of a silicon oxide film, a silicon nitride oxide film, a silicon nitride film, a hafnium oxide film, a tantalum oxide film, a titanium oxide film, or an aluminum oxide film. For example, when the substrate 110 is made of silicon, the insulating layer 120 may be a silicon oxide film formed by oxidizing silicon by thermal oxidation. For example, the insulating layer 120 may have a thickness of about 10 μs to about 200 μs.

The source electrode layer 140 and the drain electrode layer 150 are spaced apart from each other on the insulating layer 120. The source electrode layer 140 and the drain electrode layer 150 provide or receive electrons or holes that move along the metal channel layer 160 when a voltage is applied between the source electrode layer 140 and the drain electrode layer 150 from the outside. Function. The source electrode layer 140 and the drain electrode layer 150 may be formed in a conductive pattern. For example, the source electrode layer 140 and the drain electrode layer 150 may be formed from a doped semiconductor, a metal, a metal silicide, or a conductive metal oxide.

The metal channel layer 160 is disposed between the source electrode layer 140 and the drain electrode layer 150. The metal channel layer 160 may be formed from, for example, gold, silver, platinum, aluminum, lead, hafnium, tantalum, titanium, copper, tin, or palladium. As an example, the metal channel layer 160 may include one or more layers of metal atoms, and may have a thickness of about 5 GPa or more. According to an embodiment, in the case of a transistor in a depletion mode for conducting electrons, a depletion of charged electrons may be generated in the metal channel layer 160 by applying a predetermined negative voltage to the gate electrode layer 130. . Therefore, even if a predetermined voltage is applied between the source electrode layer 140 and the drain electrode layer 150, electrons do not conduct between the source electrode layer 140 and the drain electrode layer 150. According to another exemplary embodiment, in the case of an active mode transistor that conducts electrons, a predetermined amount of voltage is applied to the gate electrode layer 130, thereby accumulating or inverting charged electrons in the metal channel layer 160. Can be. Therefore, when a predetermined voltage is applied between the source electrode layer 140 and the drain electrode layer 150, electrons may conduct between the source electrode layer 140 and the drain electrode layer 150. In another embodiment, transistors in which holes in the metal channel layer move charges can also operate in substantially the same depletion mode and active mode as described above. As an example, the driving of a switching element using metal as a channel layer is disclosed in WO 2005/093868, which forms part of the content of the present application.

2 is a schematic view of an electrical device according to another embodiment of the present application. Referring to FIG. 2, the electric element 200 includes a substrate 210, an insulating layer 220 disposed on the substrate 210, a source electrode layer 240 and a drain electrode layer spaced apart from each other on the insulating layer 220. 250, a metal channel layer 260 positioned between the source electrode layer 240 and the drain electrode layer 250. The electric device 200 includes an upper insulating layer 225 and an upper gate electrode layer 230 disposed on the metal channel layer 260.

The substrate 210 may be a conductive substrate, and may include an integrated circuit (not shown) therein to transmit and receive electrical signals. In contrast to the electrical device 100 of FIG. 1, the electrical device 200 is formed on top of the metal channel layer 260 instead of the gate electrode layer 130 disposed below the metal channel layer 160. ) And the upper gate electrode layer 230. Except for this, the electric element 200 has substantially the same components as the electric element 100. Therefore, detailed description will be omitted to avoid duplication.

According to some other embodiments, the electric element 200 is a lower gate electrode layer (not shown) disposed on the substrate 210 under the insulating layer 220 positioned between the source electrode layer 240 and the drain electrode layer 250. It may further include. The lower gate electrode layer may function substantially the same at substantially the same position as the gate electrode layer 130 of FIG. 1. As such, the electric device 200 may apply an electric field to the metal channel layer 260 using the lower gate electrode layer and the upper gate electrode layer 230. As described above, when the electric element employs the metal channel layers 160 and 260, the conductivity of electrons or holes moving through the metal channel layers 160 and 260 is improved, thereby reducing the size of the switching element. There is an advantage in that it is possible to suppress the short channel effect problem and leakage current increase in the idle state.

Hereinafter, a method of manufacturing an electric device according to embodiments of the present application will be described.

3A to 3C are cross-sectional views illustrating a method of forming a channel layer of an electric device according to an embodiment of the present application. Referring to FIG. 3A, a conductive substrate 310 having an insulating layer 320 thereon is provided. The conductive substrate 310 may be, for example, a semiconductor substrate, a metal substrate, a conductive metal oxide, or a conductive polymer substrate doped with n-type or p-type. As another example, the conductive substrate 310 may be a substrate that is locally conductive by forming a conductive pattern on an insulating substrate or a portion of the semiconductor substrate. The semiconductor substrate may be, for example, silicon, germanium, gallium arsenide, indium phosphorus, or the like. The insulating substrate may be, for example, silicon oxide, aluminum oxide, diamond, or the like. The conductive substrate 310 may include an integrated circuit (not shown) therein to transmit and receive electrical signals.

According to an embodiment, the insulating layer 320 may be formed by thermally oxidizing the conductive substrate 310. The insulating layer 120 may be formed of a silicon oxide film, a silicon nitride oxide film, a silicon nitride film, a hafnium oxide film, a tantalum oxide film, a titanium oxide film, or an aluminum oxide film. For example, when the conductive substrate 310 is made of silicon, the silicon oxide thin film may be formed on the conductive substrate 310 by thermally oxidizing the doped silicon. As another example, when the conductive substrate is a metal substrate, the metal substrate may be thermally oxidized to form a metal oxide film. According to other embodiments, the insulating layer 320 may be formed by performing a deposition method such as chemical vapor deposition, sputtering, atomic layer deposition, thermal evaporation, or electron beam evaporation. . The insulating layer 320 may be applied as a gate oxide film of the switching device. For example, the insulating layer 120 may be formed to have a thickness of about 10 μs to about 200 μs.

Referring to FIG. 3B, electroplating is performed in the electrolyte solution 330 using the conductive substrate 310 and the metal 350 to be plated as electrodes. The conductive substrate 310 having the insulating layer 320 thereon is immersed in the container 340 including the electrolyte solution 330, and a metal channel layer is formed on the insulating layer 320 through the electroplating. The metal 350 may be, for example, gold, silver, platinum, aluminum, lead, hafnium, tantalum, titanium, copper, tin, or palladium. The electrolyte solution 330 may include ions of the metal 350 to be plated. As an example, when the metal 350 is gold (Au), the electrolyte solution 330 may be a solution containing gold chloride acid (HAuCl 4). As another example, when the metal 350 is silver (Ag), the electrolyte solution 330 may be a solution containing silver nitrate (AgNO 3). As another example, when the metal 350 is platinum, the electrolyte solution 330 may be a solution including dinitroplatinum sulfate (H 2 Pt (NO 2) 2 SO 4) or platinum hydrochloric acid (H 2 PtCl 6). The electrolyte solution 330 may additionally include a surfactant. The surface active agent may function to assist deposition of atomic layer units of metal during electroplating described below. The power source 360 may provide a voltage between the conductive substrate 310 present in the electrolyte solution 330 and the metal 350 to be plated.

In an embodiment, a voltage may be applied such that the metal 350 has a positive polarity and the conductive substrate 310 has a relatively negative polarity. At this time, atoms in the metal 350 in contact with the electrolyte solution 330 are oxidized to generate metal ions 355, and the metal ions 355 may flow into the electrolyte solution 330. The conductive substrate 310 may generate a tunneling current 365 passing through the insulating layer 320 in response to the voltage applied from the power source 360. The tunneling current 365 may be generated by electrons having a charge passing through the insulating layer 320 in a tunneling conduction manner. As an example, when the insulating layer 320 is formed to have a thickness of 10 kV to 200 kV, the direct tunneling method or the Fowler-Nordim tunneling is proportional to the magnitude of the voltage applied to the conductive substrate 310. Electrons may pass through the insulating layer 320 in a Fowler-Nordheim tunneling manner.

The electrons of the tunneling current 365 passing through the insulating layer 320 from the conductive substrate 310 may combine with the metal ions 355 in the electrolyte solution 330 at the surface of the insulating layer 320. The metal ions 355 may be combined with the electrons to be reduced to the metal atoms 370 on the insulating layer 320. The reduced metal atoms 370 may be stacked on the insulating layer 320. According to some embodiments, the electrolyte solution 330 may include a surfactant. As an example, the surface active agent acts on the surface of the insulating layer 320 or the interface of the metal atoms 370 reduced during electroplating to remove foreign substances from the surface of the insulating layer 320 and to reduce the metal. The atoms 370 may be stacked on the insulating layer 320 in a monolayer unit. The surfactant may be applied to various known materials determined according to the type of the insulating layer 320 and the metal atoms 370.

In some embodiments, a thiol treatment may be performed on the insulating layer 320 prior to the electroplating associated with FIG. 3B. The thiol treatment is a kind of organic sulfide, which means to provide a thiol, which is a compound in which a hydrogen atom of aliphatic hydrocarbon is substituted with a mercapto group, on the insulating layer 320. The thiol may be represented by the general formula RSH, wherein R may be an alkyl group. The thiol disposed on the insulating layer 320 may increase the bonding force between the metal atom 370 and the insulating layer 320 to be plated on the insulating layer 320 in a subsequent electroplating process. Accordingly, the interface bonding force between the metal channel layer formed from the plated metal atom 370 and the insulating layer 320 may be improved. As an example, when the metal to be plated is gold, the thiol treatment may be performed using a material such as 3-mercaptopropyltrimethoxysilane (MPTS).

Referring to FIG. 3C, the metal atoms 370 stacked on the insulating layer 320 through the above-described electroplating form the metal channel layer 390. As an example, the metal channel layer 390 may include one or more layers of metal atoms, and may have a thickness of about 5 GPa or more. According to an example in which the metal channel layer 390 is applied to an electric device, the metal channel layer 390 may have a thickness of about 10 μs to about 100 μs, and may include several to several tens of layers of metal atoms. As an example, when gold (Au) is used as the metal 350 and a doped silicon substrate is used as the conductive substrate 310, 5V is applied to the gold (Au) electrode, and the doped silicon substrate is used. A ground voltage (eg, 0 V) may be applied to the metal channel layer including the gold atom layer on the silicon oxide film on the doped silicon substrate.

As described above, by applying the electroplating method using the tunneling current according to an embodiment of the present application it is possible to reliably form a thin metal channel layer of several to several tens of atomic layer units on the insulator. When the metal channel layer is applied in the switching element, the metal channel layer may cause depletion, accumulation or inversion of electrons or holes depending on the magnitude of the applied voltage.

4A to 4G are cross-sectional views illustrating a method of manufacturing an electrical device according to an embodiment of the present application. Referring to FIG. 4A, an insulating layer 420 is formed on the conductive substrate 410. The conductive substrate 410 may be, for example, a semiconductor substrate, a metal substrate, a conductive metal oxide, or a conductive polymer substrate doped with n-type or p-type. As another example, the conductive substrate 410 may be a locally conductive substrate by forming a conductive pattern on an insulating substrate or a portion of the semiconductor substrate. The semiconductor substrate may be, for example, silicon, germanium, gallium arsenide, indium phosphorus, or the like. The insulating substrate may be, for example, silicon oxide, aluminum oxide, diamond, or the like. The conductive substrate 410 may include an integrated circuit (not shown) therein to transmit and receive electrical signals.

According to an embodiment, the insulating layer 420 may be formed by thermally oxidizing the conductive substrate 410. The insulating layer 420 may be formed of a silicon oxide film, a silicon nitride oxide film, a silicon nitride film, a hafnium oxide film, a tantalum oxide film, a titanium oxide film, or an aluminum oxide film. For example, when the conductive substrate 410 is made of silicon, the silicon oxide thin film may be formed on the conductive substrate 410 by thermally oxidizing the doped silicon. As another example, when the conductive substrate is a metal substrate, the metal substrate may be thermally oxidized to form a metal oxide film. According to another embodiment, the insulating layer 420 may be formed on the conductive substrate 410 by chemical vapor deposition, sputtering, atomic layer deposition, thermal evaporation, or electron beam evaporation. Can be formed by deposition. The insulating layer 420 may be applied as a gate oxide layer of the switching element, and may be formed to have a thickness of about 10 μs to about 200 μs.

Referring to FIG. 4B, the source electrode layer 422 and the drain electrode layer 424 are formed on the insulating layer 420 so as to be spaced apart from each other. The source electrode layer 422 and the drain electrode layer 424 may be formed in a conductive pattern. The source electrode layer 422 and the drain electrode layer 424 are, for example, formed by forming a conductive thin film on the insulating layer 420 and then patterning it, such as a doped semiconductor, metal, metal silicide or conductive metal oxide. Can be formed. According to an embodiment, the conductive thin film may be formed by, for example, a process such as chemical vapor deposition, sputtering, electron beam evaporation, or thermal evaporation. Thereafter, the conductive thin film may be patterned by a known photolithography process and an etching process to form the source electrode layer 422 and the drain electrode layer 424.

Referring to FIG. 4C, the conductive substrate 410 including the insulating layer 420, the source electrode layer 422, and the drain electrode layer 424 is immersed in the electrolyte solution 430. Then, electroplating is performed using the conductive substrate 410 and the metal 450 to be plated as electrodes. First, the conductive substrate 410 is immersed in the container 440 containing the electrolyte solution 430. The electrolyte solution 430 may include ions of the metal 450 to be plated. The metal 450 may be, for example, gold, silver, platinum, aluminum, lead, hafnium, tantalum, titanium, copper, tin, or palladium. As an example, when the metal 350 is gold (Au), the electrolyte solution 330 may be a solution containing gold chloride acid (HAuCl 4). As another example, when the metal 350 is silver (Ag), the electrolyte solution 330 may be a solution containing silver nitrate (AgNO 3). As another example, when the metal 350 is platinum, the electrolyte solution 330 may be a solution including dinitroplatinum sulfate (H 2 Pt (NO 2) 2 SO 4) or platinum hydrochloric acid (H 2 PtCl 6). The electrolyte solution 430 may additionally include a surfactant. For example, the surface active agent acts on the surface of the insulating layer 420 or the interface of the metal atoms 470 reduced during electroplating, thereby removing foreign substances from the surface of the insulating layer 420 and reducing the metal. The atoms 470 may function to be stacked in a monolayer on the insulating layer 420.

Electroplating may be performed by using a power source 460 to provide a voltage between the conductive substrate 410 present in the electrolyte solution 430 and the metal 450 to be plated. In an exemplary embodiment, a positive voltage may be applied to the metal 450, and a negative voltage may be applied to the conductive substrate 410 or may be adjusted to maintain a ground state. As a result, atoms of the metal 450 in contact with the electrolyte solution 430 are oxidized to generate metal ions 455, and the metal ions 455 may flow into the electrolyte solution 430. The conductive substrate 410 may generate a tunneling current 465 passing through the insulating layer 420 in response to the voltage applied from the power source 460. The tunneling current 465 may be generated by passing electrons having a charge through the insulating layer 420 in a tunneling conduction manner. As an example, when the insulating layer 420 is formed to have a thickness of 10 kV to 200 kV, a direct tunneling method or a Fowler-nordim tunneling is proportional to the magnitude of the voltage applied to the conductive substrate 410. Electrons may pass through the insulating layer 420 in a Fowler-Nordheim tunneling manner.

The electrons of the tunneling current 465 passing through the insulating layer 420 from the conductive substrate 410 may combine with the metal ions 455 in the electrolyte solution 430 on the surface of the insulating layer 420. The metal ions 455 may be combined with the electrons to be reduced to the metal atoms 470 on the insulating layer 420. The reduced metal atoms 470 may be stacked on the insulating layer 420. Although not shown, some of the electrons of the tunneling current 465 passing through the insulating layer 420 from the conductive substrate 410 may reach the source electrode layer 422 or the drain electrode layer 424. In this case, by applying a predetermined voltage from the outside to the source electrode layer 422 and the drain electrode layer 424, electrons not participating in the reduction reaction of the metal ions 455 may be discharged from the conductive substrate 410 to the outside. .

According to one embodiment, as described above, the conductive substrate 410 may be locally conductive by forming a conductive pattern on a portion of the insulating substrate or the semiconductor substrate. As shown in FIG. 4C, the conductive pattern may be present in the conductive substrate 410 under the insulating layer 420 corresponding to the space between the source electrode layer 422 and the drain electrode layer 424. In this case, the electrons due to the tunneling current may be provided in the space between the source electrode layer 422 and the drain electrode layer 424, and the metal ions 455 may be formed in the space on the insulating layer 420. 470).

4D is a cross-sectional view illustrating a plating method according to another embodiment of the present application. As illustrated, the conductive substrate 410 including the insulating layer 420, the source electrode layer 422, and the drain electrode layer 424 is immersed in the container 440 including the electrolyte solution 430. Electroplating may be performed by providing a voltage between the conductive substrate 410 present in the electrolyte solution 430 and the metal 450 to be plated using the power source 460. In an exemplary embodiment, a positive voltage may be applied to the metal 450, and a negative voltage may be applied to the conductive substrate 410 or may be adjusted to maintain a ground state.

A voltage is applied between the source electrode layer 422 and the drain electrode layer 424 using the power supply 480, and a current flowing between the source electrode layer 422 and the drain electrode layer 424 is measured using the measuring instrument 485. Can be. During the electroplating, the metal atoms 470 reduced from the metal ions 455 are stacked on the insulating layer 420 between the source electrode layer 422 and the drain electrode layer 424. The stacked metal atoms 470 may form a metal channel layer between the source electrode layer 422 and the drain electrode layer 424. When a current equal to or greater than a predetermined threshold current value is observed in the meter 484, it may be predicted that a metal channel layer is formed between the source electrode layer 422 and the drain electrode layer 424. In addition, based on the magnitude of the measured current, it is possible to predict the thickness of the metal channel layer to be formed.

In one embodiment, when gold (Au) is used as the metal 450 to be plated and a silicon substrate doped with the conductive substrate 410 is used, a ground voltage (for example, 0 V) is applied to the doped silicon substrate. Voltage of 5V is applied to gold, based on ground voltage. A voltage of 4.9V may be applied to the source electrode layer 422 based on the ground voltage, and a voltage of 5V may be applied to the drain electrode layer 424 based on the ground voltage. As a result, gold atoms are stacked on the insulating layer 420 between the source electrode layer 422 and the drain electrode layer 424 to form a metal channel layer of gold. The source electrode layer 422 and the drain electrode layer 424 maintain a voltage similar to the voltage of 5V applied between the gold and the doped silicon substrate, respectively, thereby providing gold on the source electrode layer 422 and the drain electrode layer 424. It is possible to prevent atoms from being reduced. When a predetermined current value is observed by the measuring instrument 485, the electroplating process may be completed to secure a metal channel layer of gold having a predetermined thickness.

According to some embodiments, the electrolyte solution 330 may include a surfactant. As an example, the surface active agent acts on the surface of the insulating layer 320 or the interface of the metal atoms 370 reduced during electroplating to remove foreign substances from the surface of the insulating layer 320 and to reduce the metal. The atoms 370 may function to be stacked on the insulating layer 320 in a monolayer unit.

In some embodiments, a thiol treatment may be performed on the source electrode layer 422 and the drain electrode layer 424 prior to the electroplating process described above with reference to FIG. 4C or 4D. The thiol treatment is a kind of organic sulfide, which means that the thiol, which is a compound in which a hydrogen atom of aliphatic hydrocarbon is substituted with a mercapto group, is provided to the source electrode layer 422 and the drain electrode layer 424. The thiol may be represented by the general formula RSH, wherein R may be an alkyl group. The thiols disposed on the source electrode layer 422 and the drain electrode layer 424 prevent the metal atoms 470 from adhering to the source electrode layer 422 and the drain electrode layer 424 which are conductors in the subsequent electroplating process. can do. As an example, when the metal to be electroplated is gold, the thiol may apply 11-thioundecanoic acid (HS-C10-COOH).

 In some other embodiments, thiol treatment may be performed on the insulating layer 420 prior to the electroplating process described above with reference to FIG. 4C or 4D. The thiol treatment may increase the bonding force between the metal atom 470 and the insulating layer 420 plated on the insulating layer 420 in a subsequent electroplating process. Accordingly, the interface bonding force between the metal channel layer formed from the plated metal atoms 470 and the insulating layer 420 may be improved. As an example, when the metal to be plated is gold, the thiol treatment may be performed using a material such as 3-mercaptopropyltrimethoxysilane (MPTS).

Referring to FIG. 4E, the metal channel layer 490 is formed on the insulating layer 420 by the electroplating method of FIG. 4C or 4D. The metal channel layer 490 may include, for example, one or more layers of metal atoms, and may have a thickness of about 5 GPa or more. According to an example in which the metal channel layer 490 is applied to an electric device, the metal channel layer 490 may have a thickness of 10 μs to 100 μs, and may include several to several tens of metal atomic layers.

Referring to FIG. 4F, a gate dielectric layer 492 and a gate electrode 494 are formed on the metal channel layer 490. First, the metal channel layer 490 of FIG. 4E may be additionally patterned. As an example, the photolithography and etching processes may be used to pattern the metal channel layer 490 to have a shape and function that matches the channel layer of the electrical device. Thereafter, an oxide film or a nitride film can be formed as the gate dielectric film 492. The oxide layer may include a metal oxide such as silicon oxide or hafnium oxide, aluminum oxide, tantalum oxide, titanium oxide, or the like. The nitride film may include silicon nitride or metal nitride such as aluminum nitride, tantalum nitride, titanium nitride, or the like. The gate dielectric film 492 may be formed by performing chemical vapor deposition, sputtering, atomic layer deposition, thermal evaporation, or electron beam evaporation. The gate dielectric layer 492 may be formed to have a thickness of about 10 μs to about 200 μs.

The gate electrode 494 may be formed on the gate dielectric layer 492. In the formation of the gate electrode 494, first, a conductive thin film such as doped semiconductor, metal, metal silicide or conductive metal oxide is formed on the gate dielectric film 492 as an example. According to an embodiment, the conductive thin film may be formed by a process such as chemical vapor deposition, sputtering, electron beam evaporation, or thermal evaporation. Thereafter, the conductive thin film may be patterned by a photolithography process and an etching process to form the gate electrode 494. The gate electrode 494 may receive a predetermined gate voltage from the outside to form an electric field in the metal channel layer 490. The electric field formed in the metal channel layer 490 generates a depletion of charge in the metal channel layer 490, or accumulates or inverts the charge, thereby causing the source electrode layer 422 to pass through the metal channel layer 490. The flow of charges conducting between the drain electrode layer 424 and the drain electrode layer 424 may be controlled.

5A to 5C are views illustrating a manufacturing method of an electric device according to another embodiment of the present application. Referring to FIG. 5A, a substrate 510 having an insulating layer 520 thereon is provided. The gate electrode layer 515 may be formed on the substrate 510. According to an embodiment, the dopant may be implanted into a portion of the substrate 510 by using an ion implantation method or a diffusion method, and thus the gate electrode layer 515 may be formed on the portion of the substrate 510. In another embodiment, the substrate 510 may be etched by a lithography process and an etching process to form a predetermined contact pattern, and the gate electrode layer 515 may be formed by filling the contact pattern with a conductive material. The gate electrode layer 515 may be formed from, for example, a doped semiconductor, a metal, a metal silicide, or a conductive metal oxide. An insulating layer 520 may be formed on the substrate 510 on which the gate electrode layer 515 is formed. The substrate 510 is substantially the same as the conductive substrate 410 and insulating layer 420 described in connection with FIG. 4A except that the substrate 510 includes a gate electrode layer 515.

Thereafter, substantially the same process as in the embodiment described above with reference to FIGS. 4B-4D can be performed. As a result, as shown in FIG. 5B, the metal channel layer 590 may be formed on the insulating layer 520 between the source electrode layer 522 and the drain electrode layer 524. As an example, an electroplating process may be performed substantially the same as the electroplating process of the embodiment of FIG. 4C or 4D, and a predetermined voltage may be applied between the metal to be plated and the gate electrode layer 515. In this case, a tunneling current passing through the insulating layer 520 from the gate electrode layer 515 may occur, and thus, the metal channel layer 590 may be formed on the insulating layer 520 on the gate electrode layer 515. have.

According to some embodiments, as shown in FIG. 5C, an upper gate dielectric layer 592 and an upper gate electrode 594 may be additionally formed on the metal channel layer 590. The process of forming the upper gate dielectric film 592 and the upper gate electrode 594 may be performed by forming the gate dielectric film 492 and the gate electrode 494 on the metal channel layer 490 in the embodiment described above with reference to FIG. 4F. Since it is substantially the same as the process, it will be omitted to avoid duplication. As a result, an electric device may be formed on the upper and lower portions of the metal channel layer 590, respectively.

As described above, an electroplating method using a tunneling current may be performed to manufacture an electric element including a metal channel layer. The metal channel layer may cause depletion, accumulation, or inversion of electrons according to the magnitude of the gate voltage applied thereto. By employing the metal channel layer, the conductivity of electrons or holes in the channel layer is superior to that of the conventional one, and an electric element having a relatively small leakage current in the idle state can be formed.

6A to 6F are cross-sectional views illustrating a method of manufacturing an electrical device according to an embodiment of the present application. Referring to FIG. 6A, the source electrode layer 622 and the drain electrode layer 624 are formed to be spaced apart from each other on the conductive substrate 610 including the insulating layer 620. The conductive substrate 610, the insulating layer 620, the source electrode layer 622, and the drain electrode layer 624 include the conductive substrate 410, the insulating layer 420, and the source electrode layer 422 described above with reference to FIGS. 4A through 4E. And the drain electrode layer 424, and may be formed through a process substantially the same as the process described above with reference to FIGS. 4A and 4B.

Referring to FIG. 6B, the base metal layer 625 is formed on the conductive substrate 610 including the insulating layer 620, the source electrode layer 622, and the drain electrode layer 624. The base metal layer 625 may be, for example, a conductive thin film formed from a doped semiconductor, a metal, a metal silicide, or a conductive metal oxide. As one example, the base metal layer 625 may be made from gold, silver, platinum, aluminum, lead, hafnium, tantalum, titanium, copper, tin or palladium. As an example, the base metal layer 625 may be formed from the same material as the source electrode layer 622 and the drain electrode layer 624. According to an embodiment, the base metal layer 625 may be formed by depositing the conductive thin film on the conductive substrate 610 using a process such as chemical vapor deposition, sputtering, electron beam evaporation, or thermal evaporation.

Referring to FIG. 6C, a photoresist is applied on the conductive substrate 610 and a lithography process is performed to form a photoresist pattern 626 exposing a portion of the base metal layer 625. The photoresist pattern 626 may be formed by performing at least one lithography process, and may include a via hole 627 exposing a portion of the base metal layer 625. As shown, the lateral length X of the via hole 627 may be less than the length Y between the source electrode layer 622 and the drain electrode layer 624.

Referring to FIG. 6D, the portion of the base metal layer 625 exposed by the photoresist pattern 626 is removed to expose a portion of the insulating layer 620. According to an embodiment, the portion of the base metal layer 625 may be removed by an electrolysis method using the electrolyte solution 630. First, the electrolyte solution 630 is provided to the conductive substrate 610 on which the photoresist pattern 626 is formed. The method of providing the electrolyte solution 630 to the conductive substrate 610 may be, for example, a method of dipping the conductive substrate 610 in the electrolyte solution 630 or spraying the electrolyte solution 630 on the conductive substrate 610 ( spray) and the like, but is not limited thereto, and various known methods may be applied. Hereinafter, as an example, a method of dipping the conductive substrate 610 in the electrolyte solution 630 will be described with reference to the accompanying drawings.

The conductive substrate 610 is immersed in the container 640 including the electrolyte solution 630, and the conductor introduced from the outside using the source electrode layer 622 and the drain electrode 624 of the conductive substrate 610 as the anode electrode. Electrolyte solution 630 is electrolyzed using 650 as a cathode electrode. The conductor 650 may be, for example, a metal such as gold, silver, platinum, aluminum, lead, hafnium, tantalum, titanium, copper, tin, or palladium, but a known electrode material may be used. In the electrolysis process, the metal of the base metal layer 625 is converted into metal ions 655 to be introduced into the electrolyte solution 630, thereby removing the portion of the base metal layer 625. As a result, the source extension layer 632 and the drain extension layer 634 separated by the contact pattern 628 and the contact pattern 628 can be formed. The size of the contact pattern 628 may determine the length and width of the metal channel layer of the electrical device to be described later. The source extension layer 632 and the drain extension layer 634 surround the source electrode layer 622 and the drain electrode layer 624, respectively, and extend from each of the source electrode layer 622 and the drain electrode layer 624 to be formed to face each other. Can be. The electrolysis method may prevent the lower insulating layer 620 from being damaged while removing a portion of the base metal layer 625. Therefore, the insulating layer 620 exposed by the contact pattern 628 is not subjected to mechanical and electrical damage, and as described below, the metal channel layer forming process can be reliably performed on the exposed insulating layer 620. Will be. That is, as an example, the metal channel layer may be uniformly formed on the exposed insulating layer 620.

According to an embodiment, when the base metal layer 625 is made of gold, the electrolyte solution 630 may use a solution containing hydrochloric acid (HCl). The conductive substrate 610 including the photoresist pattern 626 is dipped in the container 640 in which the electrolyte solution 630 containing hydrochloric acid (HCl) is contained. The power source 660 may apply a negative voltage to the conductor 650, and apply a ground voltage (eg, 0 V) to the source electrode layer 622 and the drain electrode layer 624. In the electrolysis process of the electrolyte solution 630, the gold of the base metal layer 625 partially exposed by the photoresist pattern 626 is oxidized to gold ions 655 and introduced into the electrolyte solution 630. Through electrolysis as described above, the gold of the base metal layer 625 may be partially removed, and the contact pattern 628 may be formed. When the contact pattern 628, the source extension layer 632, and the drain extension layer 634 are formed, the photoresist pattern 626 may be removed.

According to some other embodiments, removal of the base metal layer 625 partially exposed by the photoresist pattern 626 may be performed by an etching process unlike the embodiment of FIG. 6D. The etching process may be performed by dry etching, wet etching, or a combination thereof. In the etching process, a known etching solution or an etching gas applicable to the metal of the base metal layer 625 may be used. When the contact pattern 628, the source extension layer 632, and the drain extension layer 634 are formed by an etching process, the photoresist pattern 626 may be removed. Subsequent heat treatment can compensate for the damage of the insulator surface in the etching process.

Referring to FIG. 6E, the conductive substrate 610 including the contact pattern 628 is immersed in the electrolyte solution 635. Then, electroplating is performed using the conductive substrate 610 and the metal 652 to be plated as electrodes. First, the conductive substrate 610 is immersed in a container 645 containing the electrolyte solution 635. The electrolyte solution 635 may include ions of the metal 652 to be plated. The metal 652 may be, for example, gold, silver, platinum, aluminum, lead, hafnium, tantalum, titanium, copper, tin or palladium. As an example, when the metal 652 is gold (Au), the electrolyte solution 635 may be a solution including HAuCl 4. The electrolyte solution 635 may additionally include a surfactant. The surface active agent may serve to assist deposition of atomic layer units of metal during electroplating. The power supply 665 may provide a voltage between the conductive substrate 610 present in the electrolyte solution 635 and the metal 652 to be plated to perform electroplating. In one embodiment, a positive voltage is applied to the metal 652 and a negative voltage is applied to the conductive substrate 610 or adjusted to maintain a ground state. The metal 652 is oxidized to produce metal ions 656, which may be introduced into the electrolyte solution 635. The conductive substrate 610 may generate a tunneling current 665 passing through the insulating layer 620 in response to the voltage applied from the power source 665. Tunneling current 665 may be generated by passing electrons with charge through insulating layer 620 in a tunneling conduction manner. As an example, when the insulating layer 620 is formed to have a thickness of 10 kV to 200 kV, a direct tunneling method or a Fowler-nordim tunneling is proportional to the magnitude of the voltage applied to the conductive substrate 610. Electrons may pass through the insulating layer 620 in a Fowler-Nordheim tunneling manner.

Some of the electrons in the tunneling current 665 passing through the insulating layer 620 from the conductive substrate 610 may reach the surface of the insulating layer 620 exposed by the contact pattern 628. At the surface of the insulating layer 620 exposed by the contact pattern 628, some of the electrons of the tunneling current 665 may combine with the metal ions 656 in the electrolyte solution 635. The metal ions 656 may be combined with some of the electrons to be reduced to the metal atoms 670 on the insulating layer 620 exposed by the contact pattern 628. The reduced metal atoms 670 may be stacked on the exposed insulating layer 620 to form a metal channel layer. Although not shown, other portions of the electrons of the tunneling current 665 passing through the insulating layer 620 from the conductive substrate 610 may include the source electrode layer 622, the device extension layer 632, the drain electrode layer 624, and the like. Drain extension layer 634 may be reached. At this time, a predetermined voltage is applied to the source electrode layer 622, the device extension layer 632, the drain electrode layer 624, and the drain extension layer 634 so as not to participate in the reduction reaction of the metal ions 656. Electrons may be emitted from the conductive substrate 610 to the outside.

According to an exemplary embodiment, a voltage may be applied between the source electrode layer 522 and the drain electrode layer 524 during the electroplating process by applying the same method as the method described above with reference to FIG. 4D. While the electroplating is in progress, a voltage is applied between the source electrode layer 622 and the drain electrode layer 624 using the power source 680, and the source electrode layer 622 and the drain electrode layer 624 using the meter 685. You can measure the current flowing between them. By measuring the current, it is possible to predict whether the electroplating process is completed and the thickness of the metal channel layer formed. As an example, when gold (Au) is used as the metal 652 to be plated and a doped silicon substrate is used as the conductive substrate 610, a voltage of a ground voltage (eg, 0 V) is applied to the doped silicon substrate. Apply a voltage of 5V to the gold based on the ground voltage. A voltage of 4.9V may be applied to the source electrode layer 622 based on the ground voltage, and a voltage of 5V may be applied to the drain electrode layer 624 based on the ground voltage. In this case, a voltage application pad (not shown) electrically connected to each of the source electrode layer 622, the drain electrode layer 624, and the doped silicon substrate and positioned on the doped silicon substrate may be separately provided. As such, gold atoms are deposited on the insulating layer 620 exposed by the contact pattern 628 between the source extension layer 632 and the drain extension layer 634 to form a metal channel layer of gold. The source electrode layer 622 and the drain electrode layer 624 respectively maintain a voltage having a magnitude similar to a voltage of 5V applied between the gold and the doped silicon substrate, so that the source electrode layer 622, the source extension layer 632, The reduction of gold atoms on the drain electrode layer 624 and the drain extension layer 634 can be prevented. When a predetermined current value is observed by the measuring device 685, the electroplating process may be completed to secure a metal channel layer of gold having a predetermined thickness.

According to some embodiments, the electrolyte solution 635 may include a surfactant. As an example, the surface active agent acts on the surface of the insulating layer 320 or the interface of the metal atoms 370 reduced during electroplating to remove foreign substances from the surface of the insulating layer 320 and to reduce the metal. The atoms 370 may function to be stacked on the insulating layer 320 in a monolayer unit.

In some other embodiments, thiol treatment may be performed on the insulating layer 620 prior to the electroplating of FIG. 6E. The thiol treatment may increase the bonding force between the metal atom 670 and the insulating layer 620 plated on the insulating layer 620 in a subsequent electroplating process. Accordingly, the interface bonding force between the metal channel layer formed from the plated metal atom 670 and the insulating layer 620 may be improved. As an example, when the metal to be plated is gold, the thiol treatment may be performed using a material such as 3-mercaptopropyltrimethoxysilane (MPTS).

6F illustratively shows a metal channel layer 690 formed on the insulating layer 620 between the source extension layer 632 and the drain extension layer 634 as a result of the electroplating method. Referring to FIG. 6G, a gate dielectric film 692 and a gate electrode 694 are formed on the metal channel layer 690. The method of forming the gate dielectric film 692 and the gate electrode 694 is substantially the same as the process of forming the gate dielectric film 492 and the gate electrode 494 on the metal channel layer 490 in the embodiment described above with reference to FIG. 4F. Since the description is the same, it is omitted in order to exclude redundant descriptions.

As described above, an electroplating method using a tunneling current may be performed to form a metal channel layer on the insulator. The metal channel layer may cause depletion, accumulation, or inversion of electrons according to the magnitude of the gate voltage applied thereto, and thus may be applied to the channel layer of the switching element.

7A to 7C are views illustrating a method of manufacturing an electric device according to another embodiment of the present application. Referring to FIG. 7A, a substrate 710 having an insulating layer 720 thereon is provided. The gate electrode layer 715 may be formed on the substrate 710. According to an embodiment, a gate electrode layer 715 may be formed on the portion of the substrate 710 by implanting a dopant into a portion of the substrate 710 using an ion implantation method or a diffusion method. In another embodiment, the substrate 710 may be etched by a lithography process and an etching process to form a predetermined contact pattern, and the gate electrode layer 715 may be formed by filling the contact pattern with a conductive material. The gate electrode 715 may be formed from, for example, a doped semiconductor, a metal, a metal silicide, or a conductive metal oxide. An insulating layer 720 may be formed on the substrate 710 on which the gate electrode layer 715 is formed. The substrate 710 is substantially the same as the conductive substrate 410 and the insulating layer 420 described in connection with FIG. 6A except that the gate electrode layer 715 is included.

Thereafter, substantially the same process as in the embodiment described above with reference to FIGS. 6B-6E can be performed. As a result, as shown in FIG. 7B, the metal channel layer 790 may be formed on the insulating layer 720 between the source extension layer 732 and the drain extension layer 734. As an example, an electroplating process may be performed substantially the same as the electroplating process of the embodiment of FIG. 6E, and a predetermined voltage may be applied between the metal to be plated and the gate electrode layer 715. In this case, a tunneling current passing through the insulating layer 720 from the gate electrode layer 715 may occur, and thus, the metal channel layer 790 may be formed on the insulating layer 720 above the gate electrode 715. have.

According to some embodiments, as shown in FIG. 7C, an upper gate dielectric layer 792 and an upper gate electrode 794 may be additionally formed on the metal channel layer 790. The process of forming the upper gate dielectric layer 792 and the upper gate electrode 794 may be performed by forming the gate dielectric layer 692 and the gate electrode 694 on the metal channel layer 690 in the above-described embodiment with reference to FIG. 6G. Since it is substantially the same as the process, it will be omitted to avoid duplication. As a result, an electric device having gate electrodes may be formed on the upper and lower portions of the metal channel layer 790, respectively.

As described above, an electroplating method using a tunneling current may be performed to manufacture an electric element including a metal channel layer. The metal channel layer may have several to several tens of metal atomic layers, and may cause depletion, accumulation, or inversion of electrons depending on the magnitude of the gate voltage applied thereto. The conductivity of the charge through the metal channel layer is superior to that of the related art, and it is possible to form an electric element having a relatively small leakage current in the atmospheric state.

6A to 6G and 7A to 7C illustrate a method of manufacturing an electric device, in forming a metal channel layer having a predetermined length and width, first, a metal base layer having a sufficient length and width is formed. By forming and removing a portion of the metal base layer, a contact pattern corresponding to a portion where the metal channel layer is to be formed may be previously formed. The metal channel layer may be formed on the insulator inside the contact pattern by electroplating. This makes it possible to more easily control the thickness, length, and width when forming a metal channel layer having a relatively small size. In addition, when removing a part of the metal base layer, when the electrolysis method is used, the underlying insulating layer can be prevented from being damaged, so that the metal channel layer can be uniformly formed in subsequent electroplating methods.

Although described above with reference to the drawings and embodiments, those skilled in the art various modifications and changes to the embodiments disclosed in the present application within the scope not departing from the spirit of the present application described in the claims below I can understand that you can.

100: electrical element, 110: substrate, 120: insulating layer, 130: gate electrode layer, 140: source electrode layer, 150: drain electrode layer, 160: metal channel layer,
200: electric element, 210: substrate, 220: insulating layer, 225: upper insulating layer, 230: upper gate electrode layer, 240: source electrode layer, 250: drain electrode layer, 260: metal channel layer,
310: conductive substrate, 320: insulating layer, 330: electrolyte solution, 340: container, 350: metal, 355: metal ion, 360: power source, 365: tunneling current, 370: metal atom 390: metal channel layer,
410: conductive substrate, 420: insulating layer, 422: source electrode layer, 424: drain electrode layer, 430: electrolyte solution, 440: container, 450: metal, 455: metal ions, 460: power, 465: tunneling current, 470: metal Atomic, 480: power source, 485: instrument, 490: metal channel layer, 492: gate dielectric film, 494: gate electrode,
510: substrate, 515: gate electrode layer, 520: insulating layer, 522: source electrode layer, 524: drain electrode layer, 590: metal channel layer, 592: upper gate dielectric layer, 594: upper gate electrode,
610: substrate, 620: insulating layer, 622: source electrode layer, 624: drain electrode layer, 625: base metal layer, 626: photoresist pattern, 627: via hole, 628: contact pattern, 630: electrolyte solution, 632: source extension layer, 634: drain extension layer, 635: electrolyte solution, 640, 645: container, 650: conductor, 652: metal, 655, 656: metal ion, 660, 665: power, 670: metal atom, 680: power, 685: instrument, 690 : Metal channel layer, 692: gate dielectric film, 694: gate electrode,
710: substrate, 715: gate electrode layer, 720: insulating layer, 722: source electrode layer, 724: drain electrode layer, 732: source extension layer, 734: drain extension layer, 790: metal channel layer, 792: upper gate dielectric film, 794: Top gate electrode.

Claims (33)

(a) providing a conductive substrate having an insulating layer thereon;
(b) dipping the conductive substrate including the insulating layer and a metal to be plated in an electrolyte solution; And
(c) using the conductive substrate and the metal as electrodes, respectively, by applying a voltage to generate a tunneling current through which the electrons pass through the insulating layer from the conductive substrate, the electrons passing through the insulating layer and the metal in the electrolyte solution Forming a metal channel layer on the insulating layer by bonding ions of
Method of forming channel layer of electric element. The method according to claim 1,
The conductive substrate is a semiconductor substrate doped with n-type or p-type
Method of forming channel layer of electric element. The method according to claim 1,
The conductive substrate is a method for forming a channel layer of an electric element formed by forming a conductive pattern in a semiconductor substrate or an insulating substrate. The method according to claim 1,
The electrolyte solution is a channel layer forming method of an electric element containing ions of the metal to be plated. The method according to claim 1,
And the metal is any one selected from the group consisting of gold, silver, platinum, aluminum, lead, hafnium, tantalum, titanium, copper, tin and palladium. The method according to claim 1,
Step (b) is a method of forming a channel layer of an electric device in which the voltage is applied such that the metal has a positive polarity and the conductive substrate has a negative polarity in the electrolyte solution. The method according to claim 1,
Before the step (b), further comprising the step of performing a thiol treatment on the insulating layer, the channel layer forming method of the electric element to increase the bonding force of the metal and the insulating layer produced in the step (b).
(a) forming an insulating layer on the conductive substrate;
(b) forming a source electrode layer and a drain electrode layer on the insulating layer to be spaced apart from each other;
(c) dipping the conductive substrate including the insulating layer, the source electrode layer, and the drain electrode layer in an electrolyte solution; And
(d) performing electroplating using the conductive substrate and the metal to be plated as electrodes, respectively,
And forming a metal channel layer between the source electrode layer and the drain electrode layer by combining electrons of the tunneling current passing through the insulating layer from the conductive substrate with ions of the metal in the electrolyte solution. The method of claim 8,
The conductive substrate is a method of manufacturing an electric element is a semiconductor substrate doped with n-type or p-type. The method of claim 8,
The conductive substrate is a method of manufacturing an electrical element formed by forming a conductive pattern in a semiconductor substrate or an insulating substrate. The method of claim 10,
The conductive pattern is a lower gate electrode layer, and the insulating layer is a lower gate dielectric layer.
Method of manufacturing an electrical device. The method of claim 8,
The electrolyte solution is a manufacturing method of an electric element containing the ions of the metal to be plated. The method of claim 8,
In step (d), a voltage is applied between the source electrode layer and the drain electrode layer, and a current flowing between the source electrode layer and the drain electrode layer is measured to determine whether the electroplating process of forming the metal channel layer is completed. Method of manufacturing an electrical device. The method of claim 8,
And the source electrode layer and the drain electrode layer are formed by depositing and patterning a metal thin film on the insulating layer. The method of claim 8,
(e) forming an upper gate dielectric layer on the metal channel layer; And
(f) forming an upper gate electrode layer on the upper gate dielectric layer. The method of claim 8,
In step (d), the electrolyte solution comprises a surface active agent, the surface active agent is a method of manufacturing an electric element such that the metal channel layer of the atomic layer unit is formed on the insulating layer. The method of claim 8,
Before the step (d), further comprising the step of performing a thiol treatment on the insulating layer, the channel layer forming method of the electric element to increase the bonding force of the metal and the insulating layer produced in the step (d). The method of claim 8,
prior to step (d), further comprising performing a thiol treatment on the source electrode layer and the drain electrode layer to inhibit the metal produced in step (d) from adhering to the source electrode layer and the drain electrode layer. Method of forming channel layer of electric element. (a) forming an insulating layer on the conductive substrate;
(b) forming a source electrode layer and a drain electrode layer on the insulating layer to be spaced apart from each other;
(c) forming a base metal layer on the conductive substrate including the insulating layer, the source electrode layer and the drain electrode layer;
(d) applying a photoresist on the conductive substrate and forming a photoresist pattern exposing a portion of the base metal layer through a lithography process;
(e) removing the portion of the exposed base metal layer to expose a portion of the insulating layer; And
(f) performing electroplating in the electrolyte solution using the conductive substrate and the metal to be plated as electrodes, respectively,
Forming a metal channel layer on the portion of the insulating layer by combining electrons of the tunneling current passing through the insulating layer from the conductive substrate with ions of the metal in the electrolyte solution.
Method of manufacturing an electrical device. The method of claim 19,
and (d) the photoresist pattern determines the length or width of the metal channel layer formed by the electroplating. The method of claim 19,
(e) step
(e1) providing an electrolyte solution for electrolysis on the conductive substrate on which the photoresist pattern is formed; And
(e2) electrolyzing the electrolyte solution for electrolysis by applying a voltage to the electrolyte solution and the conductive substrate,
And the part of the exposed base metal layer is etched by ionizing the exposed metal of the base metal layer into the electrolyte solution for electrolysis by an oxidation reaction of the electrolysis. The method of claim 19,
The conductive substrate is a method of manufacturing an electric element is a semiconductor substrate doped with n-type or p-type. The method of claim 19,
The conductive substrate is a method of manufacturing an electrical element formed by forming a conductive pattern in a semiconductor substrate or an insulating substrate. The method of claim 19,
The conductive pattern is a lower gate electrode layer, and the insulating layer is a lower gate dielectric layer.
Method of manufacturing an electrical device. The method of claim 19,
The electrolyte solution is a manufacturing method of an electric element containing the ions of the metal to be plated. The method of claim 19,
In step (f), a voltage is applied between the source electrode layer and the drain electrode layer, and a current flowing between the source electrode layer and the drain electrode layer is measured to determine whether the electroplating process of forming the metal channel layer is completed. Method of manufacturing an electric device. The method of claim 19,
(g) forming an upper gate dielectric layer on the metal channel layer; And
and (h) forming an upper gate electrode layer on the upper gate dielectric layer. The method of claim 19,
In the step (f), the electrolyte solution comprises a surface active agent, the surface active agent is a method of manufacturing an electric element such that the metal channel layer of the atomic layer unit is formed on the insulating layer. The method of claim 19,
prior to step (f), further comprising performing a thiol treatment on said portion of said insulating layer, thereby increasing the bonding force between said metal produced in step (f) and said portion of said insulating layer. Channel layer formation method. A substrate including a gate electrode layer therein;
A gate insulating layer on the substrate;
A source electrode layer and a drain electrode layer spaced apart from each other on the gate insulating layer;
A source extension layer and a drain extension layer extending from the source electrode layer and the drain electrode layer to face each other; And
And an electroplated metal channel layer disposed between the source extension layer and the drain extension layer. 31. The method of claim 30,
And the source extension layer, the drain extension layer and the metal channel layer are made of the same metal. 31. The method of claim 30,
And the distance between the source extension layer and the drain extension layer is shorter than the distance between the source electrode layer and the drain electrode layer. 31. The method of claim 30,
And an upper gate insulating layer and an upper gate electrode layer disposed on the metal channel layer.

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