KR101179275B1 - Apparatus and method for management of memory - Google Patents

Abstract

PURPOSE: A memory management device and a method thereof are provided to efficiently and stably use a restricted cache memory resource and to setup a block group between a main memory and a cache memory. CONSTITUTION: A memory group setting unit(151) gives a group ID to each group. A page cache setting unit(152) sets up a plurality of blocks to a page cache. A memory mapping unit(153) maps a block of a virtual memory of each process. A page cache managing unit(154) selects a block of the page cache as the buffer in a data access command process. The page cache managing unit gives the group ID according to a selection sequence of the block.

Description

Memory management apparatus and method {APPARATUS AND METHOD FOR MANAGEMENT OF MEMORY}

The present invention relates to a memory management apparatus and method.

In a virtualized environment of computer systems, a virtual machine behaves as if it uses independent hardware. When processing data in such a virtual environment, the physical address of the virtual machine (that is, a guest) is converted into a host physical address, and data processing by the converted host physical address is processed through a cache area.

However, in a virtual environment, data processing through a plurality of virtual machines may occur simultaneously or consecutively, and an error may occur in the process of converting each virtual machine's physical address into a host physical address. In addition, even after the physical address of the virtual machine is converted to a host physical address, data processing according to a plurality of host physical addresses is concentrated in a specific area of the cache, thereby causing a cache miss.

Therefore, in the related art, a method of preventing a cache miss by previously mapping a host physical address for each physical address of a virtual machine and mapping a cache region for each host physical address in advance has been proposed.

However, in the conventional cache miss prevention scheme, the mapping scheme between the shared region configured in the host physical address and the physical address of the virtual machine and the mapping scheme between the shared region and the cache are not considered. For reference, the shared area is a storage area shared by a plurality of virtual machines in physical memory. In this case, as in the conventional cache miss prevention scheme, when the shared region in the host physical address is also mapped to the cache region in advance, an error occurs when a plurality of virtual machines share a specific region among the shared regions. That is, since the physical addresses of the virtual machines sharing and using the specific region are different from the host physical addresses mapped in advance, an error occurs in the use of the cache mapped to each host physical address or a waste occurs in the use of the cache. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and to provide a memory management apparatus and method capable of efficiently using a limited cache memory resource.

In addition, the present invention is to provide a memory management apparatus and method capable of efficiently managing a shared area set in the main memory in order to increase the data processing speed of a plurality of virtual machines in a virtualized environment.

Memory management apparatus according to an aspect of the present invention for achieving the above technical problem, grouping the blocks of the cache memory and the main memory into a plurality of groups according to a predetermined classification criteria, the cache memory and the main memory of the A memory group setting unit for assigning a group identification ID for each group so that groups match each other; A page cache setting unit configured to set a plurality of blocks in the main memory as a page cache that operates as a data processing buffer with a sub memory; A memory mapping unit for mapping a block of a plurality of process-specific virtual memories with the remaining blocks of the main memory except the block set as the page cache; And a page cache management unit that selects one block of the page cache as the buffer when processing the data access command for each process, and sequentially assigns the group identification ID based on the type according to the order in which the one block is selected. .

According to another aspect of the present invention, a memory management method includes classifying blocks of a cache memory and a main memory into a plurality of groups according to preset classification criteria, assigning a group identification ID to each of the groups, and providing a plurality of blocks in the main memory. Setting a block of to a page cache operating as a buffer for data processing with the sub memory; Mapping blocks of a plurality of process-specific virtual memories to the remaining blocks of the main memory except for the block configured as the page cache; And selecting one block in the page cache and assigning the group identification ID to the selected one block when the data access command for each process occurs, wherein the plurality of groups are arranged in the order in which the one block is selected. The identification ID is assigned sequentially based on the type.

According to the above-described problem solving means of the present invention, by setting a block group matching each other between the main memory and the cache memory, there is an effect that can use the limited cache memory resources efficiently and stably.

According to the problem solving means of the present invention, the shared use of the page caches of a plurality of processes by sequentially assigning the types of block groups for data processing according to the order in which the pages of the page cache area set in the main memory are selected. It is possible to prevent a cache miss that may occur at the time, and to increase the cache usage efficiency by allowing the cache memory to be used evenly for each type of block group.

1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention.
2 is a block diagram illustrating a configuration of a memory management apparatus according to an embodiment of the present invention.
3 is a structural diagram of address patterns of a cache memory and a main memory for explaining a page coloring scheme according to an embodiment of the present invention.
4A is a diagram for describing a page coloring method according to an embodiment of the present invention.
4B illustrates a page cache coloring scheme according to an embodiment of the present invention.
5 is a flowchart illustrating a memory management method according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention.

2 is a block diagram illustrating a configuration of a memory management apparatus according to an embodiment of the present invention.

First, as shown in FIG. 1, the computer system 100 according to an embodiment of the present invention may include a central processing unit 110, a cache memory 120, a main memory 130, a sub memory 140, and a memory. The management device 150 is included.

The central processing unit 110 performs overall computational processing according to the operating system of the computer system 100. In this case, a plurality of virtual machines are driven on the computer system according to an embodiment of the present invention, and the central processing unit 110 performs arithmetic processing generated between the host operating system and the guest operating system (ie, a virtual machine). do. For reference, each guest in accordance with one embodiment of the present invention operates as a process.

Specifically, the central processing unit 110 processes a data access command for each process, and reads or writes data from the main memory 130 during data access command processing.

In this case, the central processing unit 110 may store the data such as frequently generated instructions and data in the cache memory 120 temporarily and call them when necessary for high speed data processing, thereby enabling high speed arithmetic processing.

Meanwhile, each of the storage spaces of the cache memory 120, the main memory 130, and the sub memory 140 is divided and managed in units of blocks. In an embodiment of the present invention, the blocks may have a predetermined size according to an operating system. Divided into 'pages'.

The cache memory 120 is a buffer for temporarily storing data processed between the central processing unit 110 and the main memory 130, and is frequently used to access data on the main memory 130 of the central processing unit 110. The data is temporarily stored and provided at each call of the central processing unit 110.

In detail, the cache memory 120 allocates a block to temporarily store data processed (that is, write or read) from a block of the main memory 130 during a data access process of the central processing unit 110.

The blocks of the cache memory 120 are mapped to the blocks of the main memory 130, and the blocks allocated in advance are allocated to the corresponding blocks of the main memory 130 when the block is allocated. Accordingly, the cache memory 120 is equally allocated to each group when allocating blocks for data processing, thereby preventing cache misses and efficiently using cache memory resources.

Blocks of the cache memory 120 according to an embodiment of the present invention are grouped through the memory management apparatus 150 and matched with the block groups of the main memory 130 for each group.

The main memory 130 is a memory device capable of directly exchanging data with the central processing unit 110. The main memory 130 acquires data (data such as programs and data) stored in the sub memory 140 when a process is executed. 110 and provide for execution.

The main memory 130 according to an embodiment of the present invention is mapped in block units with virtual memory of virtual machines (ie, guests) on the computer system 100. In this case, the main memory 130 reads data from a block of virtual memory when processing a data access command of each process (that is, a guest), and stores the data in a block of the main memory 130 previously mapped to the block of the virtual memory. Write the read processed data.

The sub memory 140 is a storage device for storing data outside the central processing unit 110 and is relatively slower than the main memory 130 and permanently stores a large amount of data. Examples include disks and the like.

At least a portion of the sub memory 140 according to an exemplary embodiment of the present invention is used as a physical memory of the virtual memory, and the blocks of the sub memory 140 used as the virtual memory are the main memory 130. Mapped to blocks.

The memory management apparatus 150 performs memory management for processing data between the cache memory 120, the main memory 130, and the sub memory 140 in order to efficiently use the cache memory 120 and the main memory 130. .

Specifically, as shown in FIG. 2, the memory management apparatus 150 according to an embodiment of the present invention may include a memory group setting unit 151, a page cache setting unit 152, a memory mapping unit 153, and a page cache management unit ( 154).

The memory group setting unit 151 groups the cache memory 120 and the main memory 130 into groups each including a plurality of blocks, and assigns a group identification ID for each group. In this case, the memory group setting unit 151 assigns a group identification ID to match each group of the cache memory 120 and the main memory 130 with each other.

For reference, in the exemplary embodiment of the present invention, the grouping process is referred to as 'page coloring process'. That is, a group identification ID given to each group of the cache memory 120 and the main memory 130 is defined as 'color' as a group type, and pages included in a specific color group of the main memory 130 are the specific color. Data is processed using the pages of the color group in cache memory 120 of the same color as the group.

In detail, the memory group setting unit 151 colors the pages of the cache memory 120 and the main memory 130 according to a preset classification criterion. In this case, the memory group setting unit 151 may set the classification criteria by using the address pattern of the cache memory 120 and the address pattern of the main memory 130.

For example, FIG. 3 is a structural diagram of address patterns of a cache memory and a main memory for explaining a page coloring scheme according to an embodiment of the present invention.

In FIG. 3, the cache memory 120 has a capacity of 4 MB, 16-way set associative, and 64B offset. At this time, the cache memory 120 has 4096 cache indexes, and 12 bits are used to represent the cache index. Accordingly, as shown in FIG. 3, the lower 6 bits of the physical page number on the address pattern of the physical memory of the main memory 130 and the cache memory (L2 Cache) are shown. The upper six bits of the Cache Set Index on the address pattern of 120 correspond.

In this case, the memory group setting unit 151 sets the classification criteria based on a bit pattern difference between the address patterns of the cache memory 120 and the main memory 130. That is, in FIG. 3, 64 colors are set based on a value of 6 bits corresponding to a cache index bit of the cache memory 120 and a physical page number bit of the main memory 130. Therefore, each block (ie, page) of the cache memory 120 and the main memory 130 is given a color of any one of the above-described color types.

For reference, since the cache memory 120 illustrated in FIG. 3 is 16-way, up to 16 pages for the same color type may exist in the cache memory 120. As such, since the number of pages having the same color on the cache memory 120 is determined, the color of the cache memory 120 is equally used in the data processing of each page of the main memory 130 to efficiently use the resources of the cache memory 120. Can be used.

The page cache setting unit 152 sets a page having a predetermined size (or number) among the pages of the main memory 130 as a page cache area which is a temporary storage area for data processing with the virtual memory. In this case, the page cache setting unit 152 sets a plurality of pages among the pages of the main memory 130 in which the page coloring process with the cache memory 120 is completed, as a page cache.

Meanwhile, pages of the main memory 130 are mapped to pages of virtual memory of a plurality of processes, respectively, and the page cache area is a temporary storage area shared and used by a plurality of processes. Therefore, when a plurality of processes share and use a specific page of the page cache while each page of the page cache is previously colored, a coloring error occurs in the page cache area.

For example, when processing a data access command of the first process, the first data is read from a specific page of the first process (that is, a page of the virtual memory) in the sub memory 140, and then the first page of the page cache is read. 1 Data can be write processed. Then, when the second process reads the first data stored in the first page, the coloring of the first page is broken. That is, the page coloring of the first page is broken because the first page is page colored in the first data processing by the first process and the page colored color in the second data processing by the second process.

Therefore, the page cache setting unit 152 releases the color setting for the pages set as the page cache. For reference, the pages of the page cache are colored by the page cache manager 154.

The memory mapping unit 153 maps the blocks of the virtual memory for each process (ie, pages) except for the page cache set in the main memory 130. In this case, the memory mapping unit 153 sequentially maps the blocks of the virtual memory 130 according to the colors of the blocks of the main memory 130 so that the colors set for the blocks of the main memory 130 are uniformly used.

For example, FIG. 4A is a diagram for describing a page coloring scheme according to an embodiment of the present invention.

As shown in FIG. 4A, each page of the virtual memory Process A of the process A and the physical memory of the main memory 130 is mapped to correspond to each page, and is mapped to each page of the main memory 130. The pages of virtual memory of process A are mapped to the pages of main memory 130 so that the applied colors are used evenly. As such, the colors of the virtual memory and the main memory 130 are uniformly mapped, so that the pages of the cache memory 120 and the pages of the main memory 140 are equally divided according to color types as shown in FIG. 4A. Is mapped.

The memory mapping unit 153 creates and stores a matching table by matching each block of the virtual memory with each address of the block of the main memory 130 mapped. Thereafter, the memory mapping unit 153 detects the physical address of the main memory 130 matched to the address of the virtual memory from the matching table and provides the same to the central processing unit 110 when the data access command is processed for each process.

The page cache manager 154 selects a page of a page cache as a data processing buffer when processing a data access instruction for each process, and sequentially assigns colors by types according to the order in which the pages of the page cache are selected.

In detail, the page cache manager 154 selects an unused page among a plurality of pages included in the page cache. For reference, the data read from the virtual memory (that is, the sub memory) is written to the selected page.

For example, FIG. 4B is a diagram for describing a page cache coloring scheme according to an embodiment of the present invention.

As shown in FIG. 4B, a page cache area is set in a physical memory of the main memory 130. The remaining pages, except for the page of the virtual memory process A of the process A and the page cache area of the main memory 130, are mapped to each other and are page colored.

4B illustrates a state in which data of a page of a kernel area or a user area of a virtual memory Process A (that is, a sub memory) of a process A is read or written to a page of a page cache area. At this time, the data stored in the page of the virtual memory of the process A (Virtual Memory Process A) is written to the page mapped in advance of the page of the main memory 130 through the page cache area, or the virtual memory of the process A ( It can be written to another page in Virtual Memory Process A).

In this case, as shown in FIG. 4B, the page cache manager 154 sequentially processes the data of the page of the virtual memory of the process A to the page of the page cache area, and then sequentially colors based on the type. To perform the coloring process of the page cache.

In addition, the page cache manager 154 provides the central processing unit 110 with the information of the color assigned to one page of the page cache when processing the data access command of the corresponding process. In this case, the central processing unit 110 processes the corresponding data through the page of the cache memory 120 of the same color as the provided color information.

Hereinafter, a memory management method on the computer system 100 according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 5.

5 is a flowchart illustrating a memory management method according to an embodiment of the present invention.

First, a page coloring process is performed on blocks of a cache memory and a main memory (S510).

Specifically, each block of the cache memory and the physical memory is classified into a plurality of groups based on a relationship between the address pattern of the cache memory and the address pattern of the physical memory (for example, a bit pattern difference), and the blocks within the same group are classified into a plurality of groups. The same color (ie, group identification ID). At this time, each group of the cache memory and the physical memory correspond to groups having the same color.

Next, a page cache area is set in the main memory (S520).

Specifically, a block having a predetermined size (or number) among the blocks in the main memory is set as a page cache area, and the page cache area operates as a buffer shared by a plurality of processes.

Thereafter, memory mapping is performed between the main memory and the virtual memory (S530).

At this time, the pages of the main memory, other than the page cache, are mapped to the pages of the virtual memory for each of the plurality of processes.

Then, when a data access instruction for each process is generated, a coloring process for the page cache is performed (S540).

 Specifically, when an access process for data previously stored in a page of virtual memory (ie, a sub-memory) occurs, an arbitrary page in the page cache is selected as a buffer to perform data processing for data to be accessed, and the selected page Colors pages in the cache.

At this time, the types of colors are sequentially applied according to the order in which the pages of the page cache are selected. That is, the pages of the page cache are selected according to the order in which the data access commands are issued by a plurality of processes, and each selected page is given a different color. For example, the currently selected page is given a color different from the color given to the previously selected page. By applying the color types to each selected page sequentially and assigning the colors, the colors are evenly applied to increase the cache usage efficiency.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

100: virtualization unit 110: central processing unit
120: cache memory 130: main memory
140: sub memory 150: memory management device

Claims (11)

In the memory management device of a computer system,
A memory group setting unit for grouping blocks of a cache memory and a main memory into a plurality of groups according to a predetermined classification criterion, and assigning a group identification ID for each group so that the groups of the cache memory and the main memory match each other;
A page cache setting unit configured to set a plurality of blocks in the main memory as a page cache that operates as a data processing buffer with a sub memory;
A memory mapping unit for mapping a block of a plurality of process-specific virtual memories with the remaining blocks of the main memory except the block set as the page cache; And
And a page cache manager which selects one block of the page cache as the buffer and sequentially assigns the group identification ID according to the order in which the one block is selected when processing the data access command for each process. The method of claim 1,
The memory group setting unit,
And setting the classification criteria based on a bit pattern difference between the cache memory and the address pattern of the main memory. The method of claim 1,
The memory mapping unit,
Mapping a physical address of the main memory to each address of the virtual memory to store a matching table,
And processing the data access command by detecting a physical address of the main memory that matches the address of the virtual memory from the matching table when the data access command is processed. The method of claim 1,
The page cache management unit,
And providing a group identification ID assigned to the one block to a central processing unit for processing the data access command so that a block in the group of the cache memory corresponding to the provided group identification ID is selected. The method according to any one of claims 1 to 4,
The page cache management unit,
And an unused block among the blocks in the page cache as the one block when the data access command is processed. The method of claim 1,
The page cache management unit,
When the group identification ID is granted, a group identification ID different from the group identification ID given to the previous block selected immediately before the currently selected block is assigned to the currently selected block.
And a memory management device for sequentially selecting the types. In the memory management method of a computer system,
(a) classifying the blocks of the cache memory and the main memory into a plurality of groups according to preset classification criteria, and assigning group identification IDs to the groups;
(b) setting a plurality of blocks in the main memory as a page cache which operates as a buffer for data processing with a sub memory;
(c) mapping blocks of a plurality of process-specific virtual memories to the remaining blocks of the main memory except for the block set as the page cache; And
(d) selecting one block in the page cache and assigning the group identification ID to the selected one block when the data access command for each process occurs;
In the step (d)
And sequentially assigning the plurality of group identification IDs based on a type in the order in which the one block is selected. The method of claim 7, wherein
In the step (a)
And setting the classification criteria based on a bit pattern difference between an address pattern of the cache memory and an address pattern of the main memory. The method of claim 7, wherein
In the step (a)
And assigning the group identification ID so that the groups of the cache memory and the main memory match each other. The method of claim 7, wherein
After the step (d)
And writing data read-processed from the sub memory or the main memory to the one block according to the data access command for each process. The method of claim 7, wherein
After the step (d)
And allocating an unused block among the blocks in the group of the cache memory matching the group identification ID assigned to the one block as a data processing block when processing the data access command for each process.

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