KR101179078B1 - Method of forming a metal wiring in a semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a metal wiring of a semiconductor device, has the effect of improving the characteristics of the device by removing defects in the copper electroplating process and improving the buried characteristics.

According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: forming an interlayer insulating film having an opening having a predetermined shape on a semiconductor wafer; Sequentially forming a diffusion barrier layer and a seed layer on the entire structure surface including the openings; And forming a copper layer on the seed layer by the electroplating process so as to fill the opening, wherein the electroplating process is performed by varying the current wave shape and the current distribution for each wafer position.

Metal wiring, copper, electroplating

Description

Method of forming a metal wiring in a semiconductor device

1A to 1D are cross-sectional views illustrating processes of forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

2 to 11 are views for explaining various electroplating methods according to the current wave form according to the present invention,

2 is a diagram showing a multi-current DC plating scheme.

3 is a view showing a pulsed reverse plating scheme.

4 is a diagram showing a pulse on pulse plating method.

5 shows a three-step plating method.

6 is a diagram showing a direct 4-step plating method.

7 shows a high duplex pulse plating scheme.

8 shows a low duplex pulse plating scheme.

9 is a view showing a unipolar pulse plating method.

10 is a diagram showing a step 1 unipolar pulse plating method.

11 is a diagram showing a step 2 unipolar pulse plating method.

Description of the Related Art

100 semiconductor wafer 101 interlayer insulating film

102: dual damascene pattern 103: diffusion barrier layer

104: seed layer 105: copper layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming metal wirings in semiconductor devices, and more particularly, to a method of forming metal wirings in semiconductor devices capable of improving device characteristics by removing defects in copper electroplating processes and improving embedding characteristics.

As the integration of devices increases, there is a problem in driving a device such as an RC delay. As a method of improving the device, copper having a lower resistivity than conventional aluminum is used as a metal wiring material. Research into this low dielectric constant insulating film is in progress. In the process of metal wiring, rather than directly etching copper having a fine wiring structure, an insulating film is first formed, a single or dual damascene pattern is formed in the insulating film, and then copper is embedded in the pattern. In the process of performing a CMP.

On the other hand, when copper is in direct contact with the general insulating film, deterioration of device characteristics occurs due to the diffusion of copper, and a diffusion barrier layer is essentially applied between the insulating film and the copper wiring to prevent diffusion of copper. Currently, TaN, which is widely applied as a diffusion barrier layer, is formed by physical vapor deposition (PVD), which has a limited step coverage characteristic. As the degree of integration increases, a copper seed layer is formed. There is a problem that the embedding characteristics in the process or copper electroplating process is lowered. In particular, defects such as voids and overplating phenomena generated during the electroplating process adversely affect the characteristics of the device.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to remove metal defects in the copper electroplating process and to improve the embedding characteristics, thereby forming metal wirings of semiconductor devices capable of improving device characteristics. To provide a method.

Metal wiring forming method of a semiconductor device according to the present invention for achieving the above object,

Forming an interlayer insulating film having an opening of a predetermined shape on the semiconductor wafer;

Sequentially forming a diffusion barrier layer and a seed layer on the entire structure surface including the openings; And

Forming a copper layer on the seed layer by the electroplating process to fill the opening, characterized in that the electroplating process is performed by varying the current wave shape and current distribution for each wafer position.

Here, the electroplating process is characterized by using a multi-current DC plating method.

The electroplating process is characterized by using a pulsed reverse plating method.

In addition, the electroplating process is characterized by using a pulse on pulse plating method.

In addition, the electroplating process is characterized by using a three-step plating method.

In addition, the electroplating process is characterized in that using a direct four-step plating method.

In addition, the electroplating process is characterized by using a high duplex pulse plating method.

In addition, the electroplating process is characterized by using a low duplex pulse plating method.

In addition, the electroplating process is characterized by using a unipolar pulse plating method.

In addition, the electroplating process is characterized in that using a step 1 unipolar pulse plating method.

In addition, the electroplating process is characterized in that using the step 2 unipolar pulse plating method.

In addition, the electroplating process is characterized in that to maintain an average wafer current density of 0.1 to 50 mA / ㎠.

In addition, the electroplating process is -300 to 40 ℃ using an electroplating solution containing 1 to 200 g / liter H ₂ SO ₄ , 1 to 500 ppm HCl and 0.05 to 20 ml / liter organic additive It is characterized by performing at a temperature.

In addition, as the organic additive, cross linked polyimine, sulfopropylated polyethylene imine, [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether ([( 3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether), and mixtures thereof.

In addition, the organic additive is characterized in that it is used in the range of 0.05 to 20 ml / L.

Further, as the organic additive, potassium salt and SPSA (Sulfo-) in [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether ([(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether) Propyl-Sulfide-Acid) is used to add one or more of the features.

Further, the above [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether ([(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether), potassium salt and SPSA (Sulfo-Propyl-Sulfide- Acid) is characterized in that each used in the range of 0.05 to 20 ml / L.

In addition, as the organic additive, any one or more of SPSA (Sulfo-Propyl-Sulfide-Acid), beta-naphtol, and alkoxylated (alkoxylated) may be added to the cross linked polyimine. It is characterized by using.

In addition, the cross linked polyimine (Sulfo-Propyl-Sulfide-Acid), beta-naphtol (beta-naphtol) and alkoxylated (alkoxylated) are used in the range of 0.05 to 20 ml / L, respectively. It is characterized by.

In addition, the bath temperature of the electroplating process is -20 to 50 ℃, the flow rate of the bath is characterized in that 1 to 10 gal / min.

In addition, the electroplating process is characterized in that the rotation of the wafer is performed in a combination of clockwise and counterclockwise direction.

In addition, after the copper layer is formed by the electroplating process,

Performing a hydrogen reduction heat treatment on the copper layer; And

CMP the resultant until the surface of the interlayer insulating film is exposed.

In addition, the hydrogen reduction heat treatment, characterized in that carried out at a temperature of room temperature to 350 ℃ in a hydrogen reduction atmosphere.

In addition, the hydrogen reducing atmosphere is characterized by using any one of a H ₂ gas, a mixture of Ar gas, H ₂ gas in the hydrogen mixed gas, and N ₂ gas mixture of hydrogen gas mixed in H ₂ gas.

In addition, before performing the hydrogen reduction heat treatment,

Spin and rinse dry the copper layer is characterized in that it further comprises.

The opening may be any one of a dual damascene pattern, a via hole, and a trench.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout.

1A to 1D are cross-sectional views illustrating processes of forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention, and FIGS. 2 to 11 illustrate various electroplating methods according to current wave forms according to the present invention. It is a figure for demonstrating.

As shown in FIG. 1A, an interlayer insulating film 101 is formed on a semiconductor wafer 100 that has undergone various processes for forming a semiconductor device. The interlayer insulating film 101 is preferably formed of an insulating material having a low dielectric constant (low k).

Subsequently, a portion of the interlayer insulating layer 101 is etched to form an opening of a predetermined shape, for example, a dual damascene pattern 102 that exposes a portion of the wafer 100. Here, an example in which the subsequent process is performed by forming the dual damascene pattern 102 in the interlayer insulating film 101 will be described as an example. However, a via hole (not shown) or a trench (not shown) may be formed in the interlayer insulating film 101. The present invention can also be applied when the process proceeds. Next, a cleaning process is performed to remove a native oxide film or contaminants formed on the surface of the wafer 100 exposed by the dual damascene pattern 102.

1B, a diffusion barrier layer 103 and a copper seed layer 104 are sequentially formed on the entire structure surface including the dual damascene pattern 102. The diffusion barrier layer 103 may include a physical vapor deposition (PVD) TiN film, a chemical vapor deposition (CVD) TiN film, and a metal organic chemical vapor deposition (MOCVD) TiN film. At least one of PVD Ta, PVD TaN, PVD TiAlN, PVD TiSiN, PVD TaSiN, CVD Ta, CVD TaN, CVD WN, CVD TiAlN, CVD TiSiN and CVD TaSiN It is preferable to form.

Next, as shown in FIG. 1C, a copper layer 105 is formed on the copper seed layer 104 by an electroplating process to completely fill the dual damascene pattern 102. In this case, the electroplating process for forming the copper layer 105 is performed by varying the current wave form and the current distribution for each wafer position. For example, the electroplating process may include a multi current DC plating method, a pulsed reverse plating method, a pulse on pulse plating method, and a three step plating method (3). step plating method, direct 4 step plating method, high duplex pulse plating method, low duplex pulse plating method, unipolar pulse plating method Method, step 1 unipolar pulse plating method, step 2 unipolar pulse plating method, or the like.

2 is a diagram showing a multi-current DC plating method, FIG. 3 is a diagram showing a pulsed reverse plating method, FIG. 4 is a diagram showing a pulse on pulse plating method, and FIG. 5 is a diagram showing a three step plating method. 6 is a diagram showing a direct four step plating method, FIG. 7 is a diagram showing a high duplex pulse plating method, FIG. 8 is a diagram showing a low duplex pulse plating method, and FIG. 9 is a unipolar pulse plating method. 10 is a diagram showing a step 1 unipolar pulse plating method, and FIG. 11 is a diagram showing a step 2 unipolar pulse plating method.

First, in the case of using the multi-current DC plating method, as shown in FIG. 2, a forward current is supplied at 1 A to 10 A for 0.1 ms to 100 sec, and then off time for 0.1 ms to 10 sec. The copper layer 105 may be formed by repeating a process having an off time 2 to 10 times.

When using the pulsed reverse plating method, as shown in FIG. 3, the forward current is supplied at 1 A to 20 A for 0.1 sec to 200 sec, and has an off time for 1 ms to 30 ms. The reverse current may be supplied at 1 A to 10 A for 5 ms to 50 sec, and then the process of having an off time for 1 ms to 30 ms may be repeated 2 to 10 times to form the copper layer 105. .

In the case of using the pulse on pulse plating method, as shown in FIG. 4, first, the forward current is supplied at 0.1 A to 3 A for 0.1 sec to 10 sec, and the forward current is 0.1 A to 5 A at 0.1 sec. Feed for 10 sec. Then, the following process, that is, forward current is supplied at 0.1 A to 10 A for 0.1 sec to 10 sec, then forward current is supplied at 0.1 A to 20 A for 0.1 sec to 10 sec, and again forward current is 0.1 A After supplying to 10 A for 0.1 sec to 10 sec, the process having an off time for 0.1 ms to 100 sec may be repeated 2 to 10 times to form the copper layer 105.

In the case of using a three-step plating method, as shown in FIG. 5, first, the forward current is supplied at 0.1 A to 3 A for 0.1 sec to 10 sec, and the forward current is 0.1 A to 10 A at 0.1 sec to 10 A. The copper layer 105 may be supplied by supplying for 20 sec, and then supplying a forward current at 0.1 A to 20 A for 0.1 sec to 20 sec.

In the case of using the direct 4-step plating method, as shown in FIG. 6, first, the forward current is supplied at 0.1 A to 3 A for 0.1 sec to 10 sec, and the forward current is 0.1 A to 10 A at 0.1 sec. To 20 sec, and then forward current is supplied at 0.1 A to 20 A for 0.1 sec to 10 sec, and forward current is supplied at 0.1 A to 30 A for 0.1 sec to 20 sec to provide copper layer 105 Can be formed.

In the case of using the high duplex pulse plating method, as shown in FIG. 7, first, the forward current is supplied at 0.1 A to 10 A for 0.1 sec to 10 sec, and the forward current is 0.1 A to 20 A at 0.1 sec. Feed for 10 sec. Then, the following procedure, that is, forward current is supplied at 0.1 A to 40 A for 0.1 sec to 10 sec, then has an off time for 0.1 ms to 100 sec, and again the forward current is 0.1 A to 30 A at 0.1 sec to After supplying for 30 sec, the process having an off time for 0.1 ms to 100 sec may be repeated 2 to 10 times to form the copper layer 105.

In the case of using the low duplex pulse plating method, as shown in FIG. 8, first, the forward current is supplied at 0.1 A to 10 A for 0.1 sec to 10 sec, and the forward current is 0.1 A to 20 A at 0.1 sec. Feed for 10 sec. Then, the following process, that is, forward current is supplied at 0.1 A to 30 A for 0.1 sec to 10 sec, then has an off time for 0.1 ms to 100 sec, and again the forward current is 0.1 A to 40 A at 0.1 sec to After supplying for 30 sec, the process having an off time for 0.1 ms to 100 sec may be repeated 2 to 10 times to form the copper layer 105.

In the case of using the unipolar pulse plating method, as shown in FIG. 9, first, the forward current is supplied at 0.1 A to 10 A for 0.1 sec to 10 sec, and the forward current is 0.1 A to 20 A at 0.1 sec. Feed for 10 sec. Then, the following process, that is, forward current is supplied to 0.1 A to 30 A for 0.1 sec to 10 sec, and the process having an off time for 0.1 ms to 100 sec is repeated 2 to 10 times to the copper layer 105 Can be formed.

In the case of using the step 1 unipolar pulse plating method, as shown in FIG. 10, first, a forward current is supplied at 0.1 A to 10 A for 0.1 sec to 10 sec, and then an off time is performed for 0.1 ms to 10 sec. Eggplant repeat the process 2 to 10 times. Subsequently, the forward current was supplied at 0.1 A to 20 A for 1 sec to 20 sec, the off time was 0.1 ms to 10 sec, and the forward current was again supplied at 0.1 A to 30 A for 1 sec to 50 sec. Layer 105 may be formed.

In the case of using the step 2 unipolar pulse plating method, as shown in FIG. 11, first, a forward current is supplied at 0.1 A to 10 A for 0.1 sec to 20 sec. Then, the following process, that is, forward current is supplied at 0.1 A to 20 A for 0.1 sec to 10 sec, and then a process having an off time for 0.1 ms to 10 sec is repeated 2 to 10 times. Then, the forward current may be supplied again at 0.1 A to 30 A for 1 sec to 50 sec to form the copper layer 105.

As described above, during the electroplating process, the average wafer current density is maintained at 0.1 to 50 mA / cm 2, and the current distribution is changed for each wafer position to improve the uniformity of the electroplating layer. . In addition, the electroplating process is -300 to 40 ℃ using an electroplating solution containing 1 to 200 g / liter H ₂ SO ₄ , 1 to 500 ppm HCl and 1 to 20 ml / liter organic additive At a temperature of Here, as an organic additive included in the electroplating solution, we use cross linked polyimine, which is wet, or use sulfopropylated polyethylene imine, or [(3-sulfur). Poppropoxy) -polyalkoxy] -beta-naphthyl ether ([(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether) may be used, or a mixture of the above materials may be used. Such organic additives are preferably used in the range of 0.05 to 20 ml / L.

In addition, as the organic additive, in [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether in potassium salt and Sulfa-Propyl-Sulfide-Acid (SPSA) instead of the above-mentioned materials. Any one or more may be added and used, wherein [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether, potassium salt and SPSA are each used in the range of 0.05 to 20 ml / L. desirable. In addition, as the organic additive, one or more of SPSA, beta-naphtol and alkoxylated may be added to the crosslinked polyimine, wherein the crosslinked polyimine, SPSA, beta- Naphthol and alkoxides are preferably used in the range of 0.05 to 20 ml / L, respectively.

On the other hand, the bath (bath) temperature of the electroplating process is in the range of -20 to 50 ℃, the flow rate of the bath (flow rate) is 1 to 10 gal / min. In addition, the electroplating process is performed in a rotational combination of clockwise and counterclockwise direction under the condition of the rotational speed of the wafer 10 to 500 rpm.

As described above, in the present invention, organic additives such as crosslinked polyimines, sulfopropylated polyethylene imines, and [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether and the like according to the current wave form By applying various electroplating methods, defects such as voids and overplating phenomena generated in the copper electroplating process can be eliminated, and the buried characteristics can be improved.

Next, spin and rinse dry treatment of the copper layer 105 formed as described above is performed under conditions in which the rotational speed of the wafer is 100 to 2,500 rpm using pure water (DI water).

After that, by performing the hydrogen reduction thermal treatment to the copper layer 105, change the morphology of the grain (grain morphology). The hydrogen reduction heat treatment is performed at a temperature of room temperature to 350 ° C. in a hydrogen reduction atmosphere for substantially 3 hours or less. Hydrogen reducing atmosphere at this time is mixing the case of using only the H ₂ gas, in the case of using the hydrogen mixed gas a mixture of Ar gas to less than 95% of the H ₂ gas, and N ₂ gas to H ₂ gas to 95% or less In case of using one hydrogen mixed gas.

Then, as shown in FIG. 1D, the resultant is subjected to chemical mechanical polishing (CMP) until the surface of the interlayer insulating film 101 is exposed to form copper metal wiring. After the CMP process, post-cleaning may be performed.

The present invention is not limited to the above-described embodiments, but can be variously modified and changed by those skilled in the art, which should be regarded as included in the spirit and scope of the present invention as defined in the appended claims. something to do.

As described above, according to the method for forming metal wirings of the semiconductor device according to the present invention, crosslinked polyimine, sulfopropylated polyethylene imine, and [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether By applying a variety of electroplating methods according to the organic additives such as the current wave form and the like, it is possible to eliminate defects in the copper electroplating process and improve the buried properties. Therefore, the present invention can contribute to improvement of the degree of integration and characteristics of the device.

Claims (26)

Forming an interlayer insulating film having openings on the semiconductor wafer; Sequentially forming a diffusion barrier layer and a seed layer on the entire structure surface including the openings; And Forming a copper layer on the seed layer by an electroplating process to fill the opening; The electroplating process is carried out using an electroplating solution containing an organic additive; As the organic additive, potassium salt and SPSA (Sulfo-Propyl-) in [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether ([(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether) Method for forming a metal wiring of the semiconductor device, characterized in that any one or more of (Sulfide-Acid) is added and used. The method of claim 1, The electroplating process is a metal current forming method of a semiconductor device, characterized in that using a multi-current DC plating method. The method of claim 1, The electroplating process is a metal wire forming method of a semiconductor device, characterized in that using a pulsed reverse plating method. The method of claim 1, The electroplating process is a metal wiring forming method of a semiconductor device, characterized in that using a pulse on pulse plating method. The method of claim 1, The electroplating process is a metal wiring forming method of a semiconductor device, characterized in that using a three-step plating method. The method of claim 1, The electroplating process is a metal wire forming method of a semiconductor device, characterized in that using a direct four-step plating method. The method of claim 1, The electroplating process is a metal wiring forming method of a semiconductor device, characterized in that using a high duplex pulse plating method. The method of claim 1, The electroplating process is a metal wiring forming method of a semiconductor device, characterized in that using a low duplex pulse plating method. The method of claim 1, The electroplating process is a metal wiring forming method of a semiconductor device, characterized in that using the unipolar pulse plating method. The method of claim 1, The electroplating process uses a step 1 unipolar pulse plating method. The method of claim 1, The electroplating process uses a step 2 unipolar pulse plating method. The method of claim 1, The electroplating process is a method for forming a metal wire of the semiconductor device, characterized in that to maintain an average wafer current density of 0.1 to 50 mA / ㎠. The method of claim 1, The electroplating process is carried out at a temperature of -300 to 40 ℃ using an electroplating solution containing 1 to 200 g / liter H ₂ SO ₄ , 1 to 500 ppm HCl and 0.05 to 20 ml / liter organic additive A metal wiring forming method of a semiconductor device, characterized in that performed. The method of claim 13, As the organic additive, cross linked polyimine, sulfopropylated polyethylene imine, [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether ([(3- sulfopropoxy) -polyalkoxy] -beta-naphthyl ether), and a mixture thereof. The method of claim 13, The organic additive is a metal wiring forming method of a semiconductor device, characterized in that used in the range of 0.05 to 20 ml / L. delete The method of claim 1, The [(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether ([(3-sulfopropoxy) -polyalkoxy] -beta-naphthyl ether), potassium salt and SPSA (Sulfo-Propyl-Sulfide-Acid) The metal wiring forming method of a semiconductor device, characterized in that used in the range of 0.05 to 20 ml / L, respectively. The method of claim 1, As the organic additive, any one or more of SPSA (Sulfo-Propyl-Sulfide-Acid), beta-naphtol, and alkoxylated (alkoxylated) is added to the cross linked polyimine. A metal wiring forming method for a semiconductor device, characterized in that. The method of claim 18, The cross linked polyimine (Sulfo-Propyl-Sulfide-Acid), beta-naphtol (alkoxylated) and alkoxylated (alkoxylated) are each used in the range of 0.05 to 20 ml / L. A method of forming metal wirings in a semiconductor device. The method of claim 1, The bath temperature of the said electroplating process is -20-50 degreeC, and the flow velocity of a bath is 1-10 gal / min, The metal wiring formation method of the semiconductor element characterized by the above-mentioned. The method of claim 1, The electroplating process is a method of forming a metal wire of a semiconductor device, characterized in that the rotation of the wafer in a combination of a clockwise and counterclockwise direction. The method of claim 1, After the copper layer is formed by the electroplating process, Performing a hydrogen reduction heat treatment on the copper layer; And And CMP the resultant until the surface of the interlayer insulating film is exposed. 23. The method of claim 22, The hydrogen reduction heat treatment is a metal wiring forming method of a semiconductor device, characterized in that carried out at a temperature of from room temperature to 350 ℃ in a hydrogen reduction atmosphere. 24. The method of claim 23, Metal of a semiconductor device characterized by using any one of a hydrogen reduction atmosphere is H ₂ gas, a mixture of Ar gas to H ₂ gas hydrogen mixed gas, and N ₂ gas having a hydrogen gas mixture mixed with the H ₂ gas Wiring formation method. 23. The method of claim 22, Before performing the hydrogen reduction heat treatment, Spin and rinse dry the copper layer. The method of claim 1, And the opening is one of a dual damascene pattern, a via hole, and a trench.

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