KR101178324B1 - Safety-grade communication interface module for nuclear power plant satety system - Google Patents

Abstract

Disclosed is a safety class communication module used in nuclear power communication networks. In one embodiment, the safety class communication module, a dual-port memory for storing the transmission data, using a field-programmable gate array (FPGA), a packet processor for packet processing the transmission data on a hardware basis, and the It may be configured to include a transceiver for transmitting the packetized transmission data, when the received data is delivered to the packet processor by the transceiver, the packet processor may process the received data using the FPGA. .

Description

Safety class communication module {SAFETY-GRADE COMMUNICATION INTERFACE MODULE FOR NUCLEAR POWER PLANT SATETY SYSTEM}

Embodiments of the present invention relate to a safety class communication module used in nuclear power communication networks.

A nuclear power plant usually consists of a system with more than 100 individual functions. These systems are largely divided into a nuclear steam supply system (NSSS) centered on a nuclear reactor, a secondary circulation cooling system that delivers steam to a generator, and a turbine that receives steam from the secondary circulation cooling system and runs a generator. Generator system, and other auxiliary equipment.

In order to monitor the health of each system while operating the nuclear power plant, various types of sensors must be installed in the reactor system, and the signals input from the sensors must be monitored to determine the state of the nuclear power plant. At this time, if there is an abnormality in the system affecting the safety of the reactor during operation of the nuclear power plant or an abnormality in the cooling function in the nuclear steam supply system, such an abnormal state is detected and the reactor stop function is started by dropping the control rod and engineering safety The plant operating system must be driven to cool the reactor.

In recent years, in the measurement control system of nuclear power plants, system devices are digitized according to the development of digital and communication technology, and information exchange between system devices is also performed through a high speed digital communication network. Since nuclear power plants require high reliability and safety, nuclear network technology must also provide high availability and high reliability.

Accordingly, in the nuclear power communication network, there is a demand for a communication module capable of ensuring soundness of operation and data, and ensuring high-speed packet processing and reliability without causing malfunctions to affect other modules.

An embodiment of the present invention uses the VERSA module Eurocard bus (VME bus), an industrial digital system interface standard that has proven reliability and performance, and processes packets based on hardware using FPGA technology, thereby improving high-speed packet processing and reliability. Provide safety class communication module that can be secured.

In addition, an embodiment of the present invention provides a safety-grade communication module that can minimize the influence on other modules due to the occurrence of an error by excluding direct signal transmission and reception between modules.

In addition, an embodiment of the present invention provides a safety class communication module that can perform a diagnosis and monitoring function by itself using a separate Digital Signal Processor (DSP).

In addition, an embodiment of the present invention provides a safety-grade communication module that can withstand electromagnetic interference by using an optical cable having excellent electrical isolation characteristics as a transmission medium.

In order to achieve the above object, the safety class communication module comprises a packet processor for hardware-based packet processing of the transmission data using a dual-port memory for storing transmission data and a field-programmable gate array (FPGA), And a transceiver for transmitting the packetized transmission data, and when the reception data is transmitted to the packet processor by the transceiver, the packet processor packetizes the received data using the FPGA.

According to one embodiment of the present invention, when a malfunction occurs in a nuclear power communication network, it is possible to ensure the operation and soundness of data and to ensure high-speed packet processing and reliability without affecting other modules.

1 is a view showing the configuration of a safety class communication module according to an embodiment of the present invention.
2 is a view showing a detailed configuration of a safety class communication module according to an embodiment of the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. Like reference symbols in the drawings denote like elements.

1 is a view showing the configuration of a safety class communication module according to an embodiment of the present invention.

1 shows an internal configuration of a safety class communication module 100 used in a nuclear power plant measurement control system (nuclear power communication network). Referring to FIG. 1, the safety class communication module 100 according to an embodiment of the present invention may include a dual port memory 110, a packet processor 120, and a transceiver 130.

The dual port memory 110 stores transmission data.

In this case, the dual port memory 110 may be physically separated into a space for storing the transmission data to be transmitted and a space for storing the received reception data so as to support data transmission and reception through the network of the process module 180.

That is, the dual port memory 110 may include a Tx-FIFO buffer for storing transmission data, and an Rx-FIFO buffer for storing received data separately from the Tx-FIFO buffer. Accordingly, the dual port memory 110 may store the received data separately from the transmitted data. For example, the dual port memory 110 may be a RAM of 32Kbytes size.

The packet processor 120 functions to hardware-process the transmission data using a field-programmable gate array (FPGA). That is, the packet processor 120 reads the transmission data stored in the dual port memory 110 and transfers the read transmission data and a frame including an address or a CRC code to the transceiver 130. have.

The transceiver 130 functions to transmit the packet processed transmission data.

Here, the transceiver 130 may be implemented as a PHY Transceiver that is responsible for the communication function of the physical layer, the transceiver 130 is a packet processor 120 that is responsible for the communication function of the MAC layer and through the Media Independence Interface (MII) Can be connected. In addition, the transceiver 130 may be responsible for serializing parallel data, parallelizing serial data, and coding of physical layers such as 4B / 5B coding / decoding and NRZ-I.

In addition, when the received data is transmitted to the packet processor 120 by the transceiver 130, the packet processor 120 packetizes the received data using an FPGA. That is, the packet processor 120 may check an error with respect to the received data and store the received data that is checked as not in an error in the Rx-FIFO buffer in the dual port memory 110.

In addition, as another embodiment of the present invention, the safety class communication module 100 may further include a digital signal processor 140 for performing a diagnostic or monitoring function for the safety class communication module 100.

Here, the digital signal processor 140 monitors the cyclic redundancy check (CRC) function for the packet processor 120 and monitors the health of the dual port memory 110 (that is, the Tx-FIFO buffer and the Rx-FIFO buffer). , The PHY layer inspection of the generated test frame, or monitoring of data traffic may be performed. In addition, the digital signal processor 140 may monitor data traffic exchanged through the safety class communication module 100.

In addition, as another embodiment of the present invention, the safety class communication module 100 may further comprise a VME interface 150.

Here, the VME interface 150 may interface with the process module 180 that exchanges data with the dual port memory 110. The interface for data exchange with the process module 180 is via the VME backplane and may be performed in an FPGA named VME interface.

In addition, the digital signal processor 140 may diagnose data exchange function between the dual port memory 110 and the VME interface 150 while reading and writing data in the dual port memory 110.

In addition, as another embodiment of the present invention, the safety class communication module 100 may further comprise an optical transmitter 160 and the optical receiver 170.

The optical transmitter 160 may function to convert the packetized transmission data transmitted from the transceiver 130 into an optical signal.

In addition, the optical receiver 170 may function to convert the received data of the optical signal received from the optical cable into an electrical signal and transmit it to the transceiver 130.

Therefore, according to one embodiment of the present invention, when a malfunction occurs in a nuclear power communication network, it is possible to ensure the operation and soundness of data without affecting other modules, and to ensure high-speed packet processing and reliability.

2 is a view showing a detailed configuration of a safety class communication module according to an embodiment of the present invention.

2, the safety level communication module 200 according to an embodiment of the present invention is a dual port memory 110, packet processor 120, PHY transceiver, DSP, VME interface, Fiber Optic Transimitter, Fiber Optic Receiver It may be configured to include a MAC address DIP Switch, a VME Address DIP Switch, and a VME-Backplane.

The dual port memory 110 may include a Tx-FIFO buffer 210 and an Rx-FIFO buffer 220.

The Tx-FIFO buffer 210 may store transmission data, and the Rx-FIFO buffer 220 may be separated from the Tx-FIFO buffer 210 and store received data.

The packet processor 120 may include a data transmitter 230 and a data receiver 240.

The data transmitter 230 may read transmission data stored in the Tx-FIFO Buffer 210, generate an address, a CRC32 code, and the like, configure a frame, and transmit a frame configured with a 10 or 100 Mbps PHY transceiver.

The data receiver 240 receives the received data from the 10 or 100 Mbps PHY Transceiver, stores the frame, interprets the frame header to determine whether to store the data, calculates the CRC32, checks the error, and receives the received received data in the Rx-FIFO Buffer. Can be stored at 220.

Here, the DSP (Digital Signal Processor) may perform its own diagnostic and monitoring function for the safety class communication module 200.

In addition, the interface for data exchange with process modules is via the VME backplane and can be performed in an FPGA named VME interface.

As described above, according to an embodiment of the present invention, by using a VME bus (VERSA module Eurocard bus), which is an industrial digital system interface standard whose reliability and performance have been verified, and processing packets on a hardware basis using FPGA technology, Packet processing and reliability can be secured.

In addition, according to an embodiment of the present invention, by excluding direct signal transmission and reception between modules, it is possible to minimize the influence on other modules due to the occurrence of an error.

In addition, according to an embodiment of the present invention, by using an optical cable having excellent electrical isolation characteristics as a transmission medium, it is possible to withstand electromagnetic interference well.

In the present invention as described above has been described by the specific embodiments, such as specific components and limited embodiments and drawings, but this is provided to help a more general understanding of the present invention, the present invention is not limited to the above embodiments. For those skilled in the art, various modifications and variations are possible from these descriptions. Therefore, the spirit of the present invention should not be construed as being limited to the described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, are included in the scope of the present invention.

100: safety class communication module
110: dual port memory
120: packet processor
130: transceiver
140: digital signal processor
150: VME interface
160: optical transmitter
170: optical receiver

Claims (7)

A transceiver for transmitting the received data;
A packet processor for packet-processing the transferred data using a field-programmable gate array (FPGA) in a communication network used in a nuclear power plant metrology control system; And
A digital signal processor that performs diagnosis and monitoring based on the packet processed by the packet processor and provides information on the performance to a process module.
Including,
The packet processor,
The packet processing unit includes: a data receiving unit which checks an error on the data and stores the checked data in a dual port memory as an error; And
A data transmitter for reading data stored in the dual port memory and transferring a frame including the read data and an address or a CRC code to the transceiver;
Including, safety rating communication module. delete The method of claim 1,
The dual port memory,
Rx-FIFO buffer for storing the packetized data
Including, safety rating communication module. The method of claim 1,
The digital signal processor,
Performing at least one of monitoring of a Cyclic Redundancy Check (CRC) function for the packet processor, monitoring of health for the dual port memory, checking of the PHY layer for generated test frames, or monitoring for data traffic Class communication module. delete The method of claim 1,
The data receiver,
At least one of cyclic redundancy check (CRC) error frame information, MAC error frame information, length error frame information, header error frame information, or Rx-FIFO buffer overflow information for the data having an error. Update the transmitted information to the digital signal processor,
The data transmission unit,
A safety class communication module for updating a transmission frame count value and transmitting the same to the digital signal processor. The method of claim 1,
The digital signal processor,
The packet processor collects at least one of CRC error frame information, MAC error frame information, length error frame information, header error frame information, or Rx-FIFO buffer overflow information to calculate total error count information for each information. ,
A safety class communication module for generating data traffic monitoring information using the transmission frame count value and the reception frame count value received from the packet processor, and transmitting the data traffic monitoring information when requested by the process module.

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