KR101175189B1 - Method for manufacturing N-type and P-type chalcogenide material, Doped homojunction chalcogenide thin film transister and method of fabricating the same - Google Patents

Abstract

The chalcogenide thin film transistor of the present invention and a manufacturing method thereof include: forming an n-type chalcogenide layer constituting a channel layer on a substrate; forming a diffusion barrier layer over the n-type chalcogenide layer and patterning the diffusion barrier layer; And depositing and diffusing the Te alloy on the n-type chalcogenide layer to form a p-type chalcogenide layer constituting the source and drain regions. According to the present invention, a thin film transistor can be manufactured using a chalcogenide material having an n-type conductivity and a chalcogenide material having a p-type conductivity.

Description

Method for manufacturing N-type and P-type chalcogenide material, Doped homojunction chalcogenide thin film transister and method of fabricating the same}

The present invention relates to a method of manufacturing n-type and p-type chalcogenide materials, a chalcogenide thin film transistor, and a method of manufacturing the same. More specifically, a method of manufacturing an n-type chalcogenide material and a p-type chalcogenide material, and a method of manufacturing a chalcogenide thin film transistor using an n-type chalcogenide material and a p-type chalcogenide material will be.

In general, with the development of information and communication technology, technological developments such as high-speed processing and mass storage are also being made. Elements used in information storage include optical information storage elements known as CDs and DVDs, and electric memory elements such as DRAMs. Devices used in the field of information storage and processing include photo thin film transistors and CMOS image sensors. Photo thin film transistors are typically manufactured using a CMOS process.

The low-cost, low-efficiency optical conductivity is achieved by using the unique element of GeTe-Sb ₂ Te ₃ (Ge ₂ Sb ₂ Te ₅ : GST), which contains the CHALCOGENIDE series of elements on the periodic table. Low temperature process photoconductive thin film transistor (PHOTO-TFT) can be manufactured. In addition, an empty state of the same concentration of the Ge ₂ Sb ₂ Te ₅ as the charge concentration by the isolated electron pair state of the germanium antimony telluride (Ge ₂ Sb ₂ Te ₅ ) material of the amorphous phase containing an element of the chalcogenide series ( An undoped thin film type chalcogenide transistor may be fabricated using a diode function predicted as a potential barrier formation principle caused by a difference in charge concentration due to a vacancy state.

However, as in the present invention, by adding oxygen (O ₂ ) to Ge ₂ Sb ₂ Te ₅ containing a chalcogenide-based element based on the periodic table, the n-type chalcogenide material and the p-type chalcogenide material are There is no known method for producing a thin film transistor using the manufactured n-type chalcogenide material and p-type chalcogenide.

Looking at the conventional technology for the optical recording material of the optical information storage, the next generation nonvolatile memory that has been studied using Ge ₂ Sb ₂ Te ₅ as follows.

[Prior Art 1]

Prior art 1 changes the phase of Ge ₂ Sb ₂ Te ₅ from amorphous phase to crystalline phase to crystalline phase by applying a certain amount of light. It is about whether it can be applied to information storage.

[Prior Art 2]

The prior art 2 was proposed by Ovsinsky, the first proposer of the Ge ₂ Sb ₂ Te ₅ series phase change material, and the phase change phenomenon is described in terms of nonvolatile memory (PRAM) using phase change. It relates to a method used for electric memory. This technique relates to memory as a method of applying a switch phenomenon to an electrical memory in which crystalline phases move together.

[Prior Art 3]

The prior art 3 relates to a paper announcing the results of measuring characteristics by fabricating an electric memory transistor using Ge ₂ Sb ₂ Te ₅ . Basically, it corresponds to the method using the phase change mechanism taken in the above-described prior art 1 and the prior art 2, and applies a switching phenomenon to the memory and the TFT, which is shown by moving states in a crystalline or amorphous phase.

Chalcogenide materials are known to have typical p-type conductivity due to the inherent properties of their atomic structure. It is known that the main cause of the p-type conductivity is caused by the vacancy state in the band gap. Due to the unique characteristics of the atomic structure, no n-type chalcogenide material has been developed until now.

1 is a conceptual diagram schematically illustrating a structure of a photo thin film transistor manufactured using a general CMOS process. The structure of the photo thin film transistor manufactured by the actual CMOS process is more complicated.

Referring to FIG. 1, an amorphous silicon film 110 is formed on a silicon substrate 100 doped with impurities. Source and drain ohmic contact portions 120 are formed on both sides of the amorphous silicon film 110 to improve ohmic contact. The ohmic contact part 120 is formed by implanting impurities into a portion of the amorphous silicon film 110. The source electrode 140 and the drain electrode 150 are formed in the source and drain ohmic contact part 120, respectively. The gate insulating layer 130 is formed on the amorphous silicon film 110, the ohmic contact portion 120, the source electrode 140, and the drain electrode 150. The gate insulating film 130 is formed using an oxide film. A gate electrode is formed on the gate insulating layer 130 using the metal layer 160.

In order to manufacture a conventional photo thin film transistor having such a structure, a high temperature (eg, 500 ° C. to 1000 ° C.) process is required. In particular, the thin film transistor manufactured by using the CMOS process of FIG. 1 must use an expensive silicon substrate and absolutely requires an ion implantation process for forming an ohmic contact portion. Or absolutely requires hydrogenated and doped ohmic contact portions.

Currently, TFTs used in TFT-LCD displays and / or mobile phones have the same structure as in FIG. 1.

In the case of chalcogenide material, in order to utilize the layer of reference numeral 110 of FIG. do. This structure is known as the typical structure of the best transistor.

The present invention is designed to solve the above problems,

An object of the present invention is to develop a chalcogenide material having an n-type conductivity and a chalcogenide material having a p-type conductivity by using a chalcogenide material that can be actively used in the information storage field or used as a next-generation device. .

In addition, an object of the present invention is to manufacture a highly efficient chalcogenide thin film transistor having a high on / off ratio by using the developed n-type and p-type conductivity material.

The n-type chalcogenide material manufacturing method according to the present invention comprises the steps of: placing a chalcogenide material as a target; And injecting argon (Ar) gas and oxygen (O ₂ ) gas into the deposition chamber to deposit the chalcogenide material on the substrate.

In particular, the chalcogenide material is characterized in that the Ge ₂ Sb ₂ Te ₅ .

On the other hand, n-type chalcogenide material manufacturing method of the present invention, the step of depositing a Te alloy on the n-type chalcogenide material; And diffusing the n-type chalcogenide material on which the Te alloy is deposited.

In particular, Te alloy is characterized in that the one selected from the group consisting of GeTe, SbTe, Te.

In addition, the step of diffusing the n-type chalcogenide material on which Te alloy is deposited is characterized in that it is performed by applying thermal energy to the n-type chalcogenide material on which Te alloy is deposited.

On the other hand, chalcogenide thin film transistor manufacturing method, the step of forming an n-type chalcogenide layer constituting a channel layer on the substrate; forming a diffusion barrier layer over the n-type chalcogenide layer and patterning the diffusion barrier layer; And depositing and diffusing the Te alloy on the n-type chalcogenide layer to form a p-type chalcogenide layer constituting the source and drain regions.

In particular, the substrate is characterized in that one of a glass substrate, a plastic substrate, a polyimide substrate, a vinyl substrate.

The chalcogenide layer may be formed of a Ge ₂ Sb ₂ Te ₅ layer.

The method may further include forming a gate electrode through the gate insulating layer under the n-type chalcogenide layer constituting the channel layer.

The gate insulating layer may be a polymer PMMA film which is an organic material.

In addition, the gate insulating layer is characterized in that the silicon oxide film formed by the PECVD method.

On the other hand, the thin film transistor of the present invention comprises a chalcogenide layer constituting a channel layer and having a first type conductivity; A chalcogenide layer formed on both sides of the chalcogenide layer having a first type conductivity to form a source and a drain region, and having a second type conductivity; And a source electrode and a drain electrode constituting the source and drain regions and connected to the chalcogenide layer having the second type conductivity.

In particular, the chalcogenide layer constituting the channel layer and the source and drain regions is a Ge ₂ Sb ₂ Te ₅ layer.

In addition, a gate electrode formed through the gate insulating layer below the chalcogenide layer having the first conductivity may be further provided.

The gate insulating layer may be a polymer PMMA film which is an organic material.

In addition, the gate insulating layer is characterized in that the silicon oxide film formed by the PECVD method.

In addition, a diffusion barrier layer is formed on the chalcogenide layer having the first conductivity.

The channel layer is n-type, and the source and drain regions are p-type.

The channel layer is p-type, and the source and drain regions are n-type.

The present invention has the following effects.

A method of preparing a chalcogenide material and a p-type conductivity chalcogenide material using a chalcogenide material and a chalcogenide material having a n-type conductivity and a chalcogenide having a p-type conductivity Thin film transistors can be manufactured using materials.

In addition, the thin film transistor according to the present invention is not only can be manufactured in a low temperature process, but also can be processed on a plastic substrate, and there is an advantage that it can be implemented at low cost because no ion implantation is required.

In addition, it has a high mobility and it is expected that logic devices on a sensor or plastic substrate can be manufactured in the future.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, a repeated description, a known function that may obscure the gist of the present invention, and a detailed description of the configuration will be omitted. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity. In the drawings, the size and thickness of films (layers) or regions are exaggerated for clarity.

The present invention utilizes a CHALCOGENIDE layer that can be actively used in the information storage field or as a material for next generation nonvolatile memory devices. As an example of the chalcogenide layer, a GeTe-Sb ₂ Te ₃ layer (Ge ₂ Sb ₂ Te ₅ , hereinafter referred to as a 'GST layer') is used. Although the GST layer is exemplified as a chalcogenide layer, the present invention is not limited thereto.

The chalcogenide layer used in the present invention has high efficiency photoconductivity and can be used as a photoconductive layer of an optical thin film transistor (Photo TFT). In addition, the chalcogenide layer of the present invention can change the phase from the amorphous phase to the crystalline phase or the crystalline phase to the amorphous phase by laser or thermal energy.

Of course, the thin film transistor of the present invention can be formed on a glass substrate in a low cost and low temperature process.

Chalcogenide layers are only possible for p-type semiconductors due to the inherent properties of their atomic structure. The majority of p-type charges in the amorphous phase are governed by the lone pair electron state. The amorphous chalcogenide layer exhibits p-type semiconductor characteristics due to the lone electron pair state. The Fermi Level (Ef) of the amorphous chalcogenide layer is in the form of a p-type semiconductor close to the intrinsic level (Ei), and the difference in charge concentration (carrier concentration) between the intrinsic level (Ei) and the Fermi level (Ef) Difference) is Φ p2 and has a small value. The band gap (Egp2) between the valence band (Ev) and the conduction band (Ec) of the amorphous chalcogenide layer is 0.7 eV. In the crystalline chalcogenide layer, the lone electron pair state in the amorphous phase disappears and the p-type semiconductor characteristics are exhibited by a large number of charges generated by a vacancy state occurring in the periodic crystalline atomic structure.

Accordingly, the n-type chalcogenide material has never been developed by the doping method due to the defect of the basic atomic structure described above.

In the present invention, the chalcogenide material exhibiting the n-type semiconductor characteristics (hereinafter, 'n-type chalcogenide material').

First, a chalcogenide material (eg, GST) is deposited on a substrate. The equipment used for deposition is a sputter (eg, RF Magnetron Sputter) equipment, which is typically used to deposit chalcogenide materials. In addition to sputtering, a thermal evaporation apparatus is also possible.

Sputter is used to find the conditions for depositing a chalcogenide material, GST, as a co-sputter or a single target. At this time, argon (Ar) gas is used as the plasma gas. The above process is generally a method used when depositing a chalcogenide material.

2 is a graph showing the transmission characteristics of the chalcogenide material generally deposited according to the above-described method.

In the case of amorphous chalcogenide, the band gap is 0.7 eV (wavelength of about 1700 nm band) as shown in FIG. 2. When the amorphous chalcogenide deposited is crystallized in this way, the band gap becomes about 0.5 eV, and the light transmission curve is a curve in which the long wavelength is shifted.

Below, the process of manufacturing an n-type chalcogenide raw material is demonstrated.

First, in order to fabricate an n-type chalcogenide material, oxygen may be added to a deposition chamber when manufacturing an amorphous chalcogenide as shown in FIG. 3.

More specifically, the chalcogenide material is placed as a target. And oxygen gas other than argon gas is simultaneously injected into a vapor deposition chamber. Then, a portion of the injected oxygen gas is injected into the deposited chalcogenide thin film, and an n-type chalcogenide material is formed by the injected oxygen. That is, when the injection of argon gas and oxygen gas is completed, high frequency energy is supplied to a sputter gun (not shown) so that the mixture of argon gas and oxygen gas is ionized, thereby generating plasma.

Argon and oxygen ions ionized in the generated plasma impinge on the target and sputter the target material, resulting in the deposition of chalcogenide material on the substrate.

When the chalcogenide material is deposited using a sputter, when argon gas is injected to form plasma, oxygen gas is injected and injected simultaneously with the argon gas injection for n-type chalcogenide material deposition. At this time, it can be deposited while varying the ratio of the amount of oxygen gas injected and the amount of argon gas injected.

Oxygen gas and argon gas were injected into the sputter at a ratio of the amount of oxygen gas / argon gas used in the present invention at a ratio of 0.1, 0.25, 0.35, and 0.5, respectively (for example, an oxygen injection amount of 2 sccm / argon injection amount of 20 sccm = 0.1). ). At this time, the thickness of the n-type chalcogenide material to be deposited is controlled by the deposition time.

The chalcogenide material deposited by oxygen doping may be determined to be amorphous by X-ray diffraction (XRD) measurement.

4 is a result of measuring the light transmission curve of the chalcogenide material changed when the oxygen gas and the argon gas are injected into the sputter with the ratio of the amount of oxygen gas / argon gas being 0.1, 0.25, 0.35, and 0.5, respectively. As the oxygen input amount increases, the band gap shifts to the shorter wavelength. When the injection ratio of the amount of oxygen gas / argon gas is 0.1, the bandgap energy is about 1300 nm in wavelength, about 1200 nm for 0.2, about 1100 nm for 0.35, and about 1000 nm for 0.5.

In FIG. 4, the reason why the light transmission curve is curved at a long wavelength (after 1400 nm) is a typical phenomenon caused by interference of light, which is not significant for band gap prediction.

The Hall Effect was measured for each material to determine whether the conductivity of the chalcogenide material produced by varying the injection ratio of oxygen gas / argon gas was n-type or p-type.

Table 1 summarizes the results of measuring the Hall effect of the chalcogenide material produced by varying the injection ratio of the amount of oxygen gas / argon gas. Through the Hall effect, the types of carriers, the concentration of carriers, and the mobility can be known.

Injection rate of oxygen gas volume / argon gas volume Carrier Concentration (/ cm ^ 2 ) 0.1 -1.2e15 0.25 -6.99e14 0.35 -5.5e14

Looking at Table 1, it can be seen that the n-type chalcogenide material is formed regardless of the oxygen injection amount of the oxygen gas amount / argon gas amount of 0.1 to 0.35.

It is expected to be n-type material even after the injection ratio of oxygen gas / argon gas is 0.35, but if the amount of oxygen is too high, it becomes an amorphous phase with an oxide, and any (eg n-type or p-type) conductivity is measured by hole measurement. It is not known whether the material has a.

FIG. 5 is a graph illustrating a band gap that is changed by heat treatment of a chalcogenide material manufactured by varying an injection ratio of an oxygen gas amount / argon gas amount as shown in FIG. 4 in a light transmission curve. In FIG. 5, the injection ratios of oxygen gas amount / argon gas amount are 0.25, 0.35, and 0.5, respectively.

After heat treatment, the sample changes from an amorphous phase to a crystalline phase. When the injection ratio of oxygen gas amount / argon gas amount was 0.1, the band gap was about 1700 nm in the wavelength band, and in the case of 0.25, 0.35, and 0.5, the band gap band was shifted to the 1700 nm band in wavelength.

Eventually, the oxygen-doped chalcogenide thin film shows a phenomenon in which the band gap decreases as the phase transitions from the amorphous phase to the crystalline phase. These results are generally the same as the band gap changes from 0.7 eV to 0.5 eV as the phase changes from the amorphous phase to the crystalline phase in which the chalcogenide material without oxygen doping is seen.

However, in the case of oxygen doped chalcogenide thin films, when the injection ratio of oxygen gas / argon gas amount is from 0.1 to 0.5, the band gap becomes weak when the phase gap changes from the initial amorphous phase of 1.0 eV to 1.2 eV to the crystalline phase. The difference is that it moves to 0.7 eV.

Hereinafter, the process of manufacturing a p-type chalcogenide raw material is demonstrated.

As shown in FIG. 3, in order to manufacture a p-type chalcogenide material, when a Te alloy of at least one of GeTe, SbTe, and Te is deposited on an oxygen-infused chalcogenide thin film (material), and heat-treated, the diffusion is diffused. do.

It has been mentioned that the chalcogenide material is empty because it exhibits p-type conductivity. Therefore, it is highly likely that the chalcogenide material is converted to the p-type conductivity material by injecting the Te chalcogen element, which is the main factor that causes the empty state.

Accordingly, in the embodiment of the present invention, the chalcogenide material injected with oxygen is changed from an n-type conductivity material to a p-type conductivity material by injecting GeTe. As the injection method, GeTe was deposited on a deposited oxygen-doped chalcogenide material, heat treated, and a method of diffusion was selected. Generally, the heat treatment temperature to be diffused may be heat treated for about one hour at a temperature at which the chalcogenide phase changes from an amorphous phase to a crystalline phase.

Table 2 shows how the thickness of GeTe deposited on the oxygen-doped n-type chalcogenide material changes from the n-type chalcogenide material to the p-type chalcogenide material. GSTO is an n-type chalcogenide material in which the injection ratio of oxygen gas amount / argon gas amount is 0.1.

rescue shape Carrier Concentration (/ cm ^ 2) GeTe / GSTO = 0.1 N type -1.49e15 GeTe / GSTO = 0.2 N type -3.7e14 GeTe / GSTO = 0.3 P type + 2.3e16

Figure 6 is another light transmission curve before the diffusion and heat treatment of the p-type chalcogenide material prepared according to Table 2. This is the light transmission curve before the light transmission curve between the left 1000 nm and 1500 nm is diffused. Norm AS21, Norm AS20 and Norm AS19 of FIG. 6 are light transmittances of an N-type semiconductor to which oxygen is added before heat treatment, and Norm Ann21, Norm Ann20 and Norm Ann19 of FIG. 6 are light transmittances after heat treatment.

7 is a light transmission curve after heat treatment is performed by diffusing a p-type chalcogenide material prepared according to the method of Table 2 (right curves moved to 1700n).

It can be seen that the light transmission curve of the p-type chalcogenide material in which GeTe is diffused is doped so as not to change significantly from the initial oxygen-doped n-type chalcogenide material.

In the above, a method of manufacturing an n-type chalcogenide material and a p-type chalcogenide material was mentioned. Hereinafter, a process of fabricating a chalcogenide transistor using a chalcogenide material having an n-type conductivity and a chalcogenide material having a p-type conductivity manufactured through the above-described process will be described in detail.

8 to 18 are diagrams for explaining a process sequence for fabricating a transistor device having an improved on / off ratio using n-type chalcogenide and p-type chalcogenide.

Specifically, the metal layer 202 for a gate electrode is formed on the board | substrate 200, for example, a glass substrate (FIG. 8). The gate electrode metal layer 202 is formed on the substrate 200 by using a sputtering method. The gate electrode metal layer 202 is composed of, for example, a gold layer, an aluminum layer, or a chromium layer. The gate electrode metal layer 202 is patterned by a photolithography process to form the gate electrode 204. Thus, the gate electrode 204 in the form of a lower gate is completed (Fig. 9). The gate electrode 204 serves to turn on / off a photocurrent flowing in the chalcogenide layer 208 to be described later.

In FIG. 9, the gate insulating layer 206 and the gate electrode 204 are formed in the form of a lower gate formed under the chalcogenide layer 208, but the gate insulating layer 206 and the gate electrode 204 are formed. It may be configured in the form of an upper gate formed on the chalcogenide layer 205.

A gate insulating layer 206 is formed on the gate electrode 204 and the substrate 200 (FIG. 10). The gate oxide layer 206 may be formed of a chalcogenide-based insulating layer, such as an As ₂ S ₃ layer, a polymer PMMA film, a silicon oxide film, a silicon insulating film, or the like, which is an organic material. The polymer PMMA (poly methyl methacrylate) layer, which is an organic material constituting the gate insulating layer 206, is a transparent film. The gate insulating layer 220 maintains good contact with the chalcogenide layer 208 and does not change the properties of the chalcogenide layer 208 during the manufacturing process.

When the silicon oxide film is used as the gate insulating layer 206, the gate insulating layer 206 is formed by a plasma enhanced chemical vapor deposition (PECVD) method.

Next, an amorphous chalcogenide layer 208 is deposited on the gate insulating layer 206. In this case, as described above with reference to FIG. 3, in order to form an amorphous n-type chalcogenide layer 208, argon gas and oxygen gas are simultaneously injected into the deposition equipment. Then, a portion of the injected oxygen gas is injected into the deposited chalcogenide material, and the n-type chalcogenide layer 208 is formed by the injected oxygen. In an embodiment of the present invention, the chalcogenide layer 208 is formed of a GST layer and formed by a sputtering method (FIG. 11).

The upper surface of the amorphous chalcogenide layer 208 is irradiated with a laser to form a crystalline galcogenide layer 209 (FIG. 12).

In addition, the diffusion barrier layer 210 is deposited on the chalcogenide layer 209 so that diffusion does not occur. In this case, the diffusion barrier layer 210 is formed of a silicon oxide film (SiO ₂ ). In addition, the metal layer 212 is formed on the diffusion barrier layer 210. For example, the metal layer 212 is formed using aluminum (Al) (FIG. 13).

Next, the diffusion barrier layer 210 and the metal layer 212 formed on the crystalline chalcogenide layer 209 are patterned by photolithography and wet etching to form a diffusion barrier layer 214 and a metal layer having a predetermined width. 216) (FIG. 14).

The n-type conductivity of the chalcogenide layer 209 into which oxygen is injected is deposited through a method of depositing, heat treating, and dispersing GeTe in the chalcogenide layer 209 and the metal layer 216 formed on the gate insulating layer 206. Change from material to p-type conductivity material. Generally, the heat treatment temperature to be diffused may be heat treated for about one hour at a temperature where the chalcogenide phase changes from an amorphous phase to a crystalline phase.

As described above, the GeTe thin film is diffused at both sides of the chalcogenide layer 209 where the diffusion barrier layer 214 is not formed through the heat treatment process. That is, the GeTe thin film deposited on the exposed chalcogenide layer 209 is diffused at both sides of the chalcogenide layer 209 having n-type conductivity through a heat treatment process. Accordingly, both sides of the chalcogenide layer 209 having an n-type conductivity are changed to the chalcogenide layer 220 having a p-type conductivity.

At this time, the chalcogenide layer 209 on which the diffusion barrier layer 214 is formed, that is, the chalcogenide layer 209 that is not exposed, is maintained as the galcogenide layer 218 having n-type conductivity. In the present invention, the process of naturally forming the channel of the transistor will be referred to as a 'self-aligned channel process' (FIG. 15).

Accordingly, the channel width and length are naturally formed according to the shape of the antioxidant layer 214 patterned on the n-type chalcogenide layer 209. GeTe deposited on the diffusion barrier layer 214 is removed in a later process.

Thereafter, the chalcogenide layer 220 having the p-type conductivity is patterned to form a predetermined width (FIG. 16). Then, a rare layer 222 is formed on the chalcogenide layer 220, the metal layer 216, and the gate insulating layer 206 so that a contact hole 224 may be formed (FIG. 17). .

Next, a thin film transistor is completed by forming a source side metal electrode 226 and a drain side metal electrode 228 in the contact hole 224 (FIG. 18).

19 is a view illustrating a device manufactured according to the process sequence of FIGS. 8 to 17. That is, just before forming the source and drain metal electrodes. The part shown in black in the center in FIG. 19 corresponds to the channel of the transistor. The thin film transistor according to the present invention has an advantage that the channel width is naturally aligned through a self-aligned channel process as mentioned with reference to FIG. 15.

FIG. 20 is a graph showing characteristics of a thin film chalcogenide transistor made of an n-type chalcogenide material and a p-type chalcogenide material manufactured through the above-described process.

The X axis represents the source drain voltage, and the Y axis represents the unit drain current of nano amps. We can see the characteristic curve of a transistor that works very clean even at relatively low gate voltages. In addition, it can be seen that the current rectification degree shows a very good characteristic.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a conceptual diagram schematically illustrating a structure of a photo thin film transistor manufactured using a general CMOS process.

FIG. 2 is a view illustrating a light transmission curve of amorphous chalcogenide deposited through a general process, and is a light transmission curve of an amorphous chalcogenide thin film when deposited by a general sputtering method.

3 is a view showing a method of manufacturing an n-type chalcogenide material and a p-type chalcogenide material, a method of manufacturing an n-type chalcogenide material and p-type chalcogenide material formed by oxygen injection and GeTe diffusion. It is shown.

4 is a view showing a light transmission curve of the chalcogenide material varies depending on the amount of oxygen injected.

FIG. 5 is a view illustrating a shift of a light transmission curve after heat treatment of an oxygen-doped chalcogenide material, and illustrates a light transmission curve of a chalcogenide material depending on an oxygen injection amount.

6 is a view showing a light transmission curve before the p-type chalcogenide material is diffused and heat treated.

7 is a view showing a light transmission curve after the p-type chalcogenide material is diffused and heat treated.

8 to 18 are views for explaining a process of fabricating a transistor having an improved on / off ratio using an n-type chalcogenide material and a p-type chalcogenide material.

19 shows a channel state of a transistor that is naturally formed by the method of manufacturing a chalcogenide thin film transistor according to the present invention.

20 is a graph showing the characteristics of the thin-film chalcogenide transistor made of the n-type chalcogenide material and p-type chalcogenide material manufactured by the manufacturing method according to the present invention.

Claims (19)

delete delete delete delete delete Disposing a chalcogenide material as a target to form an n-type chalcogenide layer constituting a channel layer on the substrate; Simultaneously injecting argon (Ar) gas and oxygen (O 2) gas into a deposition chamber to deposit the chalcogenide material on a substrate; Forming a diffusion barrier layer on the n-type chalcogenide layer and patterning the diffusion barrier layer; And Depositing a Te alloy in the second region other than the first region in which the diffusion barrier layer is formed in the n-type chalcogenide layer; And Fabricating a chalcogenide thin film transistor comprising applying a thermal energy to the second region to diffuse the Te alloy deposited n-type chalcogenide material to form a p-type chalcogenide layer constituting a source and a drain region Way. The method of claim 6, The substrate is formed of any one of a glass substrate, a plastic substrate, a polyimide substrate, a vinyl substrate, The Te alloy is formed of any one of the group consisting of GeTe, SbTe, Te, chalcogenide thin film transistor manufacturing method. The method of claim 6, The chalcogenide layer is formed of a Ge ₂ Sb ₂ Te ₅ layer chalcogenide thin film transistor manufacturing method. The method of claim 6, And forming a gate electrode on the lower portion of the n-type chalcogenide layer constituting the channel layer through a gate insulating layer. The method of claim 9, The gate insulating layer is a chalcogenide thin film transistor manufacturing method characterized in that the organic PMMA film. The method of claim 9, And the gate insulating layer is a silicon oxide film formed by PECVD. A chalcogenide material is placed on a substrate as a target, and is then formed by simultaneously injecting argon (Ar) gas and oxygen (O2) gas into a deposition chamber, and having a first type conductivity that forms a channel layer. Naed layer; In the chalcogenide layer having the first conductivity, the Te alloy is deposited on the remaining second region except the first region where the diffusion barrier layer is formed, and the Te alloy is deposited by applying thermal energy to the second region. A chalcogenide layer formed by diffusing a cogenide material and having a second type conductivity constituting the source and drain regions; And And a source electrode and a drain electrode connected to the chalcogenide layer constituting the source and drain regions and having a second type conductivity. The method according to claim 12, The chalcogenide layer constituting the channel layer and the source and drain regions is a Ge ₂ Sb ₂ Te ₅ layer. The method according to claim 12, And a gate electrode formed under the chalcogenide layer having the first type conductivity via a gate insulating layer. The method according to claim 14, The gate insulating layer is a thin film transistor, characterized in that the organic PMMA film. The method according to claim 14, The gate insulating layer is a thin film transistor, characterized in that the silicon oxide film formed by the PECVD method. delete The method according to claim 12, And the channel layer is n-type, and the source and drain regions are p-type. The method according to claim 12, And the channel layer is p-type, and the source and drain regions are n-type.

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