KR101158505B1 - High-Speed Current Comparator and its using method - Google Patents

Abstract

The present invention relates to a high speed comparator and a high speed current comparison method used in an application for detecting an amount of current generated in an array of cells in a basic unit and converting it into a digital data form.

More specifically, in the present invention, an input voltage V _DD is applied as a source, a drain is connected to a reference current I _REF source, and a gate and a drain are conducted to generate a reference voltage V _REF as a gate signal. A reference current block unit including a first transistor; The second transistor receiving the reference voltage (V _REF ) to the gate to generate a mirror current (I _RN ) of the reference current (I _REF ) to be input to the source in series with the drain of the second transistor in sequence A data line unit including a first switching element, a first resistor, and a source of a detection current I _DN ; a unity gain buffer is formed by receiving the reference voltage V _REF to form a unity gain buffer. A pre-charge unit which charges in advance to a reference voltage V _REF value, and a voltage V _DN of the node between the first switching element and the first resistor as a negative input, and the reference voltage V _It provides a high-speed current comparator comprising a; and a comparator comprising a first comparator having a positive input ( _REF )) and a high-speed current comparison method using the same.

Reference current, reference voltage, data line, precharge, current comparator, current sensing

Description

High-speed current comparator and high-speed current comparison method using the same {High-Speed Current Comparator and its using method}

The present invention relates to a high speed comparator and a high speed current comparison method that can be used in an application that detects an amount of current generated in an array of cells in a basic unit and converts it into a digital data form. . In particular, in the method of detecting the amount of current, it can be said that the present invention relates to a current comparator that provides a faster current comparison method by adopting a pre-charging method.

Recently, in an application such as a nonvolatile memory, a fingerprint panel, and a touch screen, an array of cells of a certain basic unit is arranged, and the amount of current generated in each array is detected and the digital value is detected. Increasingly, applications are being converted to data.

In general, in such an application, a voltage sense amplifier and a current sense amplifier are used as output amplifiers of data for extracting data stored in a memory cell and transmitting the data to the next stage. Is often used because the sense speed is faster than the voltage sense amplifier. Also, in general, when the length of a transmission line that transfers data of a memory cell, that is, an input / output line pair is long, the current sensing amplification method is mainly used as compared to the voltage sensing amplification method.

The current sensing amplification method is a method of transferring a small amount of current loaded on the input / output line to the rear end without loss and converting it into a voltage to amplify it again.In order to increase the detection speed and prevent signal loss, It is required.

However, the current comparator with a multi-channel according to the prior art is easy to apply to an array form of cells in basic units such as nonvolatile memory, fingerprint recognition, touch screen, etc. Since the wire is connected to the cell, the physical wiring is long, so that the resistance is large, and the parasitic capacitance may be increased. This causes a problem that results in the response of the voltage, which is a form to be detected, to a change in the current of the data line to be delayed.

In addition, when the difference in the amount of current is very small, a relatively large amount of time is required to detect the amount of current by the resistance and parasitic capacitance of the data line in which the current is generated, and the delay time is proportional to the resistance and capacitance, Since it is inversely proportional to the amount of current, this response delay can be even more severe in the case of detection of a fine current with a small absolute value of the detection current or reference current.

Therefore, for their operation, not only i) very small differences in currents must be determined by comparing multiple channels of the array simultaneously with a single reference current, but also ii) the resistance and capacitance of the data lines. Is relatively large, there is a need for a fast current comparator and a current comparison method using the same that can support multiple channels that support very fast operation speed.

The present invention provides a current comparator that can be used in an application for detecting an amount of current generated in an array of cells of a basic unit and converting it into a digital data form. The purpose of the present invention is to provide a faster current comparison method and a faster current comparator by employing a charging method.

In addition, the present invention compares the current difference by using a single reference current (I _REF ) at the same time for multiple channels of the array (array) including a cell, a current comparator that supports multiple channels at a high operating speed And another method for providing a current comparison method.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

In order to solve the above-described problems of the related art, the present invention provides an input voltage V _DD applied as a source, a drain connected to a reference current I _REF source, and a gate and a drain connected to the reference voltage ( A reference current block unit including a first transistor for generating V _REF ); receiving the reference voltage V _REF at a gate to generate a mirror current I _RN of the reference current I _REF to be input to a source A data line unit including a second transistor, a first switching device sequentially connected to a drain of the second transistor, a first resistor, and a detection current (I _DN ) source; A precharge unit configured to receive the reference voltage V _REF to form a unity gain buffer to charge the data line with a reference voltage V _REF in advance for a predetermined time; And a comparator including a first comparator having a voltage V _DN of the node between the first switching element and the first resistor as a negative input and a positive input having the reference voltage V _REF as a positive input. Provide a current comparator.

In the present invention, the precharge unit includes a first operational amplifier configured to set the reference voltage V _REF as a positive input and to which a negative input and an output signal are conducted; A second switching element for switching between an output signal of the first operational amplifier and a negative input terminal of the first comparator; A pulse signal for a pre-charging time, which is connected to the second switching element and is a time for pre-charging the data line to a reference voltage V _REF value in advance. Precharging line; And a sensing time line connected to the first switching element and generating a pulse signal for a sensing time comparing the mirror current I _RN and the detection current I _DN . It includes a high speed current comparator.

In the present invention, the comparison unit compares the reference voltage V _REF and the voltage V _DN of the node between the first switching element and the first resistor to compare the mirror current I _RN and the detection current I _DN . And a high speed current comparator, characterized by calculating a comparison value.

In the present invention, the first transistor or the second transistor includes a high speed current comparator, characterized in that the PMOS transistor.

In the present invention, a channel unit including the data line unit, the precharge unit, and the comparison unit includes at least two or more high speed current comparators.

The present invention provides a high speed current comparator, comprising: generating a reference voltage V _REF at the reference current block unit; Generating a pulse signal from the precharging line to turn on the second switching device to pre-charge the data line to a reference voltage V _REF ; And generating a pulse signal in the sensing timeline to turn on the first switching device to compare the mirror current I _RN with the detection current I _DN . It includes a method.

Comparing the mirror current (I _RN ) and the detection current (I _DN ) in the present invention, the reference voltage (V _REF ) and the voltage of the node between the first switching element and the first resistor in the first comparator Comparing the (V _DN ) and calculating a comparison value between the mirror current (I _RN ) and the detection current (I _DN ).

The present invention provides a current comparator that can be used in an application for detecting an amount of current generated in an array of cells of a basic unit and converting it into a digital data form. It is effective to provide faster current comparison method and high speed current comparator by adopting -charging method.

In addition, the present invention compares and discriminates very small currents by using a single reference current I _REF at the same time for several channels of an array including a cell, thereby allowing multiple channels to be operated at a very high operating speed. It has the effect of providing a supported current comparator and current comparison method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only one of the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

1 is a block diagram of a reference current block unit 210 according to an embodiment of the present invention.

In the present invention, the reference current block unit (Reference Current Block) is the input voltage (V _DD ) 110 is applied as a source, the drain is connected to the reference current (I _REF ) source 130, the gate and the drain is conductive The first transistor MP _R 120 may generate the reference voltages V _REF 140 and 301 as signals. That is, the input voltage V _DD 110 of the input voltage terminal is applied based on the first transistor 120, the reference current source 130 is connected to the drain, and the reference voltage V _REF 301 is a gate signal. Is generated and supplied to each channel section. These reference voltages V _REF 140 and 301 are inputted to respective channel portions to substantially detect the detection current I _DN 310 of each data line and the mirror current I _RN 303 of the reference current. It is to calculate the current difference of.

2 is a block diagram in which a reference current block unit and one channel unit are combined according to an embodiment of the present invention.

The configuration of the reference current block unit 210 is as described above in the description of FIG. 1.

In the present invention, the channel unit 220 may include a comparator 230, a precharger 240, and a data line unit 250.

The data line unit 250 receives a reference voltage V _REF 301 generated by the reference current block unit 210 to a gate, and mirror current I _RN of the reference current I _REF 130 ( The second transistor 304 may be generated and input to the source.

In addition, the data line unit 250 may include a first switching device 307, a first resistor 308, and a detection current I _DN source that are sequentially connected to the drain of the second transistor 304 in series. The first switching element 307 is opened and closed by the operation of the pulse-pulse of the sensing time line 312 to be described later, and when the first switching element 307 is turned off, the data line is referred to as the reference voltage V _REF ( When the precharging time of charging the battery 301 in advance is advanced, and the first switching device 307 is turned on, the sensing time of comparing the mirror current I _RN 303 and the detection current I _DN 310 proceeds. do.

The precharge unit 240 receives the reference voltage V _REF 301 through the reference current block unit 210 to form a unity gain buffer to convert the data line to the reference voltage V _REF for a predetermined time. It charges in advance to the value (301).

The precharge unit 240 uses the reference voltage V _REF 301 as a positive input, and outputs signals of the first operational amplifier 305 and the first operational amplifier 305 to which the negative input and output signals are conducted. And a second switching device 306 and a second switching device 306 for switching between the negative input terminal of the first comparator 313 and the second switching device 306, and the data line is pre-set to the value of the reference voltage V _REF 301. It is connected to the precharging line 311 and the first switching device 307 for generating a pulse signal for a pre-charting time of pre-charging, and the mirror current I _RN ( 303 and a sensing time line 312 for generating a pulse signal with respect to a sensing time (sensing time) for comparing the detection current (I _DN ) 310. That is, when the pulse signal of the precharging line 311 is generated, the second switching device 306 is turned on, and the data line is pre-charged to the reference voltage V _REF 301 in advance. When the precharging time progresses and the pulse signal of the sensing time line 312 is generated, the second switching device 306 is turned off, and the mirror current I _RN 303 and the detection current I _{DN are performed.} It can be said that the sensing time comparing the 310 is performed.

The channel unit 220 may include a comparator 230. The comparator 230 may include a voltage V _DN 314 of a node between the first switching element 307 and the first resistor 308. ) As a negative input and the reference voltage (V _REF ) 301 as a positive input to compare and output the two.

That is, the mirror current I _RN 303 and the detection current I _DN 310 which are substantially the same as the reference current I _REF 130 are not compared with the reference voltage V _REF 301. By comparing the voltage (V _DN ) 314 of the node between the first switching element 307 and the first resistor 308, the amount of current generated in the data line and the reference current (I _REF ) 130 are compared. It can be called a structure.

3 is a block diagram of a channel unit 220 including a data line unit 250, a precharging unit 240, and a comparison unit 230 according to an embodiment of the present invention.

The reference voltage (V _REF ) 301 generated by the reference current block unit is input to each channel unit, and the current radiation structure of the second transistor 304, that is, MP _N (N = 1,2,3...) As a (current mirror), it is possible to generate a mirror current (I _RN ) 303 (N = 1, 2, 3, ...) which is the same current as the reference current (I _REF ) 130 in each data line.

In this case, when the detection current source 310 to be detected, i.e., I _DN (N = 1, 2, 3, ...) 310 is generated in each data line, the first switching element 307 and the first resistor ( The voltage (V _DN ) 314 of the nodes between 308, that is, V _DN (N = 1,2,3...), Is the mirror current (I _RN ) 303 generated at the applied voltage terminal (V _DD ) 302. ) And a detection current source (I _DN ) 310 formed between the data line and the ground of each channel are connected in series. Therefore, the voltage bias of V _DN 314 is equal to that of the mirror current I _RN 303 that is current radiated through the second transistor MP _N 304 and the detection current source I _DN 310 generated in the data line. It is determined by the difference.

For example, when the current value of the detection current source (I _DN ) 310 is equal to the current value of the mirror current (I _RN ) 303, the voltage bias of the node V _DN 314 of the channel is determined by the reference current block portion. Because of the same conditions as the voltage bias, the voltage bias of V _DN 314 is equal to V _REF 301.

In addition, when the detection current source I _DN 310 is smaller than the mirror current I _RN 303, the voltage of the V _DN 314 is larger than the V _REF 301, on the contrary, the detection current source I _DN. When 310) is greater than the mirror current I _RN 303, the voltage of V _DN 314 is smaller than V _REF 301.

Thus, by comparing V _REF 301 and V _DN 314 through the voltage comparator (CMP _N ) 313 of each channel, the amount of current generated in the data line of each channel is large compared to the reference current. Smallness can be determined. Such a structure does not use the reference current in each channel, but converts the reference current into a voltage in the reference current block and supplies it to each channel in the form of a current source (MP _N ) through a current copy structure. There is an advantage that can be used for multiple channels due to the occurrence of.

4 is a graph showing a current comparison detection time according to the prior art.

Current comparators with multiple channels are easy for arrays of cells in basic units, such as non-volatile memory, fingerprint recognition, and touch screens, whereas data lines are connected to multiple cells, resulting in physical The longer the wiring, the greater the resistance, and the parasitic capacitance 309 may also increase. This causes a problem in that the response of the voltage V _DN , which is a form to be detected, to a change in the current I _DN of the data line is delayed.

That is, referring to FIG. 4, it can be seen that the response of the voltage V _DN of the node between the first switching element and the first resistor is very delayed with respect to the change in the detection current I _DN . Ie VIH _MAX And V _IL The interval between the sensing time (sensing time) and referring to the graph of Figure 5 it can be seen that the sensing time is significantly longer.

In this case, the delay time is proportional to the resistance and capacitance and inversely proportional to the amount of current. Therefore, in the case of detecting a fine current having a small absolute value of the detection current I _DN or the mirror current I _RN , this response delay may be more severe.

As shown in FIG. 4, a problem may occur in that an accurate data output is not obtained within one period (1-period) and data output is delayed until the next period.

That is, when the detected current source arranged on a data line continuous reference current (I _REF) compared to have a large current, the voltage V _DN is VH, which may be determined by the detected current (I _DN) and the mirror current (I _{RN) MAX} To go up. In this situation, when the current of the data line, that is, the detection current I _DN becomes smaller than the reference current I _REF , a relatively long time is required until V _DN is discharged to V _IL . This is indicated by the waveform indicated by the solid line in the waveform 420 of the voltage of the node between the first switching element and the first resistor.

On the contrary, when the detection current source continuously has a smaller current than the reference current I _REF , the voltage of V _DN is lowered to VL _MIN, which can be determined by the mirror current I _RN and the detection current I _DN , When the detection current I _DN becomes large in comparison with the reference current I _REF , a long time is required until the V _DN is charged to V _IH . This is indicated by the dotted line in the waveform 420 of the voltage of the node between the first switching element and the first resistor.

Here, the interval between V _IH and V _IL represents the minimum voltage range that the comparator can detect. In addition, VH _MAX is the maximum voltage that can be determined by the detection current (I _DN ) and the mirror current (I _RN ), and VL _MIN is the minimum voltage that can be determined by the detection current (I _DN ) and the mirror current (I _RN ). This can be said.

That is, when the input voltage of the section abnormal between V _IH and V _IL deviates from V _REF , the comparator output value represents a margin that can be regarded as a valid value.

5 is a graph showing a current comparison detection time through a precharging method according to an embodiment of the present invention.

In order to improve the response delay, which is a problem of the prior art, the present invention forms a unity gain buffer through which an input of a reference voltage V _{REF is} provided through an operational amplifier AMP _N to form a unity gain buffer. A method of pre-charging to a reference voltage (V _REF ) value is adopted.

In this case, the speed at which each data line is charged does not depend on the difference between the detection current I _DN and the mirror current I _RN , but rather on the driving capability of the operational amplifier AMP _N. Charging is possible.

During the period when the PRE signal, that is, the pulse signal of the precharging line is “High”, the data line is rapidly charged through the operational amplifier to the reference voltage V _REF , after which the detection current I _DN and the mirror current I _RN ) changes the voltage of V _DN . In this case, when V _DN changes only by the detectable section of the comparator CMP _N , the current of each data line can be compared. Therefore, the current comparison detection time can be significantly shortened through this precharge operation.

That is, referring to the graph of FIG. 5, since the V _DN is already charged to the reference voltage value by the precharging operation, the sensing time may be noticeably reduced.

6 is a block diagram illustrating a state in which a reference current block unit and a plurality of channel units are combined according to an embodiment of the present invention.

The present invention provides a high speed current comparator comprising at least two channel units 620 including a data line unit, a precharge unit, and a comparison unit in the reference current block unit 610.

In the present invention, a plurality of channel units 620 may be configured according to the number of cells and cell lines required for application applications such as nonvolatile memory, fingerprint recognition, and touch screen.

7 is an exemplary view of an application configured using a cell connected to a reference current block unit and a plurality of channel units according to an embodiment of the present invention.

Referring to FIG. 7, each cell 740 is assumed to be a microcurrent source that appears depending on 1/0 of the memory data, the curvature (height) of the fingerprint, or the presence or absence of a touch in a nonvolatile memory, fingerprint recognition, or touch screen. Can be.

In this case, each cell 740 arranged in a horizontal line performs on / off operation simultaneously, and scans each horizontal line through a row-decoder 730. . That is, the row-decoder 730 sequentially performs the operation of comparing and detecting the amount of data corresponding to the number of channels at the same time in each channel.

As described above, according to the present invention, data detection of a memory, fingerprint recognition pattern detection, or touched coordinates of a touch screen can be secured quickly and accurately in various application applications.

8 is a flow chart of a fast current comparison method according to an embodiment of the present invention.

According to the present invention, first, a step (s810) of generating a reference voltage V _REF in the reference current block unit is performed. That is, the input voltage V _DD is applied to the first transistor as the source, the drain is connected to the source of the reference current I _REF , and the gate and the drain are conducted so as to generate the reference voltage V _REF as the gate signal. It will be entered in the negative.

Thereafter, a pulse signal is generated in the precharging line, and the second switching device is turned on to precharge the data line to a reference voltage V _REF . That is, a unity gain buffer is formed by using the first operational amplifier receiving the reference voltage V _REF , and the data line is referenced for a predetermined time according to the operation of the first switching device and the second switching device. It charges in advance to the voltage (V _REF ) value.

Thereafter, a pulse signal is generated in the sensing timeline to turn on the first switching device to compare the mirror current I _RN with the detection current I _DN . Comparing the mirror current (I _RN ) and the detection current (I _DN ) (s830), the reference voltage (V _REF ) in the first comparator and the node of the node between the first switching element and the first resistor substantially in the first comparator By comparing the voltage V _DN , a comparison value between the mirror current I _RN and the detection current I _DN is calculated.

The present invention has been described above in connection with specific embodiments of the present invention, but this is only an example and the present invention is not limited thereto. Those skilled in the art can change or modify the described embodiments without departing from the scope of the present invention, and within the equivalent scope of the technical spirit of the present invention and the claims to be described below. Various modifications and variations are possible.

1 is a block diagram of a reference current block unit according to an embodiment of the present invention.

2 is a block diagram in which a reference current block unit and one channel unit are combined according to an embodiment of the present invention.

3 is a block diagram illustrating a channel unit including a data line unit, a precharge unit, and a comparison unit according to an embodiment of the present invention.

Figure 4 is a graph showing the current comparison detection time according to the prior art.

5 is a graph showing a current comparison detection time through a precharging method according to an embodiment of the present invention.

6 is a block diagram showing a state in which the reference current block unit and the plurality of channel units combined according to an embodiment of the present invention.

7 is an exemplary view of an application configured using a cell connected to a reference current block unit and a plurality of channel units according to an embodiment of the present invention.

8 is a flow chart of a fast current comparison method according to an embodiment of the present invention.

{Description of major symbols in the drawing}

110: input voltage terminal 120: first transistor

130: reference current source 140: reference voltage output terminal

210, 610, 710: reference current block 220, 620, 720: channel

230: comparison unit 240: precharge unit

250: data line unit 301: reference voltage

302: input voltage terminal 303: mirror current source

304: second transistor 305: first operational amplifier

306: second switching element 307: first switching element

308: first resistance 309: parasitic capacitance

310: detection current source 311: precharging line

312: sensing time line 313: first comparator

314: Voltage of the node between the first switching element and the first resistor

315: Output stage 410, 510 of the first comparator: waveform of the detection current

420, 520: waveform of the voltage of the node between the first switching element and the first resistor

430, 530: waveform of the output signal of the first comparator

510: waveform of the pulse signal of the precharging line 730: low decoder

740: cell

Claims (7)

An input voltage V _DD is applied as a source and a drain is connected to a reference current source generating a reference current I _REF . A first transistor is connected to the gate and the drain to generate a reference voltage V _REF as a gate signal. Reference current block unit comprising; A second transistor that receives the reference voltage V _REF at a gate to generate a mirror current I _RN of the reference current I _REF , and is sequentially connected in series with a drain of the second transistor; A data line unit including a switching device, a first resistor, and a detection current I _DN source; A precharge unit configured to receive the reference voltage V _REF to form a unity gain buffer to charge the data line with a reference voltage V _REF in advance for a predetermined time; And A comparator including a first comparator configured to take a voltage V _DN of the node between the first switching element and the first resistor as a negative input and to set the reference voltage V _REF as a positive input; High speed current comparator comprising a. The method of claim 1, wherein the precharge unit, A first operational amplifier configured to receive the reference voltage V _REF as a positive input and to which a negative input and an output signal are conducted; A second switching element for switching between an output signal of the first operational amplifier and a negative input terminal of the first comparator; A precharge that is connected to the second switching element and generates a pulse signal for a pre-charging time for pre-charging the data line to a reference voltage V _REF line; And A sensing time line connected to the first switching element and generating a pulse signal corresponding to a sensing time comparing a mirror current I _RN and a detection current I _DN ; High speed current comparator comprising a. The method of claim 1, wherein the comparison unit, Comparing the reference voltage (V _REF ) and the voltage (V _DN ) of the node between the first switching element and the first resistor to calculate a comparison value between the mirror current (I _RN ) and the detection current (I _DN ) High speed current comparator. The method of claim 1, wherein the first transistor or the second transistor, A high speed current comparator, which is a PMOS transistor. The method of claim 1, And at least two channel portions including the data line portion, the precharge portion, and the comparison portion. In the method of comparing the current using a high speed current comparator, Generating a reference voltage V _REF using the input voltage V _DD and the reference current I _REF in the reference current block unit; Generating a pulse signal from a precharging line of the precharge unit to turn on the second switching device to pre-charge a data line to the reference voltage V _REF value in advance; And The first switching device is turned on by generating a pulse signal in the sensing time line of the precharge unit, and the mirror current I _RN and the detection current I _DN of the reference current I _{REF are} compared in the comparison unit. Comparing the; Fast current comparison method comprising a. The method according to claim 6, Comparing the mirror current (I _RN ) and the detection current (I _DN ) in the comparison unit, In the first comparator including the comparator, a mirror current I _RN and a detection current I _DN are compared by comparing the reference voltage V _REF and the voltage V _DN of the node between the first switching element and the first resistor. A high speed current comparison method, characterized in that for calculating a comparison value of.

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