KR101153651B1 - Voltage regulator with multiple output - Google Patents

Abstract

PURPOSE: A multi voltage regulator is provided to output stable multi voltage by improving output regulations. CONSTITUTION: An error amplifier(300) amplifies differential voltage of reference voltage and feedback voltage. A first voltage regulator(100) controls a voltage level of a power source input terminal and outputs and outputs voltage to a first output terminal. A second voltage regulator(200) controls the voltage level of the power source input terminal and outputs the voltage to a second output terminal. A voltage detection part(400) detects voltage according to voltages of the first and second output terminals and provides the detected voltage as the feedback voltage.

Description

Multi Voltage Regulators {VOLTAGE REGULATOR WITH MULTIPLE OUTPUT}

The present invention relates to a voltage regulator capable of outputting a plurality of voltages.

In general, a regulator may be used to supply stable power in a power supply device that supplies power to an electronic device including a memory and an IC. When the electronic device needs a separate voltage according to the standby mode and the operation mode to reduce power consumption, the regulator may generate a multi-voltage to supply the required voltage.

Conventional multi-voltage regulators use an error amplifier and a plurality of MOSFETs. In addition, there is a method of using a switch at the output terminal to select the required voltage among the plurality of voltages output from the regulator.

However, such a conventional multi-voltage regulator has a problem that the output regulation may be worse when the input voltage fluctuates when generating the multi-voltage. In addition, the conventional method of using a switch at the output stage to select the required voltage in the regulator that can be used in the memory device, the voltage can drop close to zero at the moment of switching, the memory data can be deleted if the memory is applied There was a problem.

An object of the present invention is to solve the problems of the prior art, the present invention can improve the output regulation to output a stable multi-voltage, and also to reduce the voltage drop at the moment of selecting the required voltage multi-voltage regulator In providing.

A first technical aspect of the present invention includes an error amplifier for amplifying a difference voltage between a predetermined reference voltage and a voltage fed back; A first voltage controller connected to an output terminal of the error amplifier and outputting the first output terminal to a first output terminal by adjusting a voltage level of the power input terminal; And a second voltage controller connected to an output terminal of the error amplifier for adjusting a voltage level of the power input terminal and outputting the voltage to the second output terminal and a voltage detector for detecting a voltage from the voltage of the first output terminal and the voltage of the second output terminal. It is proposed a multi voltage regulator characterized by the above-mentioned.

A second technical aspect of the present invention includes an error amplifier for amplifying a difference voltage between a predetermined reference voltage and a voltage fed back; A first voltage controller connected to an output terminal of the error amplifier and outputting the first output terminal to a first output terminal by adjusting a voltage level of the power input terminal; A second voltage adjusting unit connected to an output terminal of the error amplifier and controlling a level of a voltage of the power input terminal and outputting the voltage to the second output terminal and a voltage detector detecting a voltage from the voltage of the first output terminal and the voltage of the second output terminal; A first reference voltage unit generating a first reference voltage supplied to the error amplifier; And a second reference voltage unit configured to generate a second reference voltage supplied to the error amplifier, and a reference voltage selector configured to select one of the first reference voltage and the second reference voltage and supply the selected reference voltage to the error amplifier. It is to propose a multi-voltage regulator.

In addition, the first and second reference voltage units are characterized by generating a constant voltage irrespective of the variation of the input terminal voltage.

According to the first and second technical aspects of the present invention, the first voltage regulator includes a p-channel MOSFET having a gate connected to an output terminal of an error amplifier, a source connected to a power input terminal, and a drain connected to a first output terminal. It features.

The second voltage regulator may include a p-channel MOSFET having a gate connected to the output terminal of the error amplifier, a source connected to the power input terminal, and a drain connected to the second output terminal.

The error amplifier may include an inverting input terminal for receiving a reference voltage; And an output terminal connected to the non-inverting input terminal to which the feedback voltage is input and the first voltage adjusting unit and the second voltage adjusting unit.

The voltage detector may further include: a first resistor having one end connected to a first output terminal and the other end connected to a connection node between the error amplifier and the second output terminal; And a second resistor connected to one end of the first resistor and connected to the other end of the ground, wherein the voltage of the connection node between the first resistor and the second resistor is a voltage fed back to the error amplifier.

In addition, the voltage detector includes a gate and a drain connected to a first output terminal, a gate and a drain connected to a source of a first n-channel MOSFET and a first n-channel MOSFET having a source connected to a connection node between an error amplifier and a second output terminal. And a second n-channel MOSFET having a source connected to ground, and a connection node between the first n-channel MOSFET and the second n-channel MOSFET is connected to an input terminal of the error amplifier.

According to the present invention, stable multi-voltage can be supplied even if the input voltage of the multi-voltage regulator changes. In addition, when the multi-voltage regulator supplies a plurality of voltages to the memory or the like, there is an effect that the memory data can be prevented from dropping rapidly due to a sudden drop in voltage at the required voltage selection moment.

1 is a block diagram of a multi-voltage regulator according to an embodiment of the present invention.
2 is a detail of FIG. 1;
3 is another example of the voltage detector of the multi-voltage regulator according to one embodiment of the present invention.
4 is a configuration diagram of a first reference voltage unit and a second reference voltage unit of a multi-voltage regulator according to an embodiment of the present invention.
5 is a detailed view of FIG. 4.
FIG. 6 is a timing chart showing a change in operating mode and a supply voltage according to an operation mode in a load to which a multi-voltage regulator according to an embodiment of the present invention supplies power. FIG.
7 is another example of a multi-voltage regulator according to one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

The present invention is not limited to the embodiments described, and the embodiments of the present invention are used to assist in understanding the technical spirit of the present invention. In the drawings referred to in the present invention, components having substantially the same configuration and function will use the same reference numerals.

1 and 2 are detailed views of a multi-voltage regulator according to an embodiment of the present invention.

Referring to FIG. 1, a multi-voltage regulator according to an embodiment of the present invention may include a first voltage controller 100, a second voltage controller 200, an error amplifier 300, and a voltage detector 400. Can be. Here, the first output terminal Out1, the voltage detector 400 and the error amplifier 300 may form a first feedback path, and the second output terminal Out2, the voltage detector 400 and the error amplifier 300 may be A second feedback path can be formed.

Referring to FIG. 2, the first voltage controller 100 may adjust the level of the voltage Vin of the power input terminal and output the voltage to the first output terminal Out1. In detail, the first voltage adjustor 100 has a gate connected to an output terminal of the error amplifier 300, a power input terminal and a source connected thereto, and a p having a drain connected to the first output terminal Out1 and the voltage detector 400. And a channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (hereinafter referred to as PMOS).

The second voltage controller 200 may adjust the level of the voltage Vin of the power input terminal to output the second voltage to the second output terminal Out2. In detail, the second voltage controller 200 may include a PMOS having a gate connected to an output terminal of the error amplifier 300, a power input terminal and a source connected thereto, and a drain connected to the second output terminal Out2.

The error amplifier 300 may control voltage regulation of the first voltage adjusting unit 100 and the second voltage adjusting unit 200. In detail, the error amplifier 300 includes an inverting input terminal for receiving a predetermined reference voltage, a non-inverting input terminal for inputting a voltage fed back to the first and second feedback loops, and a first voltage adjusting unit 100 and a second voltage adjusting unit. It may be an amplifier having an output connected to 200.

The voltage detector 400 may detect a voltage fed back to the error amplifier 300 from the voltage at the first output terminal Out1. In detail, the voltage detector 400 has one end connected to the first output terminal Out1, and the first resistor 410 and the first resistor having the other end connected to the connection node of the error amplifier 300 and the second output terminal Out2. It may include a second resistor 411 connected to one end of the 410 and the other end connected to the ground. Here, the voltage at the connection node of the first resistor 410, the second resistor 411, the error amplifier 300, and the second output terminal Out2 may be a voltage Vfd fed back to the error amplifier 300. have.

3 is another embodiment of the voltage detector 400 of the multi-voltage regulator according to the embodiment of the present invention.

Referring to FIG. 3, the voltage detector 400 includes a first n-channel in which a gate and a drain are connected to a first output terminal Out1, and a source is connected to a connection node of the error amplifier 300 and the second output terminal Out2. The MOSFET 430 (hereinafter referred to as NMOS) and a second NMOS 431 having a gate and a drain connected to a source of the first NMOS 430 and a source connected to the ground may be included. Here, the voltage Vfd fed back from the source of the first NMOS 430, the drain of the second NMOS 431, the node of the error amplifier 300, and the connection node of the second output terminal Out2 to the error amplifier 300. Can be

4 and 5 are configuration diagrams and detailed views of the first reference voltage unit 500 and the second reference voltage unit 510 of the multi-voltage regulator according to an embodiment of the present invention.

Referring to FIG. 4, the multi-voltage regulator according to the exemplary embodiment of the present invention may include a first reference voltage unit 500, a second reference voltage unit 510, and a reference voltage selector 600 to supply a reference voltage. It may include.

Referring to FIG. 5, the first reference voltage unit 500 generates the first reference voltage Vref1 from the voltage Vin of the power input terminal, and the second reference voltage unit 510 also includes the voltage Vin of the power input terminal. From the second reference voltage (Vref2) can be generated. Specifically, the first reference voltage unit 500 and the second reference voltage unit 510 may include a first PMOS M1, a second PMOS M2, a third NMOS M3, a fourth NMOS M4, and a resistor. It may include. The first PMOS M1 has a source connected to a power input terminal to which power is supplied, a gate is connected to a gate of the second PMOS M2, a drain is connected to a drain of the third NMOS M3, and The drains are connected to each other. One end of the resistor is connected in parallel to the first PMOS M1 and the power input terminal, and the other end is connected to the source of the second PMOS M2.

The second PMOS M2 has a source connected to the other end of the resistor, a gate connected to the gate of the first PMOS M1, and a drain connected to the drain of the fourth NMOS M4 and the first reference voltage Vref1. It is connected to the output terminal. The third NMOS M3 is connected to the drain of the first PMOS M1, the gate is connected to the gate of the fourth NMOS M4, and the source is connected to ground. The fourth NMOS M4 is connected to the terminal for outputting the drain of the second PMOS M2 and the first reference voltage Vref1, the gate is connected to the gate of the third NMOS M3, and the source is connected to ground. The drain and the gate are connected. The third NMOS M3 and the fourth NMOS M4 form a current mirror structure.

The reference voltage selector 600 may include a first reference voltage Vref1 generated by the first reference voltage unit 500 or a second generated by the second reference voltage unit 510 at the inverting terminal of the error amplifier 300. One of the reference voltages Vref2 may be selected and supplied.

FIG. 6 is a timing chart showing an operation mode in a load to which a multi-voltage regulator according to an embodiment of the present invention supplies power and a change in the supply voltage accordingly.

Referring to FIG. 6, the horizontal axis represents the change in the operation mode at the load, and the vertical axis represents the magnitudes of the operating voltage and the standby voltage. The first waveform VW1 is a voltage waveform in the multi-voltage regulator according to an embodiment of the present invention, and the second waveform VW2 is a voltage waveform in the multi-voltage regulator according to the prior art.

7 is another example of the multi-voltage regulator according to one embodiment of the present invention.

Referring to FIG. 7, the multi-voltage regulator according to an embodiment of the present invention may further include a third voltage adjuster 250. In this case, the voltage detector 400 may further include a third resistor 412 connected to a path through which the output of the third voltage regulator 250 is fed back in addition to the configuration shown in FIG. 2.

Like the first voltage controller 100 and the second voltage controller 200, the third voltage controller 250 may adjust the level of the voltage Vin at the power input terminal and output the same to the third output terminal Out3. have. In detail, the third voltage adjuster 250 may include a PMOS having a gate connected to the output terminal of the error amplifier 300, a source connected to the power input terminal, and a drain connected to the third output terminal Out3.

The voltage detector 400 may further include a third resistor having one end connected to the connection node between the other end of the second resistor and the third output terminal and having the other end connected to the ground.

Hereinafter, the operation and effect of the present invention will be described in detail with reference to the accompanying drawings.

A multi-voltage regulator according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

In FIG. 1, the first voltage controller 100 adjusts the voltage level of the power input terminal Vin according to the output of the error amplifier 300, and outputs a constant voltage to the first output terminal Out1.

Referring to FIG. 2, the first voltage regulator 100 is formed of a PMOS, which will be described below.

In FIG. 2, the source of the PMOS is supplied with a voltage Vin at a power input terminal, and the drain of the PMOS is connected to a connection node between the first output terminal Out1 and the voltage detector 400. The gate of the PMOS is connected to the output terminal of the error amplifier 300 and receives an amplified difference voltage between the feedback voltage Vfd and the reference voltage Vref.

For example, when the voltage of the power input terminal increases, the voltage of the first output terminal Out1 connected to the drain of the PMOS also increases. Accordingly, the feedback voltage Vfd detected by the voltage detector 400 also rises from the previous state. The feedback voltage Vfd input to the non-inverting terminal of the error amplifier 300 increases, but the reference voltage input to the inverting terminal is constant, so that the voltage difference between both terminals also increases.

Since the error amplifier 300 amplifies the voltage difference between the input terminals, the output of the error amplifier 300, which is input to the gate of the PMOS, also becomes larger than the previous state. As the gate voltage of the PMOS increases, the voltage of the first output terminal Out1 becomes lower than the previous state. Therefore, even if the voltage Vin of the power input terminal is changed, the voltage output to the first output terminal Out1 through the PMOS controlled by the error amplifier 300 may be a stable voltage without large variation.

The second voltage regulator 200 also stabilizes the voltage of the second output terminal Out2 similarly to the operation principle of the first voltage regulator 100 described above. This may be expressed as Equation 1 below.

[Equation 1]

In Equation 1, R1 represents a first resistor, R2 represents a second resistor, Vref represents a reference voltage, and 0.5 represents a constant value determined in consideration of feedback.

Referring to Equation 1, there is an effect that a stable output of a required level can be obtained by changing the values of the first resistor 410 and the second resistor 411 of the voltage detector 400.

Referring to FIG. 3, another example of the voltage detector 400 in the multi-voltage regulator according to the exemplary embodiment of the present invention will be described.

Referring to FIG. 3, a gate and a drain are connected to the first output terminal Out1 instead of the first resistor 410 and the second resistor 411 of FIG. 2, and the error amplifier 300 and the second output terminal Out2 are connected to each other. A first NMOS 430 having a source connected to the connection node and a second NMOS 431 having a gate and a drain connected to the source of the first NMOS 430 and a source connected to the ground.

That is, the voltage detector 400 of FIG. 3 has the effect of reducing the overall size of the regulator while obtaining the same effect by using the turn-on resistance of the transistor instead of the resistor.

A multi-voltage regulator according to an embodiment of the present invention will be described with reference to FIGS. 2 and 4.

2 and 4, it can be seen that the reference voltage input to the inverting terminal of the error amplifier 300 can be changed. The reference voltage input to the error amplifier 300 is selected from among the first reference voltage Vref1 generated by the first reference voltage unit 500 or the second reference voltage unit 510 generated by the second reference voltage unit 510. The reference voltage selector 600 is selected according to the operation mode or the standby mode of the load.

For example, the reference voltage generated by the first reference voltage unit 500 is 1 [V], the reference voltage generated by the second reference voltage unit 510 is 1.4 [V], and the first resistor of the voltage detector 400 is used. When 410 is 300K [Ohm] and the second resistor 411 is 600K [Ohm], the voltage at the first output terminal Out1 is 1.25 [V] in the first reference voltage Vref1 according to the above equation. The voltage at the second output terminal Out2 is 1.0 [V]. In the second reference voltage Vref2, the voltage at the first output terminal Out1 is 1.75 [V] and the voltage at the second output terminal Out2 is 1.4 [V].

In the above example, when the operating voltage is 1.8 [V] in the memory and the voltage required for memory data retention in the standby mode is 1 [V] or more, in the above example, the voltage is supplied to the memory at the first output terminal (Out1), In the operation mode, the reference voltage selector 600 may select the second reference voltage Vref2, and in the standby mode, the reference voltage selector 600 may select the first reference voltage Vref1. In this case, the second output terminal Out2 may supply a voltage to another block of the load. As described above, the multi-voltage regulator according to an embodiment of the present invention, while supplying voltage to different loads through a plurality of output stages, the voltage required for the operation mode and standby mode in accordance with the change of the reference voltage at one output terminal It can be supplied without a large voltage drop (to be described later in the description of FIG. 6).

Referring to FIG. 5, it can be seen that the first reference voltage unit 500 and the second reference voltage unit 510 have the same structure, and may be a band gap reference circuit having a current mirror structure.

When the reference voltage supplied from the circuit of FIG. 5 is calculated, it is expressed as Equation 2 below.

은 전자의 이동도,

는 정공의 이동도, Vthn은 NMOS의 문턱전압, Cox는 단위면적당 게이트 커패시턴스, W는 채널의 폭, L은 채널의 길이, R은 저항값을 의미한다.
here

Silver electron mobility,

Is the mobility of holes, Vthn is the threshold voltage of the NMOS, Cox is the gate capacitance per unit area, W is the width of the channel, L is the length of the channel, and R is the resistance value.

In Equation 2, the reference voltage generated by each reference voltage unit includes a resistance value, one end of which is connected in parallel to the first PMOS and the power input terminal, and the other end of which is connected to the source of the second PMOS, and the first, second PMOS, and the fourth. Since it depends on the width W and the length L of each channel of the NMOS, it can be seen that the first reference voltage Vref1 can be generated regardless of the voltage variation of the power input terminal.

Referring to FIG. 6, in an electronic device including a memory and the like, in a multi-voltage regulator according to an embodiment of the present invention and a multi-voltage regulator according to the related art, a voltage is changed and supplied according to a standby mode and an operation mode. Each waveform.

In the case of the voltage waveform VW2 of the prior art, a mode in the case of the voltage waveform VW1 by the multi-voltage regulator according to an embodiment of the present invention is compared with the voltage dropping close to zero at the switching moment for selecting the required voltage. It can be seen that the voltage drop is not large even if the supply voltage changes depending on the conversion.

That is, the conventional multi-voltage regulator selects the voltages output from the plurality of output terminals by using one reference voltage at the output terminal side, so that the voltage drop occurs largely because there is a time gap at the instant of switching at the output terminal.

In contrast, the multi-voltage regulator according to the exemplary embodiment of the present invention includes a plurality of reference voltage units as shown in FIG. 4, and supplies a voltage by changing a reference voltage unit in a required voltage in an operation mode or a standby mode. There is no need to select the output stage as shown in the figure so that the voltage drop does not occur much.

In particular, when the multi-voltage regulator according to an embodiment of the present invention supplies a multi-voltage to the memory, since the voltage does not drop significantly when changing the voltage, the problem of the prior art that the memory can be erased when changing the mode can be solved It works.

Referring to FIG. 7, it may further be seen that the third voltage adjuster 250 and the third resistor 412 of the voltage detector 400 may be further included, and a feedback loop may be formed to further implement a stable multi-voltage. have. The third voltage regulator 250 includes a PMOS having a gate connected to the output terminal of the error amplifier 300, a source connected to the power input terminal, and a drain connected to the third output terminal Out3. Like the first voltage adjusting unit 100 and the second voltage adjusting unit 200, the third voltage adjusting unit 250 adjusts the level of the voltage Vin of the power input terminal and outputs it to the third output terminal Out3.

The voltage detector 400 further includes a third resistor having one end connected to the connection node between the other end of the second resistor and the third output terminal and the other end connected to the ground. Therefore, although the voltage Vfd fed back to the error amplifier is different from the case of FIGS. 1 and 6, the operation principle is the same, and thus a detailed description thereof will be omitted.

As described above, according to the present invention, a stable multi-voltage can be supplied even if a change occurs in the input voltage of the multi-voltage regulator. In addition, when the multi-voltage regulator supplies a plurality of voltages to the memory or the like, there is an effect that the memory data can be prevented from dropping rapidly due to a sudden drop in voltage at the required voltage selection moment.

100: first voltage control unit 200: second voltage control unit
300: error amplifier 400: voltage detector
410: first resistance 411: second resistance
430: first n-channel MOSFET 431: second n-channel MOSFET
500: first reference voltage unit 510: second reference voltage unit
600: Reference voltage selector

Claims (13)

An error amplifier for amplifying a difference voltage between a predetermined reference voltage and an input feedback voltage;
A first voltage controller connected to an output terminal of the error amplifier and controlling a level of a voltage at a power input terminal and outputting the voltage to a first output terminal;
A second voltage controller connected to an output terminal of the error amplifier to adjust a level of the voltage at the power input terminal to output the second output terminal; And
The voltage detector detects a voltage according to the voltage at the first output terminal and the voltage at the second output terminal and provides the voltage as the feedback voltage.
Multi-voltage regulator comprising a. The method of claim 1, wherein the first voltage control unit,
A p-channel MOSFET having a gate connected to an output terminal of the error amplifier, a source connected to the power input terminal, and a drain connected to the first output terminal
Multi-voltage regulator comprising a. The method of claim 2, wherein the second voltage control unit,
A p-channel MOSFET having a gate connected to an output terminal of the error amplifier, a source connected to the power input terminal, and a drain connected to the second output terminal
Multi-voltage regulator comprising a. The method of claim 1, wherein the error amplifier,
An inverting input terminal for receiving the reference voltage;
A non-inverting input terminal to which the feedback voltage is input; And
An output terminal connected to the first and second voltage regulators
Multi-voltage regulator comprising a. The method of claim 1, wherein the voltage detector,
A first resistor having one end connected to the first output terminal and the other end connected to a connection node between the error amplifier and the second output terminal; And
A second resistor having one end connected to the first resistor and the other end connected to ground;
The voltage of the connection node between the first resistor and the second resistor is a voltage fed back to the error amplifier
Multi voltage regulator. The method of claim 1, wherein the voltage detector,
A first n-channel MOSFET having a gate and a drain connected to the first output terminal and a source connected to a connection node between the error amplifier and the second output terminal; And
A second n-channel MOSFET having a gate and a drain connected to the source of the first n-channel MOSFET and a source connected to ground;
A connection node between the first n-channel MOSFET and the second n-channel MOSFET is connected to an input terminal of the error amplifier
Multi voltage regulator. An error amplifier amplifying a difference voltage between a preset reference voltage and a feedback voltage;
A first voltage controller connected to an output terminal of the error amplifier and controlling a level of a voltage at a power input terminal and outputting the voltage to a first output terminal;
A second voltage controller connected to an output terminal of the error amplifier to adjust a level of the voltage at the power input terminal to output the second output terminal;
A voltage detector detecting a voltage based on the voltage at the first output terminal and the voltage at the second output terminal and providing the voltage as the feedback voltage;
A first reference voltage unit generating a first reference voltage supplied to the error amplifier;
A second reference voltage unit generating a second reference voltage supplied to the error amplifier; And
A reference voltage selector configured to select one of the first reference voltage and the second reference voltage and supply the selected reference voltage to the error amplifier;
Multi-voltage regulator comprising a. The method of claim 7, wherein the first and second reference voltage unit,
To generate a constant voltage irrespective of the change in the voltage of the power input terminal
Multi voltage regulator. The method of claim 7, wherein the first voltage control unit,
A p-channel MOSFET having a gate connected to an output terminal of the error amplifier, a source connected to the power input terminal, and a drain connected to the first output terminal
Multi-voltage regulator comprising a. The method of claim 9, wherein the second voltage control unit,
A p-channel MOSFET having a gate connected to an output terminal of the error amplifier, a source connected to the power input terminal, and a drain connected to the second output terminal
Multi-voltage regulator comprising a. The method of claim 7, wherein the error amplifier,
An inverting input terminal for receiving the reference voltage;
A non-inverting input terminal to which the feedback voltage is input; And
An output terminal connected to the first and second voltage regulators
Multi-voltage regulator comprising a. The method of claim 7, wherein the voltage detector,
A first resistor having one end connected to the first output terminal and the other end connected to a connection node between the error amplifier and the second output terminal; And
A second resistor having one end connected to the first resistor and the other end connected to ground;
The voltage of the connection node between the first resistor and the second resistor is a voltage fed back to the error amplifier
Multi voltage regulator. The method of claim 7, wherein the voltage detector,
A first n-channel MOSFET having a gate and a drain connected to the first output terminal and a source connected to a connection node between the error amplifier and the second output terminal; And
A second n-channel MOSFET having a gate and a drain connected to the source of the first n-channel MOSFET and a source connected to ground;
A connection node between the first n-channel MOSFET and the second n-channel MOSFET is connected to an input terminal of the error amplifier
Multi voltage regulator.

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