KR101149988B1 - Apparatus for adaptive TDM communication according to data input rate and method thereof - Google Patents

Abstract

A TMD communication method adaptive to the data input rate is provided. According to the present invention, the transmitting apparatus measures the first input speed of the first data input through the first port and the second input speed of the second data input through the second port, and measures the first data and the first. A frame including an input rate, second data, and a second input rate is generated and transmitted. As a result, the TMD communication adaptive to the data input rate is enabled, and thus, TDM communication can be supported for various devices without changing the design of the transmitting / receiving end.

TDM Networking, Clock Rate, Frames

Description

Apparatus for adaptive TDM communication according to data input rate and method

The present invention relates to a TDM communication method, and more particularly, to a TDM communication method that can be integratedly applied to various types of communication devices.

TDM (Time Division Multiplexing) is a method that allows multiple devices to use a communication line at the same time, and refers to a method of occupying a line by dividing the time used by multiple devices in order.

The transmitting end supporting the TDM multiplexes the devices to be connected thereto, and the receiving end demultiplexes the connected devices.

Meanwhile, the performance of devices to be connected to the transmitting / receiving end may be different. Specifically, the clock speeds used by the devices to be connected to the transmitting / receiving end may be different. The transmitting / receiving end is fixedly designed in consideration of the clock speed used by such devices to be connected.

Thus, the transmitting / receiving end is capable of multiplexing / demultiplexing only for the devices to be connected considered at the time of design. If the clock speed used by the device to be connected is not considered, then the transmit / receive end cannot support multiplexing / demultiplexing for that device.

The present invention has been made to solve the above problems, an object of the present invention, TDM communication apparatus that is adaptive to the data input rate, so as to support TDM communication for various devices without changing the design of the transmitting / receiving end and In providing a method.

According to the present invention for achieving the above object, a transmission device, a first port for receiving first data; A second port configured to receive second data; Measuring a first input speed of the first data input through the first port and a second input speed of the second data input through the second port, wherein the first data, the first input speed, A multiplexing unit generating a frame including the second data and the second input speed; And a transmitter for transmitting the frame generated by the multiplexer.

The apparatus may further include a clock generation unit configured to generate a main clock, wherein the multiplexing unit compares a first clock input with the first data through the first port to the main clock. A first framer measuring the first input speed and generating the first data in a first frame; And a second framer configured to measure the second input speed by comparing the second clock inputted with the second data through the second port with the main clock, and to generate the second data as a second frame. It is preferable to include.

The multiplexing unit may be configured to integrate a first frame generated from the first framer and a second frame generated from the second framer, and generate a frame by adding the first input speed and the second input speed. It may further include a framer.

The number of slots allocated to the first frame is determined by the first input speed, and the number of slots allocated to the second frame is determined by the second input speed.

The number of slots allocated to the first frame may be proportional to the first input speed, and the number of slots allocated to the first frame may be proportional to the second input speed.

In the frame, the second frame may be recorded after the first frame.

Preferably, the first input speed is recorded in a specific column of the frame, and the second input speed is recorded in another specific column of the frame.

The transmitting device may further include: a third port configured to receive third data; And a fourth port configured to receive fourth data, wherein the multiplexing unit includes a third input speed of the third data input through the third port and the fourth data input through the fourth port. Further measures a fourth input speed of the first data, the first input speed, the second data, the second input speed, the third data, the third input speed, the fourth data and the fourth data; It is desirable to create a frame with integrated input speed.

And, "first bandwidth + second bandwidth + third bandwidth + fourth bandwidth" is less than the bandwidth provided by the frame, the first bandwidth is the bandwidth required to transmit the first data, the second The bandwidth may be a bandwidth required for transmitting the second data, the third bandwidth may be a bandwidth required for transmitting the third data, and the fourth bandwidth may be a bandwidth required for transmitting the fourth data.

On the other hand, according to the present invention, a transmission method comprises the steps of: measuring a first input speed of first data input through a first port; Measuring a second input speed of second data input through the second port; Generating a frame including the first data, the first input speed, the second data, and the second input speed; And transmitting the generated frame.

On the other hand, the receiving apparatus according to the present invention, a receiving unit for receiving a frame; A demultiplexer configured to extract first data and second data from the frame based on a first input speed and a second input speed recorded in the frame received by the receiver; A first port through which the first data extracted by the demultiplexer is output; And a second port through which the second data extracted by the demultiplexer is output.

On the other hand, the receiving method according to the present invention comprises the steps of: receiving a frame; Extracting first data and second data from the frame based on the first input speed and the second input speed recorded in the frame received in the receiving step; Outputting first data extracted in the extraction step; And outputting second data extracted in the extracting step.

As described above, according to the present invention, the TDM communication adaptive to the data input rate is enabled, and thus, TDM communication can be supported for various devices without changing the design of the transmitting / receiving end.

Hereinafter, with reference to the drawings will be described the present invention in more detail.

1 to 3 are views provided to explain the concept of the present invention. 1 to 3, different time division multiplexing (TDM) networking situations are illustrated for explaining the concept of the present invention, which will be described in detail below.

One. TDM  Networking # 1

The network shown in Figure 1,

1) Data-1 (D1) input to the first port from the transmitting end TX is output to the first port of the receiving end RX,

2) Data-2 (D2) input to the second port at the transmitter is output to the second port of the receiver,

3) Data-3 (D3) input to the third port of the transmitting end is output to the third port of the receiving end,

4) The situation in which the data-4 (D4) input to the fourth port at the transmitting end is output to the fourth port of the receiving end is shown.

Meanwhile, as shown in FIG. 1,

1) The speed of clock-1 (C1) with respect to data-1 (D1) is Q ₁ ,

2) The speed of clock-2 (C2) with respect to data-2 (D2) is Q ₂ ,

3) The speed of clock-3 (C3) to data-3 (D3) is Q ₃ ,

4) When the speed of clock-4 (C4) with respect to data-4 (D4) is Q ₄ ,

You can see that "Q ₁ > Q ₂ > Q ₃ > Q ₄ " is true.

Specifically, they satisfy the following equation (1).

Q ₁ = (4/3) * Q ₂ = (4/2) * Q ₃ = (4/1) * Q ₄

That is, the speed Q ₁ of the clock-1 (C1) is

a) 1.33 (= 4/3) times the speed Q ₂ of clock-2 (C2),

b) 2 (= 4/2) times the speed (Q ₃ ) of clock-3 (C3),

c) 4 (= 4/1) times the speed Q ₄ of the clock-4 (C4).

As shown in FIG. 1, in the frame F transmitted from the transmitting end TX to the receiving end RX, 1) slots allocated to data-1 (D1) are 40% of all slots, and 2) data. -Slots allocated to 2 (D2) are 30% of all slots, 3) Slots allocated to data-3 (D3) are 20% of all slots, 4) Slots allocated to data-4 (D4) It can be seen that 10% of the total slots.

In other words, 1) 40% of the total bandwidth is allocated for Data-1 (D1), 2) 30% of the total bandwidth is allocated for Data-2 (D2), and 3) Data-3 (D3). For example, 20% of the total bandwidth is allocated, and 4) 10% of the total bandwidth is allocated for the data-4 (D4).

As such, bandwidth allocation (i.e., allocation of slots) includes the speeds Q ₁ , Q ₂ , of clocks C 1, C 2, C 3, C 4 for the input data D 1, D 2, D 3, D 4. Q ₃ , Q ₄ ). That is, a lot of bandwidth is allocated for data having a high clock speed, and a little bandwidth is allocated for data having a slow clock speed.

2. TDM  Networking # 2

In the network shown in FIG. 2,

1) The speed of clock-1 (C1) with respect to data-1 (D1) is Q ₁ ,

2) The speed of clock-2 (C2) with respect to data-2 (D2) is Q ₂ ,

3) The speed of clock-3 (C3) to data-3 (D3) is Q ₃ ,

4) When the speed of clock-4 (C4) with respect to data-4 (D4) is Q ₄ ,

You can see that "Q ₃ > Q ₁ > Q ₂ > Q ₄ " is true.

Specifically, they satisfy the following equation (2).

Q ₃ = (4/3) * Q ₁ = (4/2) * Q ₂ = (4/1) * Q ₄

That is, the speed Q ₃ of the clock-3 (C3) is

a) 1.33 (= 4/3) times the speed Q ₁ of clock-1 (C1),

b) 2 (= 4/2) times the speed Q ₂ of clock-2 (C2),

c) 4 (= 4/1) times the speed Q ₄ of the clock-4 (C4).

On the other hand, as shown in Figure 2, in the frame (F) transmitted from the transmitting end TX to the receiving end (RX), 1) the slot allocated to data-1 (D1) is 30% of the total slot, 2) Slots allocated to data-2 (D2) are 20% of all slots, 3) slots allocated to data-3 (D3) are 40% of all slots, 4) slots allocated to data-4 (D4) It can be seen that is 10% of the total slot.

In other words, 1) 30% of the total bandwidth is allocated for Data-1 (D1), 2) 20% of the total bandwidth is allocated for Data-2 (D2), and 3) Data-3 (D3). For example, 40% of the total bandwidth is allocated, and 4) 10% of the total bandwidth is allocated for the data-4 (D4).

Even in the TDM networking shown in FIG. 2, this bandwidth allocation (ie, allocation of slots) is equivalent to clocks C1, C2, C3, C4 for incoming data D1, D2, D3, D4. Is based on the speeds of Q ₁ , Q ₂ , Q ₃ , and Q ₄ . That is, a lot of bandwidth is allocated for data having a high clock speed, and a little bandwidth is allocated for data having a slow clock speed.

3. TDM  Networking # 3

3 illustrates a situation in which there is no data input to the third port of the transmitting end TX and no data output to the third port of the receiving end RX.

In the network as shown in Figure 3,

1) The speed of clock-1 (C1) with respect to data-1 (D1) is Q ₁ ,

2) The speed of clock-2 (C2) with respect to data-2 (D2) is Q ₂ ,

3) When the speed of clock-4 (C4) to data-4 (D4) is Q ₄ ,

You can see that the relationship of "Q ₂ > Q ₄ > Q ₁ " holds true.

Specifically, they satisfy the following equation (3).

Q ₂ = (4/3) * Q ₄ = (4/1) * Q ₁

That is, the speed Q ₂ of the clock-2 (C2) is

a) 1.33 (= 4/3) times the speed (Q ₄ ) of clock-4 (C4),

b) 4 (= 4/1) times the speed (Q ₁ ) of clock-1 (C1) _.

Meanwhile, as shown in FIG. 3, in the frame F transmitted from the transmitting end TX to the receiving end RX, 1) the slot allocated to the data-1 (D1) is 10% of the total slot, and 2) the data. Slots allocated to -2 (D2) are 40% of the total slots, 3) Slots allocated to data-4 (D4) are 30% of the total slots, and 4) Null (N) at the last 20% of the total slots. You can see that this is filled.

The reason why Null (N) is filled in the last 20% of the entire slots is that there is no data input to the third port at the transmitting end, and a surplus occurs in the frame (F).

Meanwhile, 1) 10% of the total bandwidth is allocated for Data-1 (D1), 2) 40% of the total bandwidth is allocated for Data-2 (D2), and 3) for Data-4 (D4). 30% of the total bandwidth is allocated.

Even in the TDM networking shown in FIG. 3, bandwidth allocation (ie slot allocation) is the speed Q ₁ , Q ₂ of the clocks C ₁ , C 2, C 4 for the incoming data D 1, D 2, D 4. , Q ₄ ). That is, a lot of bandwidth is allocated for data having a high clock speed, and a little bandwidth is allocated for data having a slow clock speed.

4. of input data Clock  Compare Bandwidth Allocation by Speed

In Fig. 4, the bandwidth allocation results in the TDM networking shown in Figs. As shown in FIG. 4, it can be seen that bandwidth allocation is performed based on the speeds Q ₁ , Q ₂ , Q ₃ and Q _{4 of} the clocks C1, C2, C3 and C4 input through the port. have.

In addition, since the TDM networking according to the present invention allocates slots to the ports according to the allocated bandwidth, the speeds Q ₁ and Q _{2 of} the clocks C1, C2, C3, and C4 input to the respective ports are allocated. , Q ₃ , Q ₄ ), it can be said that the configuration of the frame (F) is different.

How the structure of the frame F is different is shown in the center portion of FIGS. 1 to 3, and thus a detailed description thereof will be omitted.

5. Sender ( TX )

Hereinafter, the transmitting end TX capable of performing the TDM networking shown in FIGS. 1 to 3 will be described in detail with reference to FIGS. 5 and 6.

5 is a detailed block diagram of a transmitter according to an embodiment of the present invention. As shown in FIG. 5, the transmitter 100 according to the present embodiment includes input ports 111, 112, 113, and 114, an OSC 120, a MUX 130, and an optical transmitter 140. do.

The input ports 111, 112, 113, and 114 receive a clock and data together. Specifically,

1) The input port-1 111 receives the clock-1 (C1) and the data-1 (D1) together,

2) Input port-2 112 receives clock-2 (C2) and data-2 (D2) together,

3) Input port-3 113 receives clock-3 (C3) and data-3 (D3) together,

4) Input port-4 114 receives clock-4 (C4) and data-4 (D4) together.

The OSC 120 generates a main clock C and applies it to the MUX 130 and the optical transmitter 140. The main clock C is implemented to be faster than the clocks C1, C2, C3, and C4 input through the input ports 111, 112, 113, and 114.

The MUX 130 measures the speeds Q ₁ , Q ₂ , Q ₃ , Q _{4 of} the clocks C1, C2, C3, C4 input through the input ports 111, 112, 113, 114. The frame F including the data D1, D2, D3, and D4 input through the input ports 111, 112, 113, and 114 is generated and output.

Upon generation of the frame F, the MUX 130 is based on the speeds Q ₁ , Q ₂ , Q ₃ , Q ₄ of the clocks C1, C2, C3, C4, and the data D1, D2, D3, D4) are arranged. In addition, the MUX 130 stores the speeds Q ₁ , Q ₂ , Q ₃ and Q ₄ of the measured clocks C1, C2, C3 and C4 in the frame F. FIG.

Detailed description of the MUX 130 will be described later in detail with reference to FIG.

The optical transmitter 140 converts the frame F output from the MUX 130 into an optical signal and transmits the converted optical signal to the receiver RX.

Hereinafter, the above-described MUX 130 will be described in detail with reference to FIG. 6. FIG. 6 is a detailed block diagram of the MUX 130 shown in FIG.

As shown in FIG. 6, MUX 130 includes framers 131-1, 131-2, 131-3, and 131-4, an integrated-framer 132, and a scrambler 133.

Framers 131-1, 131-2, 131-3, and 131-4 are speeds of clocks C1, C2, C3, and C4 input through input ports 111, 112, 113, and 114. Measure (Q ₁ , Q ₂ , Q ₃ , Q ₄ ). In measuring the clock speed, the framers 131-1, 131-2, 131-3, and 131-4 use the main clock C generated by the OSC 120. Specifically,

1) Framer-1 (131-1) is the rate (Q ₁₎ of the clock 1 (C1) compared to the main clock (C) of the clock 1 (C1) which is input through the input port 1 (111) Measure it,

2) Framer-2 (131-2) compares clock-2 (C2) input through input port-2 (112) with main clock (C) to determine the speed (Q ₂ ) of clock-2 (C2). Measure,

3) framer-3 (131-3) is the speed (Q ₃₎ of the clock-3 (C3) as compared with the main clock (C) a clock-3 (C3), which is input through the input port 3 (113) Measure it,

4) framer-4 (131-4) is the speed (Q ₄₎ of the clock 4 (C4) as compared with the main clock (C) a clock 4 (C4), which is input through the input port 4 (114) Measure

Framers 131-1, 131-2, 131-3, and 131-4 integrate information about measured clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ -framer 132. To pass.

The framers 131-1, 131-2, 131-3, and 131-4 frame the data frames generated by framing the data D1, D2, D3, and D4 using the main clock C. FIG. Transfer to the integrated-framer 132. Specifically,

1) Framer-1 131-1 frames Frame Data-1 (D1) to generate Frame-1 (F1),

2) Framer-2 131-2 frames Frame-2 (D2) to generate Frame-2 (F2),

3) Framer-3 (131-3) frames Data-3 (D3) to generate Frame-3 (F3),

4) Framer-4 131-4 frames Data-4 (D4) to generate Frame-4 (F4).

Framers 131-1, 131-2, 131-3, and 131-4 deliver the generated frames F1, F2, F3, and F4 to the unified-framer 132, respectively.

The integrated-framer 132 is the clock speeds Q ₁ , Q ₂ , Q ₃ , Q ₄ and data D1 received from the framers 131-1, 131-2, 131-3, and 131-4. The frame F is generated by using D2, D3, and D4. The process of generating the frame F is as follows.

First, the integrated-framer 132 stores the frame-bit " 1110111001 ", clock speeds Q ₁ , Q ₂ , Q ₃ , Q ₄ and stuffing-bits in the frame F to be generated. .

The position on frame F where the frame bit " 1110111001 ", clock speeds Q ₁ , Q ₂ , Q ₃ , Q ₄ and stuffing-bits are contained is determined.

7 shows the format of the frame F. As shown in FIG. As shown in FIG.

1) In each row of the first column of the frame F, the frame-bit " 1110111001 "

2) In each row of the tenth column except the last row of the frame F, the speed Q ₁ of the clock-1 (C1) is recorded as 9 bits,

3) In the last row of the tenth column of frame F, the stuffing-bit CBIT ₁ for frame-1 F1 is stored.

4) In each row of the 19th column except the last row of the frame F, the speed Q ₂ of the clock-2 (C2) is recorded as 9 bits,

5) In the last row of the 19th column of frame F, the stuffing-bit CBIT ₂ for frame-2 F2 is stored.

6) In each row of the 28th column except the last row of the frame F, the speed Q ₃ of the clock-3 (C3) is recorded as 9 bits,

7) The last row of the 28th column of frame F contains the stuffing-bit CBIT ₃ for frame-3 F3,

8) In each row of the 37th column except the last row of the frame F, the speed Q ₄ of the clock-4 (C4) is recorded as 9 bits,

9) In the last row of the 37th column of frame F, the stuffing-bit CBIT ₄ for frame-4 F4 is stored.

In addition, the unified-framer 132 records frame-1 (F1), frame-2 (F2), frame-3 (F3), and frame-4 (F4) in order in the frame F, Integrate the frames F1, F2, F3, F4.

Accordingly, in frame F, frame-2 (F2) is recorded after frame-1 (F1), frame-3 (F3) is recorded after frame-2 (F2), and frame-3 (F3). ) Frame-4 (F4) is recorded after.

In the frame F shown in FIG. 7,

1) each row of the second to ninth columns,

2) each row of columns 11 to 18,

3) each row in column 20 to column 27,

4) each row in columns 29 to 36 and

5) In columns 38 to 45,

Data of the frames F1, F2, F3, and F4 are stored in the fast row, and are stored in the same row in the fast row.

Meanwhile, bandwidths allocated to the frames F1, F2, F3, and F4 (that is, slots allocated) are determined based on the clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ . Specifically,

1) Slots allocated to frame-1 (F1) are proportional to the speed Q ₁ of clock-1 (C1),

2) Slots allocated to frame-2 (F2) are proportional to the speed Q ₂ of clock-2 (C2),

3) Slots allocated to frame-3 (F3) are proportional to the speed Q ₃ of clock-3 (C3),

4) Slots allocated to frame-4 (F4) are proportional to the speed Q ₄ of clock-4 (C4).

On the other hand, the clock speeds (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are expressed in multiples of "1 / (total number of bits of frame (F)) * (speed of main clock)", respectively. It is complemented by stuffing bits. Specifically,

1) The speed Q ₁ of clock-1 (C1) is complemented by CBIT ₁ ,

2) The speed Q ₂ of clock-2 (C2) is complemented by CBIT ₂ ,

3) The speed (Q ₃ ) of clock-3 (C3) is complemented by CBIT ₃ ,

4) The speed Q ₄ of clock-4 (C4) is complemented by CBIT ₄ .

Thus, in a TDM networking situation as shown in FIG. 1, the data in frame F is stored as shown in FIG. 8. In Figure 8,

1) Slots marked with "D1" are slots containing data-1 (D1) constituting frame-1 (F1),

2) Slots marked with "D2" are slots in which data-2 (D2) constituting frame-2 (F2) is stored.

3) Slots marked with "D3" are slots containing data-3 (D3) constituting frame-3 (F3),

4) The slots labeled "D4" are slots in which the data-4 (D4) constituting the frame-4 (F4) is stored.

Meanwhile, the scrambler 133 illustrated in FIG. 6 scrambles the frame F generated by the integrated-framer 132, and transmits the scrambled frame F to the optical transmitter 140.

6. Transmission process

Up to now, the TDM data transmission method performed in the transmission apparatus 100 described above is summarized as shown in FIG. 9. 9 is a flowchart provided to explain a TDM data transmission method according to another embodiment of the present invention.

As shown in FIG. 9, first, the framers 131-1, 131-2, 131-3, and 131-4 use the main clock C generated by the OSC 120 to input the input ports ( The speeds Q ₁ , Q ₂ , Q ₃ and Q _{4 of} the clocks C1, C2, C3 and C4 input through the 111, 112, 113 and 114 are respectively measured (S310).

Information about the clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ measured in step S310 is transferred to the integrated-framer 132.

In addition, the framers 131-1, 131-2, 131-3, and 131-4 may output data D1, D2, D3, and D4 input through the input ports 111, 112, 113, and 114. Framed to generate the frames (F1, F2, F3, F4) (S320).

Frames F1, F2, F3, and F4 generated in operation S320 are also transferred to the integrated framer 132.

Then, the integrated-framer 132 uses the clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ measured in step S310 and the frames F1, F2, F3, and F4 generated in step S320. A frame F is generated. A detailed procedure is shown in steps S330 to S350.

That is, the unified-framer 132 stores the frame-bit “1110111001”, clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ and stuffing-bits in the frame F (S330).

In addition, the integrated-framer 132 determines slots to include the frames F1, F2, F3, and F4 based on the clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ (S340). . The slots that will contain the frame (ie the bandwidth for the frame) are proportional to the speed of the clock for the data contained in that frame.

Then, the integrated-framer 132 assigns Frame-1 (F1), Frame-2 (F2), Frame-3 (F3), and Frame-4 (F4) to Frame F according to the determination result of step S340. The frames F1, F2, F3, and F4 are integrated in order (S350).

Then, the scrambler 133 scrambles the frame F generated by the integration-framer 132 (S360).

Thereafter, the optical transmitter 140 converts the scrambled frame F from the scrambler 133 into an optical signal and transmits the converted optical signal to the receiving terminal RX (S370).

7. Recipient RX )

Hereinafter, the receiving end TX capable of performing the TDM networking shown in FIGS. 1 to 3 will be described in detail with reference to FIGS. 10 and 11.

10 is a detailed block diagram of a receiving apparatus according to an embodiment of the present invention. As shown in FIG. 10, the receiver 200 according to the present embodiment includes an optical receiver 210, an OSC 220, a DEMUX 230, and output ports 241, 242, 243, and 244. do.

The optical receiver 210 receives the frame of the optical signal transmitted by the optical transmitter 140 of the transmission apparatus 100, converts the optical signal into an electrical signal, and transmits the converted frame to the DEMUX 230.

The OSC 220 generates a main clock C and applies the same to the DEMUX 230 and the light receiver 210. The main clock C is preferably implemented at the same speed as the OSC 120 of the transmitter 100.

On the other hand, it is possible to implement by receiving the main clock (C) from the transmitting device 100, in which case the OSC 220 of the receiving device 200 can be omitted.

The DEMUX 230 separates the data D1, D2, D3, and D4 from the frame F input from the optical receiver 210, and outputs the separated data D1, D2, D3, and D4 to the output ports. (241, 242, 243, 244) respectively.

The DEMUX 230 separates each of the data D1, D2, D3, and D4 according to the clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ from the frame F, and transmits the DEMUX 230 to the DEMUX 230. A detailed description thereof will be provided later with reference to FIG. 11.

The output ports 241, 242, 243, and 244 output data D1, D2, D3, and D4 received from the DEMUX 230 to connected devices, respectively. Specifically,

1) Output port-1 241 outputs data-1 (D1) to the connected device-1 (not shown),

2) Output port-2 242 outputs data-2 (D2) to the connected device-2 (not shown),

3) Output port-3 (243) outputs data-3 (D3) to connected device-3 (not shown),

4) Output port-4 244 outputs data-4 (D4) to the connected device-4 (not shown).

Hereinafter, the above-described DEMUX 230 will be described in detail with reference to FIG. 11. FIG. 11 is a detailed block diagram of the DEMUX 230 shown in FIG. 10.

As shown in FIG. 11, the DEMUX 230 includes a descrambler 231, an integrated-reframer 232, and leaframers 233-1, 233-2, 233-3, and 233-4. do.

The descrambler 231 descrambles the scrambled frame F received from the optical receiver 210, and delivers the descrambled frame F to the integrated-reframer 232.

The integrated-reframer 232 extracts the clock speeds Q ₁ , Q ₂ , Q ₃ and Q ₄ contained in the frame F received from the descrambler 231. The integrated-reframer 232 divides the frame F into frames F1, F2, F3, and F4 by referring to the extracted clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ . .

As described above, since the position on the frame F where the clock speeds Q ₁ , Q ₂ , Q ₃ , Q ₄ are stored is determined, the integrated-reframer 232 may use the clock speeds in the frame F. It is possible to extract (Q ₁ , Q ₂ , Q ₃ , Q ₄ ).

On the other hand, the frame F (F1), Frame-2 (F1), Frame-2 (F2), Frame-3 (F3) and Frame-4 (F4) has been described in accordance with the following principles.

First, it has been described above that frames F (F1), frames-2 (F2), frames-3 (F3), and frames-4 (F4) are sequentially stored in the frame F. FIG. That is, in frame F, frame-2 (F2) is recorded after frame-1 (F1), frame-3 (F3) is recorded after frame-2 (F2), and frame-3 (F3) Frame-3 (F3) is recorded later, and frame-4 (F4) is recorded after frame-3 (F3).

Secondly, the slots allocated to the frames F1, F2, F3, and F4 in the frame F have been described above based on the clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ . Specifically,

1) The number of slots allocated to the frame-1 (F1) is proportional to the speed Q ₁ of the clock-1 (C1),

2) the number of slots allocated to frame-2 (F2) is proportional to the speed Q ₂ of clock-2 (C2),

3) The number of slots allocated to the frame-3 (F3) is proportional to the speed Q ₃ of the clock-3 (C3),

4) The number of slots allocated to the frame-4 (F4) is proportional to the speed Q ₄ of the clock-4 (C4).

Since frame F has been generated on the basis of the above principle, the integrated-reframer 232 refers to the clock speeds Q ₁ , Q ₂ , Q ₃ , Q ₄ and selects frame F into frames ( F1, F2, F3, F4) can be separated.

Meanwhile, the integrated-reframer 232 transfers the separated frames F1, F2, F3, and F4 to the leaf reamers 233-1, 233-2, 233-3, and 233-4, respectively.

The leaf reamers 233-1, 233-2, 233-3, and 233-4 have data D1, D2, and D2 in the frames F1, F2, F3, and F4 received from the integrated-reframer 232. D3 and D4 are extracted and delivered to output ports 241, 242, 243 and 244. Specifically,

1) The leaframer-1 233-1 extracts the data-1 (D1) from the frame-1 (F1) and delivers it to the output port-1 (241).

2) Releafer-2 (233-2) extracts data-2 (D2) from frame-2 (F2) and forwards it to output port-2 (242),

3) Leaf Reamer-3 (233-3) extracts Data-3 (D3) from Frame-3 (F3) and forwards it to Output Port-3 (243),

4) The leaframer-4 233-4 extracts the data-4 (D4) from the frame-4 (F4) and transfers the data-4 (D4) to the output port-4 (244).

8. Receiving Process

Up to now, the TDM data receiving method performed in the receiving apparatus 200 described above is illustrated in FIG. 12. 12 is a flowchart provided to explain a TDM data receiving method according to another embodiment of the present invention.

As shown in FIG. 12, first, the optical receiver 210 receives a frame F of an optical signal transmitted by the optical transmitter 140 of the transmission apparatus 100, converts the frame F into an electrical signal, and converts the electrical signal into an electrical signal. The transmitted frame is transmitted to the DEMUX 230 (S410).

Then, the descrambler 231 provided in the DEMUX 230 descrambles the scrambled frame F received from the optical receiver 210, and delivers the descrambled frame F to the integrated-reframer 232. (S420).

The integrated-reframer 232 extracts clock speeds Q ₁ , Q ₂ , Q ₃ and Q ₄ contained in the frame F received from the descrambler 231 (S430). The integrated-reframer 232 divides the frame F into frames F1, F2, F3, and F4 by referring to the extracted clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ . (S440).

Then, the leaf reamers 233-1, 233-2, 233-3, and 233-4 have the data D1, in the frames F1, F2, F3, and F4 received from the integrated-reframer 232. D2, D3, and D4 are extracted and transferred to the output ports 241, 242, 243, and 244 (S450).

The output ports 241, 242, 243, and 244 are data D1, D2, and D3 received from the leaf reamers 233-1, 233-2, 233-3, and 233-4 provided in the DEMUX 230. , D4) is output to connected devices (not shown) (S460).

9. Examples of applicable networks

13 is a diagram illustrating a network to which the present invention is applicable. In FIG. 13, 1) a computer 11, a voice telephone 12, a photographing apparatus 13 and a wireless repeater 14 are connected to four input ports provided in the transmitting apparatus 100 so as to communicate with each other. 4) illustrates a network in which the computer 21, the voice phone 22, the display device 23, and the wireless repeater 24 are connected to four output ports provided in the reception device 200.

In FIG. 13, the transmitting apparatus 100 multiplexes the computer 11, the voice telephone 12, the photographing apparatus 13, and the wireless repeater 14 according to the transmitting method shown in FIG. When generating the frame F for multiplexing, the transmitting apparatus 100 varies the data arrangement in the frame F according to the clock speeds of the connected devices.

In addition, the reception apparatus 200 demultiplexes the computer 21, the voice telephone 22 display apparatus 23, and the wireless repeater 24 according to the reception method illustrated in FIG. 12.

8. Other

In the above embodiment, a transmission / reception device provided with four input / output ports is assumed, but the number thereof may be modified.

In addition, the clock speeds Q ₁ , Q ₂ , Q ₃ , and Q ₄ mentioned in the above embodiment may be determined by the following methods: 1) In the transmitting apparatus 100, the input speeds of the data D1, D2, D3, and D4 may be used. 2) The reception apparatus 200 corresponds to output speeds of the data D1, D2, D3, and D4. Thus, the clock speeds Q ₁ , Q ₂ , Q ₃ , Q ₄ can be solved at the input / output speeds of the data D1, D2, D3, D4.

Meanwhile, the bandwidth required to transmit data-1 (D1) is "B1", the bandwidth required to transmit data-2 (D2) is "B2", and the bandwidth required to transmit data-3 (D3) is "B3", When the bandwidth required for transmitting data-4 (D4) is "B4", and the total bandwidth that a transmitting / receiving device can provide is "B", it is assumed that "B1 + B2 + B3 + B4 <B" is established. desirable.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

1 to 3 is a view provided to explain the concept of the present invention,

4 is a diagram summarizing bandwidth allocation results in the TDM networking shown in FIGS. 1 to 3;

5 is a detailed block diagram of a transmitting apparatus according to an embodiment of the present invention;

FIG. 6 is a detailed block diagram of the MUX shown in FIG. 5;

7 is a diagram showing a format of a frame applicable to the present invention;

8 shows a frame F in a TDM networking situation as shown in FIG. 1, FIG.

9 is a flowchart provided to explain a TDM data transmission method according to another embodiment of the present invention;

10 is a detailed block diagram of a receiving apparatus according to an embodiment of the present invention;

12 is a flowchart provided to explain a TDM data receiving method according to another embodiment of the present invention, and

13 is a diagram illustrating a network to which the present invention is applicable.

Claims (10)

A first port for receiving first data; A second port configured to receive second data; Measuring a first input speed of the first data input through the first port and a second input speed of the second data input through the second port, wherein the first data, the first input speed, A multiplexing unit generating an integrated frame including the second data and the second input speed; And And a transmitter configured to transmit the integrated frame generated by the multiplexer. In the integrated frame, The position at which the first input speed and the second input speed are recorded is determined, The number of slots allocated to the first frame generated from the first data is determined by the first input speed. The number of slots allocated to the second frame generated from the second data is determined by the second input speed. The first frame and the second frame are recorded in order, The first frame and the second frame may be separated from the integrated frame with reference to the first input speed and the second input speed. The sum of the number of slots allocated to the first frame and the number of slots allocated to the second frame is equal to or less than the total slots of the integrated frame. Nulls are filled in slots that are not allocated to the first frame and the second frame in the integrated frame. And the null is filled after the first frame and the second frame. The method of claim 1, Further comprising: a clock generator for generating a main clock; The multiplexing unit, A first framer for measuring the first input speed by comparing a first clock inputted with the first data through the first port with the main clock, and generating the first data as a first frame; And A second framer for measuring the second input speed by comparing the second clock inputted with the second data through the second port with the main clock and generating the second data in a second frame; Transmitting apparatus comprising a. 3. The method of claim 2, The multiplexing unit, An integrated-framer for integrating a first frame generated in the first framer and a second frame generated in the second framer and adding the first input speed and the second input speed to generate the integrated frame; The transmitting device further comprises. delete delete The method of claim 1, The first input speed is recorded in a specific column of the integrated frame, And the second input rate is recorded in another specific column of the integrated frame. delete Measuring a first input speed of first data input through the first port; Measuring a second input speed of second data input through the second port; Generating an integrated frame including the first data, the first input rate, the second data, and the second input rate; And Transmitting the generated aggregated frame; In the integrated frame, The position at which the first input speed and the second input speed are recorded is determined, The number of slots allocated to the first frame generated from the first data is determined by the first input speed. The number of slots allocated to the second frame generated from the second data is determined by the second input speed. The first frame and the second frame are recorded in order, The first frame and the second frame may be separated from the integrated frame with reference to the first input speed and the second input speed. The sum of the number of slots allocated to the first frame and the number of slots allocated to the second frame is equal to or less than the total slots of the integrated frame. Nulls are filled in slots that are not allocated to the first frame and the second frame in the integrated frame. The null is filled after the first frame and the second frame. Receiving unit for receiving the integrated frame; A demultiplexer configured to extract first data and second data from the integrated frame based on a first input speed and a second input speed recorded in the integrated frame received by the receiver; A first port through which the first data extracted by the demultiplexer is output; And And a second port through which the second data extracted from the demultiplexing unit is output. The integrated frame, The position at which the first input speed and the second input speed are recorded is determined, The number of slots allocated to the first frame generated from the first data is determined by the first input speed, The number of slots allocated to the second frame generated from the second data is determined by the second input speed. The first frame and the second frame are recorded in order, The demultiplexing unit, Separating the first frame and the second frame from the integrated frame with reference to the first input speed and the second input speed, Extracting the first data from the first frame, extracting the second data from the second frame, The sum of the number of slots allocated to the first frame and the number of slots allocated to the second frame is equal to or less than the total slots of the integrated frame. Nulls are filled in slots that are not allocated to the first frame and the second frame in the integrated frame. And the null is filled behind the first frame and the second frame. Receiving, by the receiver, the integrated frame; Extracting, by the receiving apparatus, the first data and the second data from the integrated frame based on the first input speed and the second input speed recorded in the integrated frame received in the receiving step; Outputting, by the receiving device, first data extracted in the extracting step; And And outputting, by the receiving device, second data extracted in the extracting step. The integrated frame, The position at which the first input speed and the second input speed are recorded is determined, The number of slots allocated to the first frame generated from the first data is determined by the first input speed, The number of slots allocated to the second frame generated from the second data is determined by the second input speed. The first frame and the second frame are recorded in order, The extraction step, Separating, by the receiving device, the first frame and the second frame from the integrated frame with reference to the first input speed and the second input speed; And And extracting, by the receiving device, the first data from the first frame and extracting the second data from the second frame. The sum of the number of slots allocated to the first frame and the number of slots allocated to the second frame is equal to or less than the total slots of the integrated frame. Nulls are filled in slots that are not allocated to the first frame and the second frame in the integrated frame. And the null is filled after the first frame and the second frame.

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