KR101146233B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR101146233B1 KR101146233B1 KR1020050058810A KR20050058810A KR101146233B1 KR 101146233 B1 KR101146233 B1 KR 101146233B1 KR 1020050058810 A KR1020050058810 A KR 1020050058810A KR 20050058810 A KR20050058810 A KR 20050058810A KR 101146233 B1 KR101146233 B1 KR 101146233B1
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims abstract description 11
- 239000007943 implant Substances 0.000 claims abstract description 11
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000005465 channeling Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
- H01L27/0738—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with resistors only
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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Abstract
본 발명은 저항소자의 선형성을 확보하여 정밀한 반도체 장치의 저항을 형성할 수 있는 방법을 제공하기 위한 것으로, 이를 위해 본 발명은 기판상에 게이트용 폴리실리콘 패턴을 형성하는 단계; 상기 게이트용 폴리실리콘 패턴의 양측면에 소스/드레인 영역을 형성하는 단게; 상기 소스/드레인 영역 및 상기 폴리실리콘 패턴을 포함하는 기판 전면에 ESD 성장을 진행하여 래트럴 단결정구조의 실리콘막을 성장시키는 단계; 상기 기판상에 형성된 상기 단결정구조의 실리콘막을 패터닝하는 단계; 및 상기 패터닝된 단결정구조의 실리콘막에 임플란트 공정을 진행하여 저항을 형성시키는 단계를 포함하는 반도체 장치의 제조방법을 제공한다.The present invention is to provide a method for forming a resistance of a precise semiconductor device by ensuring the linearity of the resistance element, the present invention comprises the steps of forming a polysilicon pattern for the gate on the substrate; Forming source / drain regions on both sides of the gate polysilicon pattern; Growing a silicon film having a lateral single crystal structure by performing ESD growth on an entire surface of the substrate including the source / drain region and the polysilicon pattern; Patterning the silicon film of the single crystal structure formed on the substrate; And forming a resistance by performing an implant process on the patterned silicon crystal of the single crystal structure.
반도체, 수동소자, 저항, 게이트. Semiconductors, passive devices, resistors, gates.
Description
도1a 내지 도1c는 종래기술에 의해 반도체 장치의 저항을 제조하는 방법에 관한 공정단면도.1A to 1C are cross-sectional views of a process for manufacturing a resistance of a semiconductor device by the prior art.
도2는 종래기술에 의해 제조된 저항의 문제점을 나타내는 도면.2 is a diagram showing a problem of resistance manufactured by the prior art;
도3a 내지 도3j는 본 발명의 바람직한 실시예에 따른 반도체 장치의 저항을 제조하는 방법에 관한 공정단면도.3A to 3J are cross-sectional views of a method of manufacturing a resistance of a semiconductor device according to a preferred embodiment of the present invention.
도4는 본 발명의 바람직한 실시예에 따른 반도체 장치의 저항을 나타내는 도면.4 illustrates a resistance of a semiconductor device according to a preferred embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
30 : 기판 31 : 소자분리막30
32 : 게이트용 절연막 33 : 게이트용 폴리실리콘막32: gate insulating film 33: gate polysilicon film
34 : 소스/드레인영역 35,36 : 게이트 패턴34: source / drain
본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 반도체 장치의 정밀저항을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a precision resistance of a semiconductor device.
통상적으로 반도체 장치를 제조할 때에 저항을 제조하는 방법으로는 웰을 이용하는 방법과 게이트용 폴리실리콘을 이용하는 방법을 사용한다. 웰을 이용하는 저항은 저항값이 너무 높아 작은 저항값을 원할 때는 폴리실리콘을 이용하는 저항을 사용한다.Usually, when manufacturing a semiconductor device, the method of manufacturing a resistance uses the method of using a well and the method of using polysilicon for gates. The resistance using the well is too high, so when a small resistance is desired, the resistance using polysilicon is used.
게이트용 폴리실리콘을 원하는 크기만큼 형성시키고 양단에 배선과 접합시키면 저항이 되는 것이다.If the polysilicon for the gate is formed to the desired size and joined to the wiring at both ends, it becomes a resistance.
그러나, 이러한 폴리실리콘 저항은 그 형성면적의 길이와 넓이에 따라 성상되는 그레인이 차이가 나기 때문에,아주 정밀한 저항을 요구되는 상황에서는 폴리실리콘 저항의 저항값차이로 인해 반도체 장치의 동작상에러가 발생할 수 있다.However, since the grains formed vary depending on the length and width of the formation area of the polysilicon resistor, an operation error of the semiconductor device may occur due to the difference in resistance value of the polysilicon resistor in a situation where very precise resistance is required. have.
도1a 내지 도1c는 종래기술에 의해 반도체 장치의 저항을 제조하는 방법에 관한 공정단면도이다.1A to 1C are cross-sectional views of a process for manufacturing a resistance of a semiconductor device according to the prior art.
도1a에 도시된 바와 같이, 종래기술에 의한 반도체 장치의 저항을 제조하는 방법은 먼저 기판(10)에 패드산화막과 패드질화막을 형성하고, 감광막 패턴을 이용하여 패터닝한 다음, 패터닝된 패드산화막과 패드질화막을 이용하여 기판에 트랜치를 형성하고, 형성된 트랜치에 산화막을 매립시켜 소자분리막(11)을 형성한다.As shown in FIG. 1A, a method of manufacturing a resistor of a semiconductor device according to the related art is first formed with a pad oxide film and a pad nitride film on a
이어서 도1b에 도시된 바와 같이, 게이트용 절연막(12)을 형성하고, 그 상부에 게이트용 폴리실리콘막(13)을 형성한다.Subsequently, as shown in FIG. 1B, a gate
이어서 도1c에 도시된 바와 같이, 게이트용 폴리실리콘막(13)을 패터닝하고, 그 측벽에 게이트용 측벽절연막을 형성시켜 게이트 패턴(16)을 형성시킨다.Subsequently, as shown in FIG. 1C, the
이때 피모스트랜지스터와 앤모스트랜지스터의 게이트 패턴에 각각 Phosphorus(또는 Asenic)와 boron(BF2)을 도핑하여 게이트 전극막의 저항값을 낮춘다.At this time, Phosphorus (or Asenic) and boron (BF2) are doped into the gate patterns of the PMOS transistor and the ANMOS transistor to decrease the resistance of the gate electrode film.
이어서 저항으로 될 폴리실리콘막(15)에는 붕소(Boron)를 30~50KeV, 5E13 atom/cm2 ~ 7E17 atoms/cm2 로 도핑하는 임플란트공정을 진행한다.Subsequently, an implant process of doping boron with 30 to 50 KeV and 5E13 atom / cm 2 to 7E17 atoms / cm 2 is performed on the
이렇게 형성된 저항은 저항을 위한 임플란트 공정을 하기 전에 다른 게이트 패턴을 하는 공정에서 완전히 노출되어 있고, 저항을 위한 폴리실리콘 패턴은 컬럼(column)구조를 가지기 때문에 채널링(channeling)이 발생하게 된다.The resistance thus formed is completely exposed in another gate pattern process before the implant process for the resistance, and the channeling occurs because the polysilicon pattern for the resistance has a column structure.
따라서 저항 균일도가 불량하며, 또한 채널링으로 인해 도펀트(dopant)가 균일하게 분포하지 못하게 되는 문제점이 생긴다.Therefore, there is a problem in that the resistance uniformity is poor, and that the dopant is not uniformly distributed due to channeling.
도2는 종래기술에 의해 제조된 저항의 문제점을 나타내는 도면이다.2 is a diagram showing a problem of resistance manufactured by the prior art.
도2에 도시된 바와 같이, 신호가 지나갈 때에 전반사가 일어나지 못하고 국부적인 반사가 발생하며 이때 신호의 왜곡이 발생할 수 있으며, 또한 노이즈가 증가하게 된다.As shown in FIG. 2, when the signal passes, total reflection does not occur, local reflection occurs, and distortion of the signal may occur, and noise may increase.
이는 저항의 선형성이 떨어지는 문제를 가져오는데, 아날로그 회로의 경우 소자의 선형성은 회로의 성능에 매우 큰 영향을 주기 때문에 이를 개선하는 게 매우 중요하다.This leads to a problem of poor linearity of the resistors. In the case of analog circuits, it is very important to improve the linearity of the device since it has a great effect on the performance of the circuit.
본 발명은 전술한 문제점을 해결하기 위해 제안된 것으로, 저항소자의 선형성을 확보하여 정밀한 반도체 장치의 저항을 형성할 수 있는 방법을 제공함을 목적으로 한다.The present invention has been proposed to solve the above-described problem, and an object of the present invention is to provide a method for forming a resistance of a precise semiconductor device by securing linearity of a resistance element.
본 발명은 기판상에 게이트용 폴리실리콘 패턴을 형성하는 단계; 상기 게이트용 폴리실리콘 패턴의 양측면에 소스/드레인 영역을 형성하는 단게; 상기 소스/드레인 영역 및 상기 폴리실리콘 패턴을 포함하는 기판 전면에 ESD 성장을 진행하여 래트럴 단결정구조의 실리콘막을 성장시키는 단계; 상기 기판상에 형성된 상기 단결정구조의 실리콘막을 패터닝하는 단계; 및 상기 패터닝된 단결정구조의 실리콘막에 임플란트 공정을 진행하여 저항을 형성시키는 단계를 포함하는 반도체 장치의 제조방법을 제공한다.The present invention comprises the steps of forming a polysilicon pattern for the gate on the substrate; Forming source / drain regions on both sides of the gate polysilicon pattern; Growing a silicon film having a lateral single crystal structure by performing ESD growth on an entire surface of the substrate including the source / drain region and the polysilicon pattern; Patterning the silicon film of the single crystal structure formed on the substrate; And forming a resistance by performing an implant process on the patterned silicon crystal of the single crystal structure.
본 발명은 실리콘 에피텍셜(epitaxial) 기술을 이용하여 엘리베이트된 소스드레인(elevated source drain)을 형성하는 기술에서 파생되는 래트럴 싱글 크리스탈 실리콘 성장(lateral single crystal Si growth)을 이용하여 정밀한 저항을 만드는 것에 관한 것이다.The present invention is directed to the creation of precise resistance using lateral single crystal Si growth, which is derived from a technique for forming an elevated source drain using silicon epitaxial technology. It is about.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명 의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
도3a 내지 도3j는 본 발명의 바람직한 실시예에 따른 반도체 장치의 저항을 제조하는 방법에 관한 공정단면도이다.3A to 3J are cross-sectional views of a method of manufacturing a resistance of a semiconductor device according to a preferred embodiment of the present invention.
도3a에 도시된 바와 같이, 본 실시예에 의한 반도체 장치의 저항을 제조하는 방법은 먼저 기판(30)에 패드산화막과 패드질화막을 형성하고, 감광막 패턴을 이용하여 패터닝한 다음, 패터닝된 패드산화막과 패드질화막을 이용하여 기판에 트랜치를 형성하고, 형성된 트랜치에 산화막을 매립시켜 소자분리막(31)을 형성한다.As shown in FIG. 3A, in the method of manufacturing the resistor of the semiconductor device according to the present embodiment, first, a pad oxide film and a pad nitride film are formed on a
이어서 도3b에 도시된 바와 같이, 게이트용 절연막(32)을 형성하고, 그 상부에 게이트용 폴리실리콘막(33)을 형성한다.Subsequently, as shown in FIG. 3B, a gate
이어서 도3c에 도시된 바와 같이, 게이트용 폴리실리콘막(33)을 패터닝하고, 그 측벽에 게이트용 측벽절연막을 형성시켜 게이트 패턴(36)을 형성시킨다. 이때 피모스트랜지스터와 앤모스트랜지스터의 게이트 패턴에 각각 Phosphorus(또는 Asenic)와 boron(BF2)을 도핑하여 게이트 전극막의 저항값을 낮춘다.Subsequently, as shown in FIG. 3C, the
이때 P 또는 As는 10~70KeV, 3E13 atom/cm2 ~ 7E15 atoms/cm2로 공정을 진행하고, BF2 또는 B인경우에는 10~70KeV, 3E13 atom/cm2 ~ 7E15 atoms/cm2로 도핑하는 임플란트공정을 진행한다.At this time, P or As proceeds with 10 ~ 70KeV, 3E13 atom / cm2 ~ 7E15 atoms / cm2, and in case of BF2 or B, implant process doping with 10 ~ 70KeV, 3E13 atom / cm2 ~ 7E15 atoms / cm2 do.
이어서 모스트랜지스터의 소스/드레인 영역(34)을 불순물을 도핑하여 형성하고, 소스/드레인 영역(34)의 안정을 위한 급속열처리 공정을 진행한다.Subsequently, the source /
이어서 ESD(elevated source drain)성장 공정을 진행하는데, 즉, 에피텍셜 공정을 진행하는 것이다. 이때 실리콘 격자를 래터럴(lateral)하게 성장시키는데, 이 경우 게이트 전극과 소스/드레인간에 단락이 발생할 경우 추가적인 마스크를 적용하여 게이트 패턴의 측벽스페이서상에 형성된 싱글 크리스탈 실리콘을 제거한다. Next, an ESD (Elevated Source Drain) growth process is performed, that is, an epitaxial process is performed. At this time, the silicon lattice is laterally grown. In this case, when a short circuit occurs between the gate electrode and the source / drain, an additional mask is applied to remove the single crystal silicon formed on the sidewall spacer of the gate pattern.
이 공정에서 생긴 ESD 실리콘막이 37이다. ESD 막의 두께를 조절하게 되면 저항의 저항값이 매우 높게 될 수 있다. 이때 실시하는 에피텍셜 공정은 400 ~ 1000도 범위에서 UHV 방식으로 성장을 진행한다. The ESD silicon film produced in this process is 37. By adjusting the thickness of the ESD film, the resistance value of the resistor can be very high. At this time, the epitaxial process is carried out in the UHV method in the 400 ~ 1000 degree range.
이때 ESD 실리콘막 대신에 SiGe막을 적용하여 공정을 진행할 수 있다.In this case, the SiGe film may be applied instead of the ESD silicon film to proceed the process.
이어서 도3d에 도시된 바와 같이, 기판 전체에 실리콘산화막(38)을 형성한다.3D, a
이어서 도3e에 도시된 바와 같이, 샐리사이드 공정을 위한 마스크(39)를 형성한다.Subsequently, as shown in FIG. 3E, a mask 39 for the salicide process is formed.
이어서 도3f에 도시된 바와 같이, 마스크(39)를 이용하여 실리콘산화막(38)을 제거한다.Subsequently, as shown in FIG. 3F, the
이어서 도3g에 도시된 바와 같이, 셀리사이드 공정을 진행하여 게이트 전극과 소스/드레인 영역상에 실리사이드막이 형성되도록 한다.Next, as shown in FIG. 3G, a cellicide process is performed to form a silicide film on the gate electrode and the source / drain region.
이어서 저항 형성을 위한 마스크(40)를 형성한다. 이어서 마스크(40)를 이용하여 저항이 형성될 영역에 저항을 위한 임플란트 공정을 진행한다.Subsequently, a
이때의 임플란트 공정은 붕소(Boron) 또는 BF2를 이용하여 30~50KeV, 3E13 atom/cm2 ~ 7E15 atoms/cm2로 도핑하는 임플란트공정을 진행한다.In this case, the implant process is performed using a boron (Bron) or BF2 doping 30 ~ 50KeV, 3E13 atom / cm2 ~ 7E15 atoms / cm2.
이어서 도3i에 도시된 바와 같이, 층간절연막(41)을 형성한다.Subsequently, as shown in FIG. 3I, an
이어서 도3j에 도시된 바와 같이, 하단의 도전막과 접속된 콘택플러그(42)를 형성한 다음, 상부배선(43)을 형성한다.Subsequently, as shown in FIG. 3J, the contact plug 42 connected to the lower conductive film is formed, and then the
전술한 바와 같이, 종래기술로 형성된 저항은 폴리실리콘이 컬럼구조로 되어 있어 임플란트 공정시 채널링이 쉽게 발생하며, 이는 신호 전파시 전반사가 일어나는 것을 방해하게 된다. 이는 신호의 왜곡을 발생시키며, 또한 노이즈도 함께 발생하게 되는 문제가 있었다.As described above, the resistance formed in the prior art has a polysilicon columnar structure so that channeling occurs easily in the implant process, which prevents total reflection during signal propagation. This causes a distortion of the signal, and also has a problem that noise also occurs.
그러나 본 실시예에서는 저항을 실리콘 에피텍셜 기술을 이용하여 엘리베이트된 소스드레인(elevated source drain)을 형성하는 기술에서 파생되는 래트럴 싱글 크리스탈 실리콘 성장(lateral single crystal Si growth)을 이용하여 형성하기 때문에, 저항의 정확성을 보정할 수 있게 된다.However, in the present embodiment, since the resistance is formed using lateral single crystal Si growth derived from a technique of forming an elevated source drain using silicon epitaxial technology, The accuracy of the resistance can be corrected.
또한 균일한 저항체가 형성되어 신호전파시 노이즈 방지가 가능하고, 훨씬 향상된 선형성을 확보할 수 있어 저항 소자의 응용범위가 넓어질 수있다.In addition, since a uniform resistor is formed, noise can be prevented during signal propagation, and much improved linearity can be secured, thereby increasing the application range of the resistor.
따라서 정밀한 동작이 요구되는 아날로그회로에서 본 발명에 의한 저항을 사용하게 되면 보다 정확한 동작을 기대할 수 있다.Therefore, when the resistor according to the present invention is used in an analog circuit requiring precise operation, more accurate operation can be expected.
도4는 본 발명의 바람직한 실시예에 따른 반도체 장치의 저항을 나타내는 도면이다.4 is a diagram showing a resistance of a semiconductor device according to a preferred embodiment of the present invention.
도4에 도시된 바와 같이, 본 발명에 의해 제조된 저항은 신호가 전달될 때에 전반사가 일어나서 노이즈에 대한 문제가 제거될 수 있다.As shown in Fig. 4, the resistance produced by the present invention can cause total reflection when a signal is transmitted, thereby eliminating the problem of noise.
이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식 을 가진 자에게 있어 명백할 것이다.As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.
본 발명에 의해서 정밀한 저항을 제조할 수 있게 되어 본 발명에 의한 저항을 사용하는 회로의 동작상 정확성을 기대할 수 있게 되었다.According to the present invention, it is possible to manufacture a precise resistor, and thus the operational accuracy of a circuit using the resistor according to the present invention can be expected.
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