KR101135058B1 - Encryption method and encryption device using differential fault analysis in round key generation of Data Encryption Standard - Google Patents

Abstract

Disclosed is a cryptographic processing method for executing a 16-round Fiestel type common key block cryptographic process by dividing a block into 64 bits of data. The method comprises performing an initial substitution on a 64-bit plain text, and performing first and second bit shifts on a cipher key generated by parity drop of a master key through bit left shift and compression permutation. Generating a sixteenth round key and generating a sixteenth round key through the bit left rotation, error injection and compression of the register, and dividing the 64-bit plaintext in which the initial substitution is performed into two 32-bit left and right registers. After storing in the first to sixteenth rounds, performing the encryption operation using the first to sixteenth round keys, and the bits generated through the encryption operations of the first to sixteenth rounds. Performing the reverse process of said initial substitution. The method may inject an error in the process of generating a 16-round key to widen the error injection possible range and obtain a master key by injecting fewer errors.

Description

Encryption method and encryption device using differential fault analysis in round key generation of Data Encryption Standard}

The present invention relates to a cryptographic processing method and a cryptographic processing device, and more particularly, to a cryptographic processing method and a cryptographic processing device using differential error injection attack in the round key generation process of the data encryption standard.

With the development of network communication and electronic commerce, securing security is becoming more and more important. One of security methods is encryption technology, and communication using various encryption methods is performed.

Encryption methods are largely classified into public key cryptography and common key cryptography. Public key cryptography is an encryption method for setting an encryption key and a decryption key to different keys, and common key cryptography is an encryption method for setting an encryption key and a decryption key as a common key. Although there are various algorithms in common key cryptography, one of them generates a plurality of keys based on the common key and repeats data conversion processing in block units (64 bits, 128 bits, etc.) using the generated keys. One common method is to execute common key block cryptography. Common key block cryptography is a typical US standard encryption, the Data Encryption Standard (DES) is widely used in various fields.

Various subchannel attacks on cryptographic algorithms were introduced: TA (timing attack), SPA (simple analysis), DPA (differential power analysis), EMA (electromagnetic analysis) And passive attack methods, and active attack methods such as FA (Fault Injection Attack, Fault Analysis) and DFA (Differential Error Injection Attack, Differential Fault Analysis). The differential error injection attack (DFA) is a method of obtaining a master key using a difference between a correct cipher text and an injecting cipher text in a data flow of a block cipher algorithm or a stream cipher algorithm.

Differential Error Injection Attack (DFA) against Data Encryption Standard (DES) has been proposed to recover the master key by injecting an error into the 13th round left state. After that, a generalized and extended method was introduced to inject an error into the left state of the middle round (rounds 9-12) to obtain a master key, which is a differential error injection attack (DFA) throughout the round during encryption and decryption. This means that the method can be applied. In addition, a differential error injection attack (DFA) in the key generation process has been proposed, not a differential error injection attack (DFA) in the general encryption process. However, these variously proposed methods have a problem in that complexity increases because the number of injected errors is too large.

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The technical problem to be solved by the present invention is to solve the problem of the Data Encryption Standard (DES), to compensate for the problem of the existing Data Encryption Standard (DES) in the key generation process of the Data Encryption Standard (DES) The present invention provides an encryption processing method and an encryption processing apparatus in which the number of errors is improved by injecting an error.

According to an aspect of the present invention, there is provided a cryptographic processing method for executing a 16-round Fiestel-type common key block cryptographic processing of a block in which data is divided into 64-bit blocks. To generate the first to fifteenth round keys through bit left shifting and compression permutation of the cipher key generated by parity drop. Generating a sixteenth round key through substitution; dividing the 64-bit plaintext in which the initial substitution is performed into two 32-bit bits and storing them in a left register and a right register, and then performing the first through sixteenth rounds. Performing the encryption operation using the sixteenth round key, and performing the operation on bits generated through the encryption operations of the first to sixteenth rounds. It provides the encryption processing method of performing a reverse process of the group substitution.

Generating the first to fifteenth round keys and the sixteenth round key may be performed by dividing the cipher key into two blocks and performing a one-bit or two-bit left shift through the first to fifteenth rounds. And generate a first to fifteenth round key through compression permutation, and use a cipher key of one bit or two bits left shifted through the first to fifteenth rounds. A 16th round key may be generated by performing a left shift, injecting an error into a left or right register, and performing compression.

In the generating of the first to fifteenth round keys and the sixteenth round key, one-bit left shift may be performed in the first, second, ninth, and sixteenth rounds.

The first to fifteenth round keys and the sixteenth round key may be 48 bits.

The sixteenth round key may have a value in which an error is injected into the left or right 24 bits and the remaining 24 bits may have a round key value in which no error is injected.

According to another aspect of the present invention, a program of instructions that can be executed by a digital processing apparatus is implemented to perform the encryption processing method, and provides a recording medium having a program recorded thereon that can be read by the digital processing apparatus. .

According to still another aspect of the present invention, there is provided a cryptographic processing apparatus for performing a 16-round Fiestel type common key block cryptographic processing of a block in which data is divided into 64-bit blocks. Left shift and compression of a central processing unit for executing a program, a program executed by the central processing unit, a memory for storing fixed data as operation parameters, and a cipher key generated by parity drop of a master key. The first to the fifteenth round keys are generated through compression permutation and the sixteenth round key is generated through the bit left rotation, error injection of the register, and compression substitution to generate the generated first block in a block divided into 64 bits. It provides a cryptographic processing apparatus comprising a cryptographic processing unit for performing cryptographic processing using the first to sixteenth round key. The.

The encryption processing unit divides the cipher key into two blocks and performs one or two bit left shift through the first to fifteenth rounds, and then through compression permutation to perform the first to fifteenth. Generates a round key and performs a 1-bit left shift on a cipher key that has undergone a 1-bit or 2-bit left shift through the first through 15th rounds and an error in a left or right register. After injection of the 16 th round key, compression may be generated.

The encryption processing unit includes a round key generation unit for generating first to sixteenth round keys, wherein the round key generation unit performs a parity drop on a 64-bit master key to generate a 56-bit encryption key; A first shift portion and a second shift portion for dividing an encryption key of bits into two blocks of 28 bits and performing a left or right shift of one or two bits of each block, and compression replacement of the bits on which the left cycle is performed It may include a compression substitution to perform.

The first shift unit and the second shift unit may perform 1-bit left shift in the first, second, ninth, and sixteenth rounds.

The encryption processing unit performs an initial substitution for the block that divides the data into 64 bits, and performs a left shift of 1 bit or 2 bits through the first to fifteenth rounds of the master key, and compression permutation. Generate a first through fifteenth round key and perform a one-bit or two-bit left shift through the first through fifteenth rounds. After the error is injected into the left or right register, the 16th round key is generated through compression substitution to perform encryption processing using the generated first to sixteenth round keys to the data on which the initial substitution is performed. And an inverse initial replacement unit for generating a cipher text through a reverse process of the initial substitution for bits in which encryption processing is performed through the first to sixteenth rounds. There.

The basic operation unit is used and save the data that the initial substituted performed on both the left divided into blocks of 32-bit registers (L _i) and right register (R _i), the generated first to the 16th Round Key It may include an F-function unit for performing the encryption process.

The F-function unit expands and replaces the 32-bit block with 48-bit data, and performs an exclusive OR operation of the first to sixteenth round keys generated from the round key generator in the 48-bit data. An exclusive OR operation unit for performing the operation, an S-box replacement unit for replacing and replacing the 48-bit data on which the exclusive OR operation is performed with 32-bit data, and a P-box replacement unit for copy-substituting the substituted 32-bit data. It may include.

The S-box replacement part includes eight S-boxes, and an error may be injected into the first to fourth or fifth to eighth S-boxes of the input values of the S-box.

An error may be injected into bits 1 to 16 or 17 to 32 of the output value of the S-box.

1, 2, 6, 9, 10, 13, 16, 17, 18, 20, 23, 24, 26, 28, 30, 31st or 3, 4, 5, 7, 8, of the output value of the F-function part Errors may be injected into the 11th, 12th, 14th, 15th, 19th, 21st, 22nd, 25th, 27th, and 32nd bits.

The encryption processing method according to the present embodiment may inject an error in the process of generating a 16-round key to widen an error injection possible range and obtain a master key by injecting fewer errors.

1 is a block diagram illustrating an encryption module of a data encryption standard (DES).
2 is a block diagram showing a configuration of an F-function unit.
3 is a block diagram showing a round key generation unit according to the present embodiment.
4 is a conceptual diagram illustrating a method of processing an encryption through a 16-round key injected with an error according to the present embodiment.
5 is a flowchart illustrating a method of acquiring a master key through encryption processing through an error-injected 16 round key according to the present embodiment.
6 is a block diagram showing an encryption processing apparatus that performs encryption processing according to the present embodiment.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated and described in the drawings. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms including ordinal numbers, such as second and first, may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be referred to as the first component, and similarly, the first component may also be referred to as the second component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may exist in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be given the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

b 는 a와 b의 배타적 논리합, <a>는 a의 집합, P는 평문(64비트), C는 옳은 암호문(64비트), C_L ^*는 16라운드 키 생성단계에서 왼쪽 레지스터에 오류가 주입된 암호문, C_R ^*는 16라운드 키 생성단계에서 오른쪽 레지스터에 오류가 주입된 암호문, L_i는 i번째 라운드의 왼쪽 32비트 출력값, R_i는 i번째 라운드의 오른쪽 32비트 출력값, L_i ^*는 오류가 주입된 i번째 라운드의 왼쪽 32비트 출력값, R_i ^*는 i번째 라운드의 오른쪽 32비트 출력값, K는 마스터 키(64비트) 및 RK_i는 i번째 라운드 키(48비트)를 나타낸다. In this embodiment, a

b is an exclusive OR of a and b, <a> is a set of a, P is plaintext (64-bit), C is correct ciphertext (64-bit), and C _L ^* is an error in the left register during 16-round key generation Ciphertext, C _R ^* is the ciphertext injecting an error into the right register during the 16 round key generation phase, L _i is the left 32-bit output of the i-th round, R _i is the right 32-bit output of the i-th round, and L _i ^* is The left 32-bit output value of the i-th round of the error injected, R _i ^* is the right 32-bit output value of the i-th round, K is the master key (64-bit) and RK _i is the i-th round key (48-bit).

1 is a block diagram illustrating an encryption module of a data encryption standard (DES).

Referring to FIG. 1, the encryption module 10 includes an initial replacement unit 100, a basic operation unit 200, and a reverse initial replacement unit 300. The initial substitution unit 100 performs initial permutation (IP) on a 64-bit plain text (P) block that is input. The basic operation unit 200 divides the 64-bit block in which the initial substitution has been performed into two 32-bit blocks, stores them in the left register L _i and the right register R _i , and then performs 16 rounds performed by the F-function. The product transformation and the left register (L _i ) and the right register (R _i ) are carried out for each round of 16 block transformations (Block Transformation). Here, the product transformation is an F-function unit for performing an encryption operation by inputting a 32-bit block stored in the right register R _i together with the round key RK _i generated by a round key generator (not shown). 210 and the first exclusive OR operation 220 that performs exclusive OR on the result of the F-function unit 210 together with the 32-bit block stored in the left register L _i . The 32-bit data of the first exclusive OR operation 220 is stored in the right register R _{i +1} of the next round and the 32-bit data stored in the right register R _i is the left register L _{i +} of the next round. Block transformation is performed by being exchanged and stored in ₁ ). In the encryption module 10, the first round of operations is repeated to perform 16 rounds. The reverse initial exchanger 300 outputs the cipher text (C) encrypted through the reverse initial exchange (IP− ¹ ) of the bits generated after the transformation over 16 rounds is completed.

2 is a block diagram showing a configuration of an F-function unit.

Referring to FIG. 2, the F-function unit 210 performs an F-function operation, and includes an expansion substitution unit 211, a second exclusive OR operation unit 212, an S-box substitution unit 213, and a P-box. Substitution part 214 is included. The expansion substitution unit 211 receives 32 bits of data from a register R _B that stores a 32 bit text block and expands the data into 48 bits of data. The second exclusive OR operation unit 212 receives an 48-bit data output from the expansion substitution unit 211, receives a round key RK _i from a round key generation unit (not shown), and performs an exclusive OR operation. .

The S-box replacement unit 213 includes eight S-boxes and replaces and replaces the 48 bits of data output from the second exclusive OR calculation unit 212 with 32 bits of data. The P-box replacement unit 214 copies and replaces the 32-bit data output from the S-box replacement unit 213 to output 32-bit data.

3 is a block diagram showing a round key generation unit according to the present embodiment.

Referring to FIG. 3, the master key of the Data Encryption Standard (DES) is 64 bits including a 56-bit key and 8 bits of parity check bits. The parity drop unit 20 parity drops the 64-bit master key to generate and output a 56-bit encryption key. The 56-bit encryption key is divided into two blocks of 28 bits and is divided into one bit (1, 2, 9, 16 rounds) or 2 bits left shifted by the first shift unit 31 and the second shift unit 33. After the compression substitution unit 35 through the compression substitution process to generate a 48-bit round key (RK _i ) and outputs.

In the round key generation unit according to the present exemplary embodiment, an error is injected into one of a 28-bit left register or a right register in which an input value is stored in the compression substitution unit 35 of 16 rounds. The 16 round key (RK ₁₆ ) generated and output through the compression substitution process in the compression substitution unit 35 is a value in which an error is injected into the left or right half 24 bits, and the other half 24 bits is an original round in which no error is injected. It has a key value. Accordingly, a value in which an error is injected into 1 to 4th or 5 to 8th S-boxes of the 8 S-boxes of the F-function unit 210 to which the 16 round key RK ₁₆ is input according to the present embodiment is determined. Is entered. An error is injected into bits 1 to 16 or 17 to 32 of the output value of the S-box and 1 of the output value of the F-function unit 210 by the P-box replacement unit 214 of the F-function unit 210. , 2, 6, 9, 10, 13, 16, 17, 18, 20, 23, 24, 26, 28, 30, 31st or 3, 4, 5, 7, 8, 11, 12, 14, 15, Errors can be injected into the 19th, 21st, 22nd, 25th, 27th, 32nd bits. Here, the i th round in the round key generation unit refers to a round for generating a round key used for the i th round of an encryption module of a data encryption standard (DES).

4 is a conceptual diagram illustrating a method of processing an encryption through a 16-round key injected with an error according to the present embodiment.

Referring to FIG. 4, since R ₁₆ , L ₁₆ , and L ₁₆ ^* are known to an attacker, the output difference and the input value of the F-function unit 210 may be known. A candidate group of S-box input values may be generated using output difference information of the S-box. By cipher text for several plain texts in one error, the number of candidate groups can be reduced to determine 1 to 24 bit values or 25 to 48 bit values of the round key.

5 is a flowchart illustrating a method of acquiring a master key through encryption processing through an error-injected 16 round key according to the present embodiment.

Referring to FIG. 5, an error-injected ciphertext is obtained through a correct ciphertext and a 16-round key in which an error is injected according to the present embodiment (S510). Specifically, for any plaintext P, a ciphertext C with no error injected is obtained. In the round key generation unit according to the present embodiment, a ciphertext (C _L ^* ) obtained by injecting an error into one of a 28-bit left register or a right register in which an input value is stored in a compression rounder 35 of 16 rounds. Or get a ciphertext (C _R ^* ).

Then, a set of S-box output value candidate groups is generated (S520). 16 round outputs L ₁₆ , L ₁₆ ^* , R ₁₆ = R ₁₆ ^* are obtained by initial substitution of the correct ciphertext (C) and the error-injected ciphertext (C _L ^* or C _R ^* ) obtained in S510. The output difference of the F-function unit 210 is expressed by Equation 1 below.

The F-function unit 210 obtains the output difference of the S-box through the reverse substitution process of the last substitution. The output difference of the S-box for C _L ^* affects only the first to fourth S-boxes, so it is **** 0000 and for C _R ^* The output difference of the S-box is 0000 **** since it only affects the fifth to eighth S-boxes. Here, * is a known output difference value of the S-box, and is an integer value of 0-15. When the correct output value is determined for each S-box output difference, the error-injected output value is determined as one, so there are 16 possible pairs of the correct output value and the error-injected output value. Each of the 16 output pairs for the eight S-boxes is stored in a set <output (ith S-box)>. Here i is an integer value of 1-8.

Then, a set of S-box input value candidate groups is generated (S530). Specifically, the S-box of the F-function unit 210 has four input values for one determined output value. Therefore, one correct output value and an error-injected output value have four input value candidate groups. A pair of the correct output value and the error-injected output value of the output value set of the S-box obtained in S520 has 16 input value candidate group pairs. The number of pairs of input value candidate groups in which correct input values and errors are injected into one S-box is 256 (16 × 16). Each 256 input value pairs for 8 S-boxes are stored in a set <input (ith S-box)>. Here i is an integer value of 1-8.

Then, a set of 16 round key candidate groups is generated (S540). From the R16 obtained in S530, an extended 48-bit intermediate value is obtained through the expansion substitution unit 211 of the F-function unit 210. The 48-bit intermediate value is divided into eight 6-bits to perform an exclusive OR operation on the set <input (ith S-box)> elements stored in S530. Calculation result RK ₁₆ And a pair of 6-bit candidate RK ^* ₁₆ stores a set of eight _{<ith RK 16, ith RK 16} *>. Here i is an integer value of 1-8.

Then, a master key is obtained (S560). In detail, the non-matching round key pair is removed for each set <ith RK ₁₆ , ith RK ₁₆ ^* > which are stored by repeating S510 to S540 for another plain text (S550). This process is repeated to obtain one 48-bit round key. The master key is acquired through the reverse process of the round key generation step using the confirmed 16 round key.

In detail, operations S510 to S560 are described as 256 elements (2 ⁸ ) in the S-box input value set. The total possible number of input values of the S-box is 2 ¹² (= 2 ⁶ × 2 ⁶ ). By injecting a fault in one of the plaintext S-box candidates number of input pair is reduced by 1/2 ⁴ (= ^28/212). Therefore, if an error is injected into three plain texts, the number of candidate groups of S-box input value pairs can be reduced to 1/256 (= (1/2 ⁴ ) ³ ), so that one correct input value pair can be obtained. That is, in the round key generation step, if an error is injected from the left register or the right register of the 16 round compression substitution, and the ciphertext for each 3 plain texts is obtained, the correct 16 round keys can be obtained and the round key is generated using the confirmed 16 round keys. It is possible to obtain a master key through the reverse process of the steps.

6 is a block diagram showing an encryption processing apparatus that performs encryption processing according to the present embodiment.

Referring to FIG. 6, the encryption processing apparatus 600 includes a central processing unit 610, a memory 620, an encryption processing unit 630, a random number generator 640, and a transceiver 650.

The central processing unit 610 (CPU) is a processor for starting or ending encryption processing, controlling data transmission and reception, controlling data transmission between components, and executing various other programs. The memory 620 includes a program executed by the central processing unit 610 or a ROM (Read-Only-Memory) for storing fixed data as operation parameters, a program executed in the processing of the central processing unit 610, and a program processing. It comprises a storage area for a parameter which changes suitably, RAM (Random Access Memory) used as a workpiece | work area, etc. In addition, the memory 620 can be used as a storage area for key data and the like required for encryption processing.

The encryption processing unit 630 executes encryption processing, decryption processing, and the like, which perform the method according to the present embodiment described above. The random number generator 640 executes generation of random numbers necessary for generation of a key required for encryption processing. The transceiver 650 is a data communication processor that performs data communication with the outside. For example, data communication with an IC module such as a reader / writer is executed, and output of a cipher text generated in the IC module or data input from a device such as an external reader / writer is executed.

In the present embodiment, an example in which the encryption processing apparatus 600 is an individual module is illustrated. However, the encryption processing program is not configured as an independent encryption processing module, but the encryption processing program is stored in the ROM, and the central processing unit 610 reads the ROM storage program. It can also be configured to run.

Hereinafter, the effect of the encryption processing method according to the present embodiment will be described.

A comparison between the encryption processing method according to the present embodiment and the encryption processing method of the conventional DES will be described in Table 1 below.

Referring to Table 1, a method of performing a differential error injection attack on the middle round of the DES and a method of performing a differential error injection attack on the 16 rounds according to this embodiment was compared. In the method of performing the differential error injection attack on the middle round, a master key is obtained by injecting about 20 to 10 ⁸ 1 byte random errors in the 9 to 12 rounds. On the other hand, the method of performing the differential error injection attack on the 16th round according to the present embodiment obtains the master key by injecting about 6 registers (4 bytes) random errors in the 16th round key generation step. It can be seen that the size of the injected error and the number of errors improved compared to the conventional method.

The term '~ part' used in the present embodiment refers to software or a hardware component such as a field-programmable gate array (FPGA) or an ASIC, and '~ part' performs certain roles. However, '~' is not meant to be limited to software or hardware. &Quot; to &quot; may be configured to reside on an addressable storage medium and may be configured to play one or more processors. Thus, as an example, '~' means components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, procedures, and the like. Subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. The functionality provided within the components and the 'parts' may be combined into a smaller number of components and the 'parts' or further separated into additional components and the 'parts'. In addition, the components and '~' may be implemented to play one or more CPUs in the device or secure multimedia card.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

The program is stored in a computer readable medium (computer reader media), and read and executed by the computer to implement the encryption processing method. The information storage medium includes a magnetic recording medium, an optical recording medium and a carrier wave medium.

All of the above functions may be performed by a processor such as a microprocessor, a controller, a microcontroller, an application specific integrated circuit (ASIC), or the like according to software or program code coded to perform the function. The design, development and implementation of the code will be apparent to those skilled in the art based on the description of the present invention.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention. You will understand. Therefore, the present invention is not limited to the above-described embodiment, and the present invention will include all embodiments within the scope of the following claims.

10: encryption module 100: initial replacement unit
200: basic operation unit 210: F-function unit
211: expansion substitution unit 212: second exclusive-OR operation unit
213: S-box substitution 214: P-box substitution
220: first exclusive AND operation unit 300: reverse initial replacement unit

Claims (18)

In a cipher processing method for executing a 16-round facetel type common key block cipher processing of a block divided into 64-bit data,
Performing an initial substitution on the 64-bit plain text;
A cipher key generated by parity drop of the master key is used to generate first to fifteenth round keys through bit left shift and compression permutation, and bit injection of the left register Generating a sixteenth round key through compression;
The 64-bit plaintext of which the initial substitution is performed is divided into two 32-bits and stored in a left register and a right register, and then performed through an encryption operation using the first through sixteenth round keys through first through sixteenth rounds. step; And
And performing an inverse of the initial substitution on the bits generated through the first to sixteenth round encryption operations. The method of claim 1,
Generating the first to fifteenth round keys and the sixteenth round key
By dividing the cipher key into two blocks, one-bit or two-bit left shift is performed through the first to fifteenth rounds, and the first to fifteenth round keys are generated through compression permutation. After performing a 1-bit left shift of the cipher key with 1-bit or 2-bit left shift through the first to 15th rounds, and injecting an error into the left- or right-register. And a sixteenth round key through compression conversion. The method of claim 2,
Generating the first to fifteenth round keys and the sixteenth round key;
The first, second, ninth, and sixteenth rounds, a 1-bit left shift is performed. The method of claim 1,
And the first to fifteenth round keys and the sixteenth round key are 48 bits. The method of claim 4, wherein
The sixteenth round key is a value in which an error is injected into the left or right 24 bits, and the remaining 24 bits have a round key value in which the error is not injected. A program of instructions that can be executed by a digital processing apparatus is implemented to perform the cryptographic processing method according to any one of claims 1 to 5, wherein a program that can be read by the digital processing apparatus is recorded. Record carrier. A cryptographic apparatus that executes 16 rounds of facetel type common key block cryptographic processing by dividing a block into 64 bits of data.
A central processing unit controlling the initiation and termination of encryption processing, transmission and reception of data, and executing a program;
A memory for storing a program executed by the central processing unit and fixed data as an operation parameter; And
A cipher key generated by parity drop of the master key is used to generate first to fifteenth round keys through bit left shift and compression permutation, and bit injection of the left register And an encryption processing unit for generating a sixteenth round key through compression substitution and performing encryption processing using the generated first to sixteenth round keys in a block obtained by dividing the data into 64-bits. The method of claim 7, wherein
And the first to fifteenth round keys and the sixteenth round key are 48 bits. The method of claim 8,
The sixteenth round key is a value in which an error is injected into the left or right 24 bits, and the remaining 24 bits have a round key value in which the error is not injected. The method of claim 7, wherein
The encryption processing unit
By dividing the cipher key into two blocks, one-bit or two-bit left shift is performed through the first to fifteenth rounds, and the first to fifteenth round keys are generated through compression permutation. After performing a 1-bit left shift of the cipher key with 1-bit or 2-bit left shift through the first to 15th rounds, and injecting an error into the left- or right-register. And a sixteenth round key through compression substitution. The method of claim 10,
The encryption processing unit includes a round key generation unit for generating first to sixteenth round keys,
A parity drop unit which generates a 56-bit encryption key by performing a parity drop on a 64-bit master key;
A first shift unit and a second shift unit for dividing the 56-bit encryption key into two blocks of 28 bits and performing a left shift of one or two bits of each block; and
And a compression substitution unit configured to perform compression substitution of bits on which the left rotation is performed. The method of claim 11,
And the first shift unit and the second shift unit perform a 1-bit left shift in the first, second, ninth, and sixteenth rounds. The method of claim 10,
The encryption processing unit
An initial substitution unit which performs initial substitution on a block obtained by dividing the data into 64-bits;
The master key is left-shifted one bit or two bits through the first to fifteenth rounds, and the first to fifteenth rounds are generated through compression permutation and the first to fifteenth rounds. 1-bit or 2-bit left shift through cipher key 1 bit left shift, injecting error to left or right register and compressing A basic calculation unit which generates encryption by using the generated first to sixteenth round keys to the data on which the initial substitution is performed; And
And an inverse initial replacement unit for generating a cipher text through the reverse process of the initial substitution for the bits on which encryption processing is performed through the first to sixteenth rounds. The method of claim 13,
The basic operation unit is used and save the data that the initial substituted performed on both the left divided into blocks of 32-bit registers (L _i) and right register (R _i), the generated first to the 16th Round Key And an F-function unit to perform encryption processing. The method of claim 14,
The F-function part
An expansion substitution unit for extending replacement of the 32-bit block with 48-bit data;
An exclusive-OR operation unit that performs an exclusive-OR operation on the first to sixteenth round keys generated from the round-key generation unit on the 48-bit data;
An S-box replacement unit for replacing and replacing 48-bit data on which the exclusive OR operation has been performed with 32-bit data; And
And a P-box replacement unit for copy-substituting the substituted 32-bit data. The method of claim 15,
The S-box replacement includes eight S-boxes,
And an error is injected into the first to fourth or fifth to eighth S-boxes of the input values of the S-boxes. 17. The method of claim 16,
And an error is injected into bits 1 to 16 or 17 to 32 of the output values of the S-box. The method of claim 14,
1, 2, 6, 9, 10, 13, 16, 17, 18, 20, 23, 24, 26, 28, 30, 31st or 3, 4, 5, 7, 8, of the output value of the F-function part Cryptographic processing apparatus characterized in that the error is injected into the 11th, 12th, 14th, 15th, 19th, 21st, 22nd, 25th, 27th, and 32nd bits.

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