KR101133532B1 - A variable resistor having nonvolatile memory cell - Google Patents

Abstract

The present invention is to provide a variable resistor that prevents damage to the substrate during the trimming operation for correcting the resistance value, and can trim the resistance value even after packaging. It consists of a plurality of stages consisting of a nonvolatile memory cell and a resistor connected in series between the ground terminals, each stage connected between the resistance of the previous stage and the ground terminal to program and erase the nonvolatile memory cell. Provided is a variable resistor in which the resistance value varies depending on the state.

Variable Resistors, Nonvolatile Memory Cells, EEPROM, CMOS, NMOS, PMOS, Trimming

Description

Variable resistor with nonvolatile memory cell {A VARIABLE RESISTOR HAVING NONVOLATILE MEMORY CELL}

1 is a block diagram showing a variable resistor according to a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view of the nonvolatile memory cell shown in FIG. 1. FIG.

<Explanation of symbols for the main parts of the drawings>

10: decoder

21: substrate

22: well

23: gate oxide film (dielectric film)

24, 27: gate electrode

25a, 28a: source region

25b, 28b: drain region

28c: bulk area

26: tunnel oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable resistor having a nonvolatile memory cell, and more particularly, to a variable resistor having a nonvolatile memory cell capable of program and erase operations, such as an EEPROM (Electric Erasable Programmable Read Only Memory) cell or a flash cell. Relates to a resistor.

In general, the variable resistor is a device that can change the resistance value for adjusting the frequency or volume of the radio. When the variable resistor is mounted on a printed circuit board (PCB), a trimming process of adjusting the resistance value of the variable resistor is performed. In this process, many defects such as substrate degradation or error are generated.

The variable resistor according to the prior art is commonly formed in an array form using a conductive material such as poly silicon or metal on a silicon substrate. Such a variable resistor uses a laser in the trimming operation. The trimming operation is performed by cutting and connecting the selected portion using a laser.

However, the substrate may be damaged by the laser during this trimming operation. In order to eliminate the damage on the circuit caused by the damage of the substrate, the metal array constituting the variable resistor should be formed at regular intervals. This requires a relatively large area. In addition, once the chip is packaged, the trimming operation using the laser cannot be performed. Moreover, there is a disadvantage that if a defect occurs in the trimming operation performed before the packaging process, it should be discarded. As a result, the failure rate is high because there is no way to compensate for the change in resistance caused by the package.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a variable resistor capable of eliminating damage to a substrate during a trimming operation.

It is another object of the present invention to provide a variable resistor capable of trimming the resistance value even after packaging.

It is another object of the present invention to provide a variable resistor that can significantly reduce the defective rate due to trimming errors.

The present invention according to one aspect for achieving the above object is composed of a plurality of stages consisting of a resistor and a non-volatile memory cell connected in series between the input terminal and the ground terminal, each stage is the resistance and ground of the previous stage Provided is a variable resistor connected between stages, the resistance of which varies in accordance with the program and erase states of the nonvolatile memory cell.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

1 is a view illustrating a variable resistor according to a preferred embodiment of the present invention, and FIG. 2 is a cross-sectional view of each nonvolatile memory cell shown in FIG. 1.

As shown in FIG. 1, the variable resistor according to the preferred embodiment of the present invention includes the resistors RO to R3 and the nonvolatile memory cells NVM0 to NVM3 connected in series between the input terminal A and the ground terminal VSS. And each stage (stage0 to stage3), each of which is connected between the resistance of the previous stage and the ground terminal, and programmed and erased states of the nonvolatile memory cells NVM0 to NVM3. The resistance value varies accordingly. The nonvolatile memory cells NVM0 to NVM3 are programmed or erased according to the gate voltages Vg0 to Vg3 selected according to the trimming signals trm0 and trm1.

As shown in FIG. 2, the nonvolatile memory cells NVM0 to NVM3 are formed of a single poly EEPROM cell. A single poly EEPROM cell consists of a CMOS transistor consisting of an NMOS transistor and a PMOS transistor. The single gate electrodes 24 and 27 of each transistor are interconnected to be used as floating gates, and the source and drain regions 25a and 25b and the bulk regions 28c of the PMOS transistors are interconnected to control each other. Used as a gate. In addition, the drain region 28b of the NMOS transistor is used as the input terminal A, and the source region 28a is used as the output terminal B. FIG.

Program and erase operations are performed using the F-N tunneling (Fouler-Nordheim Tunneling) method. In general, the program operation of the EEPROM cell is performed by channel hot electron injection, and the erase operation is performed by FN tunneling. However, in the preferred embodiment of the present invention, the nonvolatile memory cell (e.g. Since the program and erase operations of NVM0 to NVM3 are performed, it is preferable to apply the FN tunneling scheme. However, as an example, the program operation may also be performed by the channel thermal electron injection method according to the configuration of the peripheral circuit.

The program operation applies a high voltage of approximately 18V to the gate and voltage regions Vg0 to Vg3 of the source and drain regions 25a and 25b and the bulk region 28c of the control gate, that is, the PMOS transistor, and the source and drain regions of the NMOS transistor. It carries out by floating (28a, 28b). As a result, the high voltage applied to the control gates 25a, 25b, and 28c is transferred to the floating gates 24 and 27 in response to the coupling ratio of the gate oxide film 23 serving as the dielectric film. Accordingly, electrons are injected from the P-type substrate 21 into the floating gates 24 and 27 through the tunnel oxide film 26 to perform a program operation.

The erase operation applies a high voltage of approximately -18V to the gate and voltage regions Vg0 to Vg3 of the source and drain regions 25a and 25b and the bulk region 28c of the control gate, that is, the PMOS transistor, and the source and drain of the NMOS transistor. This is performed by floating the regions 28a and 28b. As a result, the negative high voltage applied to the control gates 25a, 25b, and 28c is transferred to the floating gates 24 and 27 corresponding to the coupling ratio of the gate oxide film 23 serving as the dielectric film. Accordingly, electrons injected into the floating gates 24 and 27 during the program operation are emitted from the P-type substrate 21 through the tunnel oxide layer 26 to perform the erase operation.

The nonvolatile memory cells have different threshold voltages depending on the program or erase state. Generally, programmed memory cells have a higher distribution than threshold voltages of erased memory cells. The program cell can be viewed in an OFF state when compared to the switching element, and the erase cell can be viewed in an ON state. That is, by selectively programming or erasing the nonvolatile memory cell to operate as a switching element, the resistance value is varied by forming or blocking a current path through the series connected resistors R0 to R3.

Hereinafter, a trimming operation of the variable resistor according to the preferred embodiment of the present invention will be described. For example, as shown in FIG. 1, when trimming the target resistance value to 'R0 + R1', other memory cells NVM0, NVM2, and NVM3 except for the second memory cell NVM1 using the decoder 10 are used. Program all and erase only the second memory cell (NVM1). As a result, the current I input to the input terminal A flows to the ground terminal VSS via the resistor R0, the resistor R1, and the memory cell NVM1. As a result, the target resistance value becomes 'R0 + R1'. Here, the program or erase operation is performed in the manner as described above.

Meanwhile, although the switching device is implemented using a single poly EEPROM cell, all of the nonvolatile memory cells capable of program and erase operations are applicable as an example. However, when implemented as a single poly EEPROM cell, since the process is implemented as a CMOS process, the process is simplified compared to the stacked EEPROM cells of the floating gate and the control gate, and since the CMOS device implemented in the chip is used as it is, no separate process is required. There is an advantage. In addition, as the program or erase operation is performed by the F-N tunneling method, the program and erase operation can be implemented by only one decoder, thereby simplifying the circuit than performing the program and erase operation by the channel hot electron injection method.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a trimming operation can be easily implemented by implementing a variable resistor using a nonvolatile memory cell as a switching element.

In addition, according to the present invention, it is possible to solve the problem that the substrate is damaged during the trimming operation using a laser in the prior art by simply performing the trimming operation through the program and erase operations.

Further, according to the present invention, the resistance value can be corrected by performing the trimming operation through the program and erase operations even after the packaging.

Therefore, according to the present invention, the defective rate due to the trimming error can be significantly reduced.

Claims (7)

It is composed of a plurality of stages consisting of a resistor and a nonvolatile memory cell connected in series between an input terminal and a ground terminal, and each stage is connected between the resistor of the previous stage and the ground terminal to program and erase the nonvolatile memory cell. Depending on the resistance value, The nonvolatile memory cell is a variable resistor consisting of a CMOS transistor. delete The method of claim 1, The CMOS transistor comprises a PMOS and an NMOS transistor with gate electrodes interconnected, wherein the source and drain regions and the bulk region of the PMOS transistor are interconnected. The method of claim 3, wherein And the nonvolatile memory cell is programmed or erased by the source and drain regions of the PMOS transistor and the gate voltage applied to the bulk region. It is composed of a plurality of stages consisting of a resistor and a nonvolatile memory cell connected in series between an input terminal and a ground terminal, and each stage is connected between the resistor of the previous stage and the ground terminal to program and erase the nonvolatile memory cell. Depending on the resistance value, The nonvolatile memory cell comprises a dual poly EEPROM cell or a single poly EEPROM cell. 6. The method according to claim 1 or 5, And the non-volatile memory cell is programmed and erased by F-N tunneling. The method according to claim 1 or 5, And the nonvolatile memory cell is programmed or erased by a gate voltage output from a decoder.

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