KR101130271B1 - A context-based adaptive variable length coding device for H.264/AVC - Google Patents

Abstract

The present invention relates to the hardware size of a context-based Adaptive Variable Length Coding device, which is an essential entropy coding element when H.264 / AVC and H.264 / SVC codecs are used. The present invention relates to a content-based variable length coder for H.264 / AVC that can be reduced. According to the present invention, a modified lookup table and a parallel processing technique are used. Earlier, by performing a zigzag scan on the first buffer, storing residual data in the forward and reverse directions, and using a double buffer to generate values for variables using the values from the previous buffer in the second buffer, It can read and write at the same time and can be parallelized to reduce hardware memory size. A content-based variable length encoder for H.264 / AVC is provided that is suitable for efficient and real-time video equipment.

Description

A context-based adaptive variable length coding device for H.264 / AVC}

The present invention relates to a video compression technology, and more particularly, content-based which is an essential entropy coding element when H.264 codec such as H.264 / AVC, H.264 / SVC is used. Context-based Adaptive Variable Length Coding The present invention relates to a content-based variable length encoder for H.264 / AVC that can reduce the hardware size of a device.

In recent years, the number of devices using video information continues to increase, and such multimedia devices require high quality and low bit rate.

In order to satisfy this requirement, the video coding standard requires a high compression ratio and an optimized coding algorithm.

Among such algorithms, context-based Adaptive Variable Length Coding (hereinafter simply referred to as 'CAVLC') is used by H.264 codecs such as H.264 / AVC, H.264 / SVC, etc. Is an essential entropy coding element, which is used, for example, in MPEG4-Part10 (H.264 / AVC), which is a video compression technique in IP TV.

Here, H.264 is an open source of object-based high-quality high-compression media format, has excellent compatibility with the existing MPEG2 broadcasting system, and has been well received by countries and companies as an international standard.

In addition, H.264 / AVC is currently being used by domestic and international satellite and terrestrial digital multimedia broadcasting (DMB) and respective IP TV sites.

In addition, as a video compressor method having high utilization in video for PMP and Internet upload, etc., it is widely used in various portable information terminals, DVRs, network cameras, surveillance cameras, navigation, and the like.

Therefore, CAVLC used in H.264 / AVC and H.264 / SVC becomes an important part of the image codec in each application field as described above, and its use range is very extensive.

Therefore, in hardware implementation of H.264 / AVC and H.264 / SVC, the influence and necessity of an efficient CAVLC encoder both in terms of price and performance are increasing.

In response to this demand, conventionally, an "integrated converter of an H.264 encoder" has been proposed, as described, for example, in Publication No. 10-2010-0059037 (published on June 4, 2010).

The integrated converter of the H.264 encoder described in Korean Patent Application Publication No. 10-2010-0059037 includes a forward integer conversion unit which performs 2-D integer conversion by repeatedly performing 1-D integer conversion for differential block or DC block processing. For the DC block processing, the forward Hadamard buffer that stores the DC output value in the forward integer converter and the scaling factor values for the value input from the forward integer converter are grouped into groups to add, subtract, and shifter. Inverse integer that performs 2-D integer conversion by repeatedly performing 1-D integer conversion on the quantization unit for quantization, the inverse quantization unit for restoring the input value from the quantization unit, and the output value of the inverse quantization unit. And a reverse Hadamard buffer for storing the dequantized result through the inverse quantization unit after performing the transform unit and the reverse Hadamard transform. to be.

More specifically, the conventional H.264 encoder is designed separately for each integer converter by an electronic circuit, but the integrated converter of the H.264 encoder of the above-described Patent Publication No. 10-2010-0059037, in the H.264 encoder Implement a quantizer and inverse quantizer using shifters, adders and subtractors without using a multiplier, and reuse a single 1-D integer converter to perform both forward and forward Hadamard transformations. By controlling forward integer conversion, quantization, inverse quantization, inverse integer conversion, and Hadamard transform, hardware cost can be minimized and performance can be maximized.

That is, according to the integrated converter of the H.264 encoder described in the above-mentioned Patent Publication No. 10-2010-0059037, the hardware cost is minimized by processing the forward integer conversion, quantization, inverse quantization, inverse integer conversion, Hadamard transformation in one converter However, the integrated converter of the above-described H.264 encoder of the Patent Publication No. 10-2010-0059037 did not provide an algorithm for reducing the processing step itself of the H.264 encoding process.

Therefore, as described above, it is desirable to provide a CAVLC encoder having a more efficient algorithm by reducing the processing steps in the encoding process, but a CAVLC encoder and an algorithm that satisfy all such requirements have not been provided. .

The present invention seeks to solve the problems of the prior art as described above. Accordingly, an object of the present invention is to replace a part having commonality in a CAVLC encoding method using a lookup table. In order to reduce the hardware memory size by simplifying the processing, a content-based variable length coder for H.264 / AVC is provided.

Further, another object of the present invention is to reduce the overall hardware size by reducing the memory size as described above, thereby reducing the production cost of the hardware, thereby reducing the cost of H.264 / AVC and H.264 / SVC. It is to provide a content-based variable length coder for H.264 / AVC which is more efficient and high performance in terms of price and performance in hardware implementation.

In order to achieve the above object, according to the present invention, a content-based variable length coder for H.264 / AVC performing the encoding process using a modified variable length coding table and a parallel processing technique In a context-based adaptive variable length coding device, an upper buffer to which input values are written and a next buffer while the input values are written so that reading and writing are performed simultaneously to improve the performance of the encoder. Encoding processing includes a first double buffer and a second double buffer each including an under buffer into which a value to be read is written, and a coeff_token block, a TrailingOnes_sign block, a level block, a total_zeros block, and a run_before block. An arithmetic operation unit, a bit stream buffer storing a result value processed by the arithmetic unit, and The call information is provided based on the variable length encoder, characterized in that configured by a control unit (control unit) for generating a control signal and an enable signal for controlling the overall operation of the firearm.

Here, the first double buffer receives residual data as input, performs zigzag scanning, and stores the data in the forward and reverse directions in the upper and lower buffers, respectively, and the second double buffer is the forward direction. The data stored in the coeff_token block, the TrailingOnes_sign block, the level block, the total_zeros block, and the PRM_G (parameter generator) generating the variables of the controller, and the data stored in the reverse direction, are used. It is configured to include a run_before generator (RB_G), which generates a variable used only in a block, in its upper and lower buffers, respectively, to serve as a variable generator, whereby the following blocks are configured to enable parallel processing.

In the modified variable length coding table, a portion having the same characteristics is modified by using an arithmetic operation so that the hardware usage is reduced as compared with a conventional look up table. The value of (codeword) is [M zeros] [1] [INFO], which is a codeword format of conventional Exponential Golomb entropy coding, and FP1 means the position where 1 first appears, The length is expressed, INFO is an information value after FP1, and INFO_length is changed to [FP1] [INFO] [INFO_length].

In addition, the value generated by the second double buffer, characterized in that configured to be stored in different positions of the buffer every 16 times so that parallel processing can be performed continuously.

In addition, the bitstream buffer is characterized in that configured as FIFO (first in first out).

As described above, according to the present invention, H.264 / AVC, which can simplify the processing and reduce the hardware memory size, by replacing a part having commonality in the CAVLC encoding method using a lookup table with arithmetic operations. It can provide a content-based variable length coder for.

Furthermore, according to the present invention, hardware implementation of H.264 / AVC and H.264 / SVC can be achieved by reducing the total hardware size by reducing the memory size as described above, thereby reducing the production cost of the hardware. In terms of cost and performance, a content-based variable length coder for H.264 / AVC can be provided.

1 is a diagram schematically illustrating a detailed configuration of a content-based variable length encoder for H.264 / AVC according to the present invention.

Hereinafter, with reference to the accompanying drawings, the details of the content-based variable-length encoder for H.264 / AVC according to the present invention will be described.

Hereinafter, it is to be noted that the following description is only an embodiment for carrying out the present invention, and the present invention is not limited to the contents of the embodiments described below.

First, with reference to FIG. 1, the detailed configuration of the content-based variable length encoder 10 for H.264 / AVC according to the present invention will be described.

1 schematically illustrates a detailed configuration of a content-based variable length encoder 10 for H.264 / AVC according to the present invention.

That is, as shown in FIG. 1, the content-based variable length encoder 10 according to the present invention uses a modified loop-up table and a parallel processing technique, and prior to applying the parallel processing technique. Two double buffers are used. The first double buffer performs the zigzag scan and stores the residual data in the forward and reverse directions, and then the second double buffer uses the values from the previous buffer for variables. Create a value.

At this time, the generated value is stored by changing the position of the buffer every 16 times so that parallel processing can be performed continuously.

Here, the first double buffer is a simple double buffer, but the second double buffer combines the function of the generator with the function of the buffer to generate the variable values and control signals to be used in the next step so that the next blocks can be parallelized. .

By using two double buffers as described above, the content-based variable-length coder can read and write simultaneously and parallel processing.

In addition, the entire module was synthesized and verified using a Megnachip 0.18㎛ CMOS Cell Library. When implemented as an ASIC, the encoder operates at 140 MHz and has about 12,000 gate counts. It is suitable for application in real time video equipment.

In addition, in FIG. 1 and the following description, description of each term is as follows.

* coeff_token: Non-zero coefficients are called TotalCoeff, a number that is 1 or -1 from the last TotalCoeff coefficient is called TrailingOnes, and up to three TrailingOnes are possible.

trailing_ones_sign Recognizes a TrailingOnes value as a sign, where 1 is encoded as 0 and -1 is encoded as 1.

* level: TotalCoeff means coefficients except TrilingOnes.

total_zeros: The total number of zero coefficients before the last nonzero coefficients.

run_before: The number of zeros between each coefficient.

That is, more specifically, the CAVLC encoder 10 according to the present invention includes two dual buffers, that is, zigzag (11, 12), PRM_G and RB_G (13, 14), and a control unit (Control unit). (15), an arithmetic processing unit consisting of a coeff_token block (16), a TrailingOnes_sign block (17), a level block (18), a total_zeros block (19), and a run_before block (20) and a bit_stream block (21). Consists of.

Here, the first double buffers 11 and 12 of the two double buffers receive residual data as input and store zigzag scanning in the forward and reverse directions.

Stored in the forward direction is used by the parameter generator (PRM_G), and stored in the reverse direction is used by the RB_G (run_before generator).

The reason for using a structure such as a double buffer as shown in FIG. 1 is to allow reading and writing to be performed simultaneously.

That is, while 16 input values are written to the upper buffer, the under buffer is repeatedly read in the next stage, thereby improving the encoder performance.

The second double buffer acts as a variable generator.

That is, PRM_G generates variables of coeff_token block 16, TrailingOnes_sign block 17, level block 18, total_zeros block 19 and control unit 15, and RB_G uses variables used only in run_before block 20. Create

Variables and control signals generated in PRM_G and RB_G allow the following blocks to be processed in parallel.

The control signal from the controller 15 controls the operation of each block because it provides an enable signal of blocks that are processed in parallel, and the variables generated in PRM_G and RB_G are provided as blocks that are processed in parallel. Allow each block in to perform the operation.

The resultant values processed in parallel by the arithmetic processing unit are stored in the bit_stream buffer 21, which is composed of FIFOs (First Insert First Output).

In addition, the above contents are described, for example, in "ITU-T H.264 Corrigendum 1 (2009.01), which describes the standard for H.264, SERIES H: AUDIOVISUAL AND MULTIMEDIA SYSTEMS Infrastructure of audiovisual services-Coding of moving video. "Such as It can be fully understood by referring to the contents of the standardization document (see p. 214 to p. 223, 9.1 Parsing process for Exp-Golomb codes ~ 9.2, CAVLC parsing process for transform coefficient levels).

Next, Modified Variable Length Coding tables used in the present invention will be described.

The modified variable length coding table is a modification of an existing look up table, and the portion having the same characteristics uses arithmetic operations, so that the hardware usage is reduced compared to the existing look up table.

In particular, compared to the case of using a memory (ROM), it can be seen that the hardware usage is reduced by 20% or more, because the frequently used parts are often replaced by arithmetic operations.

In order to configure the modified variable length coding table as described above, the codeword value, which is a value of the table, needs to be modified as in the codeword configuration of Exponential Golomb entropy coding.

The codeword format of the Exponential Golomb is configured as, for example, [M zeros] [1] [INFO].

In the modified variable length coding table, the codeword format of the Exponential Golomb is configured with a similar format [FP1] [INFO] [INFO_length].

FP1 is the position where 1 first appears, and at the same time expresses the length of FP1.

INFO is an information value after FP1, and INFO_length represents the length of INFO.

As a simple example, the codeword format is shown in Table 1 below.

[Table 1]

By using the codeword format as shown in Table 1, it is applied to two reference tables of coeff_token table and run_before table to be used in CAVLC.

The following are three cases of the coeff_token table according to the nc value, and the table and pseudo code are shown.

TABLE 2

[Table 3]

[Table 4]

TABLE 5

TABLE 6

TABLE 7

Next, Table 8 below is a modified run_before table, and Table 9 shows pseudo codes accordingly.

[Table 8]

TABLE 9

Next, the inventors of the present invention test the performance of the content-based variable length coder 10 for H.264 / AVC according to the present invention configured as described above, and the results are shown in the following [Table 10]. It was.

TABLE 10

Here, the hardware implementation was using Verilog-HDL language, and verified using a Megnachip 0.18㎛ CMOS process.

Total gate count refers to the number of 2-input nand gates, with a critical pass of 6.64ns, which can be used for real-time video.

In addition, if the first dual buffer used at the input is not needed, the total gate count is 6.5K and the hardware size is determined.

In addition, Xilinx Vertex-4 LX200-10ff1513 FPGA was used as a board test. As shown in Table 11, 1,003 of 89,088 slices (Avaliable) were used. ) Accounted for 1% (Utilization) of the total slices.

TABLE 11

In addition, the clock speed and latency on the board have a minimum period of 9.398ns and a maximum frequency of 106.401MHz.

Accordingly, as described above, according to the present invention, it is possible to provide a content-based variable length encoder for H.264 / AVC which is more efficient in terms of price and performance in hardware implementation.

In addition, according to the present invention, as a video compressor method with high utilization not only in domestic and overseas satellite and terrestrial DMB and IP TV sites, but also in PMP and Internet, it is widely used in portable information terminals, DVRs, network cameras, surveillance cameras, navigation systems, etc. It is possible to provide a content-based variable length coder for H.264 / AVC, which is essential where the H.264 codec, which is a video compression technology, is used.

As described above, the details of the content-based variable length encoder for H.264 / AVC according to the present invention have been described through the embodiments of the present invention. However, the present invention is limited only to the contents described in the above embodiments. Therefore, it is a matter of course that the present invention can be variously modified, changed, combined, and replaced by those skilled in the art according to design needs and various other factors. .

10. CAVLC Encoder 11. Double Buffer
12. Double Buffer 13. Double Buffer
14. Double buffer 15. Control part
16. coeff_token block 17. TrailingOnes_sign block
18. level block 19. total_zeros block
20. run_before block 21. bit_stream block

Claims (5)

In a context-based adaptive variable length coding device for H.264 / AVC that performs encoding processing using a modified variable length coding table and a parallel processing technique,
In order to improve the performance of the encoder, the upper and upper buffers to which the input values are written and the under buffers to which the values to be read at the next stage are written while the input values are written, so that the reading and writing are performed simultaneously. A first dual buffer and a second dual buffer comprising;
an arithmetic processing unit including a coeff_token block, a TrailingOnes_sign block, a level block, a total_zeros block, and a run_before block;
A bit stream buffer for storing a result value processed by the operation processor; And
A control unit for generating a control signal and an enable signal for controlling the overall operation of the encoder;
And the bitstream buffer comprises first in first out (FIFO).
The method of claim 1,
The first double buffer receives residual data as an input, performs zigzag scanning, and stores the data in the forward and reverse directions in the upper and lower buffers, respectively.
The second double buffer,
A parameter generator (PRM_G) for generating variables of the coeff_token block, the TrailingOnes_sign block, the level block, the total_zeros block, and the controller, respectively, using the data stored in the forward direction;
By using the data stored in the backward direction, RB_G (run_before generator) for generating a variable used only in the run_before block is included in its upper and lower buffers to serve as a variable generator, whereby the following blocks are processed in parallel. Content-based variable length encoder, characterized in that configured to enable.
The method of claim 1,
In the modified variable-length coding table, a portion having the same characteristics is modified by using an arithmetic operation so that the hardware usage is reduced as compared with a conventional look up table. ) Value is [M zeros] [1] [INFO], which is a codeword form of Exponential Golomb entropy coding, and FP1 denotes the position where 1 first appears, and the length of FP1. And INFO is an information value after FP1, and INFO_length is configured to be replaced with [FP1] [INFO] [INFO_length] when INFO_length represents the length of INFO. The method of claim 1,
And the value generated by the second double buffer is configured to be stored at different positions of the buffer every 16 times so that parallel processing can be continuously performed. delete

Images