KR101125603B1 - Manufacturing method of microelectrode array - Google Patents

Manufacturing method of microelectrode array Download PDF

Info

Publication number
KR101125603B1
KR101125603B1 KR1020100016300A KR20100016300A KR101125603B1 KR 101125603 B1 KR101125603 B1 KR 101125603B1 KR 1020100016300 A KR1020100016300 A KR 1020100016300A KR 20100016300 A KR20100016300 A KR 20100016300A KR 101125603 B1 KR101125603 B1 KR 101125603B1
Authority
KR
South Korea
Prior art keywords
electroplating
layer
pad region
photoresist
platinum
Prior art date
Application number
KR1020100016300A
Other languages
Korean (ko)
Other versions
KR20110096825A (en
Inventor
최지현
신희섭
성호근
김신근
송호영
Original Assignee
한국과학기술연구원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 한국과학기술연구원 filed Critical 한국과학기술연구원
Priority to KR1020100016300A priority Critical patent/KR101125603B1/en
Priority to PCT/KR2010/004850 priority patent/WO2011105665A1/en
Publication of KR20110096825A publication Critical patent/KR20110096825A/en
Application granted granted Critical
Publication of KR101125603B1 publication Critical patent/KR101125603B1/en

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • AHUMAN NECESSITIES
    • A61MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61NELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00Electrotherapy; Circuits therefor
    • A61N1/02Details
    • A61N1/04Electrodes
    • A61N1/05Electrodes for implantation or insertion into the body, e.g. heart electrode
    • A61N1/0526Head electrodes
    • A61N1/0529Electrodes for brain stimulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03466Conformal deposition, i.e. blanket deposition of a conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/035Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/03515Curing and solidification, e.g. of a photosensitive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362Photolithography
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/038Post-treatment of the bonding area
    • H01L2224/0383Reworking, e.g. shaping
    • H01L2224/03831Reworking, e.g. shaping involving a chemical process, e.g. etching the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/116Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162Manufacturing methods by patterning a pre-deposited material using masks
    • H01L2224/11622Photolithography
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902Multiple masking steps
    • H01L2224/11903Multiple masking steps using different masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

본 발명은 미세전극 어레이 제조방법에 관한 것으로, 더 상세하게는, 전기도금을 통해 양각 형태로 전극을 형성하여, 전극 표면의 거칠기를 크게 하면서, 전극의 두께를 증가시킬 수 있는 미세전극 어레이 제조방법에 관한 것이다. 본 발명의 일 실시예에 따른 미세전극 어레이 제조방법은, 미리 준비된 실리콘 기판 상에 희생층을 증착하는 단계; 상기 증착된 희생층 상에 제1 폴리머를 도포하여 패터닝한 후, 열 경화시키는 단계; 상기 제1 폴리머 상에 본딩 패드 영역과, 트랜스미션 라인과, 레코딩 패드 영역을 형성하도록 금속박막을 패터닝하는 단계; 상기 트랜스미션 라인을 폐쇄하고, 상기 본딩 패드 영역과 레코딩 패드 영역을 패터닝하도록 제2 폴리머를 도포하는 단계; 상기 제2 폴리머와 금속박막 상에 스퍼터 장비를 통해 시드층을 증착하는 단계; 상기 본딩 패드 영역과 레코딩 패드 영역에 대해 금속을 전기도금하여 전기도금층을 형성하는 단계; 상기 전기도금층의 상부가 개방되도록 포토레지스트를 패터닝하는 단계; 상기 포토레지스트와 전기도금층 상에 백금을 증착시키는 단계; 및 상기 포토레지스트를 제거하는 단계를 포함한다. The present invention relates to a method for manufacturing a microelectrode array, and more particularly, to form an electrode in an embossed form through electroplating, to increase the thickness of the electrode while increasing the roughness of the electrode surface, the method of manufacturing a microelectrode array It is about. Method for manufacturing a microelectrode array according to an embodiment of the present invention, depositing a sacrificial layer on a silicon substrate prepared in advance; Applying and patterning a first polymer on the deposited sacrificial layer, followed by thermal curing; Patterning a metal thin film to form a bonding pad region, a transmission line, and a recording pad region on the first polymer; Closing the transmission line and applying a second polymer to pattern the bonding pad region and the recording pad region; Depositing a seed layer on the second polymer and the metal thin film through sputtering equipment; Electroplating a metal on the bonding pad region and the recording pad region to form an electroplating layer; Patterning the photoresist such that the top of the electroplating layer is open; Depositing platinum on the photoresist and electroplating layer; And removing the photoresist.

Description

미세전극 어레이 제조방법 {MANUFACTURING METHOD OF MICROELECTRODE ARRAY}Manufacturing Method of Micro Electrode Array {MANUFACTURING METHOD OF MICROELECTRODE ARRAY}

본 발명은 미세전극 어레이 제조방법에 관한 것으로, 더 상세하게는, 전기도금을 통해 양각 형태로 전극을 형성하여, 전극 표면의 거칠기를 크게 하면서, 전극의 두께를 증가시킬 수 있는 미세전극 어레이 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a microelectrode array, and more particularly, to form an electrode in an embossed form through electroplating, to increase the thickness of the electrode while increasing the roughness of the electrode surface, the method of manufacturing a microelectrode array It is about.

전기적 자극은 신경계의 세포 반응을 유발하는데 사용되는 일반적인 기술이다. 신경계의 전기생리적 신호를 연구하는 것은 미세전극의 임피던스(impedance) 변화 때문에 매우 복잡한 과정을 필요로 한다. 따라서 전기생리적 신호와 관련된 복잡한 동작 특성을 단순화하도록 미세전극 어레이의 모든 전극들의 임피던스를 정규화(normalize)함으로써, 균일한 신경계 네트워크를 만들어야 한다. Electrical stimulation is a common technique used to induce cellular responses in the nervous system. Studying the electrophysiological signals of the nervous system requires a very complex process due to the change in the impedance of the microelectrode. Thus, a uniform neural network must be created by normalizing the impedances of all the electrodes of the microelectrode array to simplify the complex operating characteristics associated with the electrophysiological signals.

신경계의 전기생리적 신호를 측정할 때, 전극은 신호와 관련된 주파수 대역인 10Hz 내지 1kHz에서 균일한 임피던스를 가져야 한다. 낮은 임피던스는 높은 신호 이득(signal gain)을 얻기에 유리하다. 자극에 대해 전극물질은 높은 가역적 전자 주입 한계(reversible charge injection limit)를 나타내야 한다. When measuring the electrophysiological signals of the nervous system, the electrodes should have a uniform impedance at 10 Hz to 1 kHz, the frequency band associated with the signal. Low impedance is advantageous for obtaining high signal gain. For stimulation the electrode material should exhibit a high reversible charge injection limit.

가역적 전자 주입 한계는 얼마나 많은 전하가 전극에 축적될 수 있는지와, 조직에 독소산물(toxic products)을 생성하게 되는 원인인 비가역적 산화환원 반응(irreversible redox process)을 일으키는 패러데이 전류(faradaic current)를 만들지 않는 교류 인가 과정(ac cycling process)에서 전극과 전해질의 경계(interface)에서 얼마나 많은 전하가 상호교환(exchange)될 수 있는지를 의미한다. The limit of reversible electron injection limits how much charge can accumulate in the electrode and the faradaic current that causes an irreversible redox process that causes toxic products in the tissue. This means how much charge can be exchanged at the interface between the electrode and the electrolyte in an ac cycling process that does not make.

전극 표면에서의 전기화학적 행동은 매우 복잡하며 다양한 화학적, 물리적 요소를 포함한다. 전극과 전해질의 경계에서 침식(corrosion)이 일어나면, 전극 물질로 사용되는 금속 표면에서 전기화학적 반응에 의해 물질 손실(material loss)이 발생한다. 열역학적(thermadynamic) 측면에서 전극의 금속과 조직의 전해질 사이에서의 전자 교환(exchange of electrons)은 금속표면에 전류를 형성하게 된다. 따라서, 전기적 특성과 침식에 의한 마모(corrosive wear) 사이의 관계를 파악하는 것이 중요하다. Electrochemical behavior on the electrode surface is very complex and involves a variety of chemical and physical elements. If corrosion occurs at the boundary between the electrode and the electrolyte, material loss occurs due to electrochemical reactions at the metal surface used as the electrode material. In thermodynamic terms, the exchange of electrons between the metal of the electrode and the electrolyte of the tissue creates a current on the metal surface. Therefore, it is important to understand the relationship between electrical properties and corrosive wear.

전자 일함수(electron work function)는 고체인 금속 표면에서 전자 하나를 분리하는데 필요한 최소한의 에너지를 의미하고, 이 금속 표면에서의 전자 일함수는 전기적 에너지 준위를 반영하며 전극 전위(electrode potential)와 관계가 있다. 전극 물질의 표면에서의 일함수는 주로 국지적 침식 전위(local corrosion potential)와 매우 밀접한 관계가 있다. 일함수 계산을 통한 전극 물질의 표면 모폴로지(surface morphology)는 전자 행동과 침식 행동을 결정하는데 중요한 역할을 하는데 이는 전자 행동이 전기화학적 활동이나 반응성을 결정하기 때문이다. The electron work function is the minimum energy required to separate an electron from a solid metal surface, which reflects the electrical energy level and is related to the electrode potential. There is. The work function at the surface of the electrode material is mainly closely related to the local corrosion potential. Surface morphology of electrode materials through work function calculations plays an important role in determining electronic and erosion behavior, because electronic behavior determines electrochemical activity or reactivity.

전극 표면이 거칠어질수록 전자 일함수는 낮아진다. 따라서 거친 전극 표면은 더 쉽게 전자를 분리시키고, 침식율(corrosion rate)을 더 높게 한다. 즉, 전극 표면의 거칠기가 증가하면 전자 일함수는 감소하고 침식율은 증가하게 된다. The rougher the electrode surface, the lower the electron work function. Thus, the rough electrode surface more easily separates electrons and results in a higher corrosion rate. That is, as the roughness of the electrode surface increases, the electron work function decreases and the erosion rate increases.

유연한 미세전극 어레이 제조에서 전극 물질로 많이 사용되는 것은 백금(Pt)이다. 이는 백금이 화학적 침식에 강하며, 생체적합성(biocompatibility)을 갖고, 전기적 자극에 적용하기 좋은 낮은 문턱값 전위(threshold potential)를 갖기 때문이다. 그러나, 백금 역시 전극과 전해질의 경계에서 발생하는 전기화학적 반응에 의한 조직 손상을 막기 위해 균형-전하 이상 파형(balance-charge biphasic waveform)으로 전류를 인가하더라도 용해(dissolution)되는 문제가 있다.Platinum (Pt) is one of the most commonly used electrode materials in the manufacture of flexible microelectrode arrays. This is because platinum is resistant to chemical erosion, is biocompatibility and has a low threshold potential for application to electrical stimulation. However, platinum also has a problem of dissolving even when a current is applied to a balance-charge biphasic waveform to prevent tissue damage caused by an electrochemical reaction occurring at the boundary between the electrode and the electrolyte.

이상 펄스(Biphasic pulsing)가 발생하는 동안 백금의 용해는 극성(polarity), 총 전하(aggregate charge), 전하 밀도(charge density)와 같은 펄스 파라미터(pulse parameter), 전극 표면의 상태 등에 의해 영향을 받는다. 따라서 이러한 백금의 용해를 서서히 진행시키도록 전기도금한(electroplated) 백금을 형성하여 두께를 두껍게 하거나, 또는 이리듐(iridium)이나 탄탈륨(tantalium) 같은 금속에 산화물(oxide)를 주입하여 산화물 기반 전극(oxide-based electrode)을 형성하여, 표면의 거칠기를 크게 하기도 한다. 상기 방법들은 접촉 임피던스(contact impedance)를 감소시킬 수 있다.Platinum dissolution during biphasic pulsing is affected by pulse parameters such as polarity, aggregate charge, charge density, state of the electrode surface, etc. . Therefore, an electroplated platinum is formed to increase the thickness of the platinum to proceed slowly, or an oxide is injected into a metal such as iridium or tantalium to inject an oxide. -based electrodes may be formed to increase the surface roughness. The methods can reduce contact impedance.

따라서 전극 표면의 거칠기가 커질수록 금속 전극의 전자 이동이 활발하게 되며, 접촉 저항(contact resistance)이 감소하고, 정전용량 범위(capacitive region)가 커진다. 이에 따라, 가역 범위(reversible region)가 넓게 형성되므로, 비가역 반응(irreversible reaction)에 의한 조직 손상을 최소화할 수 있다. Therefore, the greater the roughness of the electrode surface, the more active the electron movement of the metal electrode, the lower the contact resistance (contact resistance), the larger the capacitive region (capacitive region). Accordingly, since a reversible region is formed wide, tissue damage due to an irreversible reaction can be minimized.

그러나, 거친 표면에서 전류는 균일한 밀도를 갖지 못하게 되며, 이는 표면의 피크(peak)보다는 밸리(valley) 부분에서 전류가 상대적으로 적게 흐르기 때문이다. 따라서 전극 표면의 거칠기와 전류 밀도의 균일도는 상반 관계(trade off)에 있게 되며, 실험적으로 실제 사용에 적용 가능한 수준을 찾아야 한다.However, on rough surfaces, the current does not have a uniform density because relatively little current flows in the valley rather than the peak of the surface. Therefore, the roughness of the electrode surface and the uniformity of the current density are in a trade off, and it is necessary to experimentally find a level applicable to actual use.

도 1은 종래의 미세전극 어레이를 도시한 도면이다. 도 1을 참조하면, 종래의 미세전극 어레이는 기판(10) 상에 희생층(20)을 형성하고, 폴리이미드(polyimide)와 같은 제1 폴리머(30) 상에 전극 패턴을 형성한다. 이후, 다시 전극(40)을 제외한 나머지 부분을 제2 폴리머(50)로 감싸며, 희생층(20)을 제거함으로써, 미세전극 어레이를 기판(10)으로부터 분리하여 제조하였다. 1 is a view showing a conventional microelectrode array. Referring to FIG. 1, a conventional microelectrode array forms a sacrificial layer 20 on a substrate 10 and forms an electrode pattern on a first polymer 30 such as polyimide. Subsequently, the microelectrode array was separated from the substrate 10 by wrapping the remaining portion except for the electrode 40 with the second polymer 50 and removing the sacrificial layer 20.

대뇌피질과 같은 신경계의 전기생리적 신호를 측정하기 위해 제조된 종래의 미세전극 어레이에서, 전극(40)은 음각의 형태로 제작되어 실제 뇌의 측정부위에 부착 시 전극이 뇌의 표면 조직에 잘 달라붙지 못하는 문제가 발생하였다. In a conventional microelectrode array manufactured for measuring electrophysiological signals of the nervous system such as the cerebral cortex, the electrode 40 is made in the form of an intaglio, and when the electrode 40 is attached to the measurement region of the brain, the electrode is different from the surface tissue of the brain. There was a problem with sticking.

즉, 종래의 미세전극 어레이의 경우, 금속 전극(40)이 제2 폴리머(50)보다 낮은 위치에 놓이게 되며, 실제 신경계에 부착 시 금속 전극(40)과 신경계 사이에 직접적인 접촉이 잘 이루어지지 않는다는 단점이 있었다. That is, in the case of the conventional microelectrode array, the metal electrode 40 is placed at a lower position than the second polymer 50, and when the metal electrode 40 is actually attached to the nervous system, direct contact between the metal electrode 40 and the nervous system is not easily achieved. There was a downside.

본 발명의 목적은 전기도금을 통해 양각 형태로 전극을 형성하여, 전극 표면의 거칠기를 크게 하면서, 전극의 두께를 증가시킬 수 있는 미세전극 어레이 제조방법을 제공하는 것이다. An object of the present invention is to provide a method of manufacturing a microelectrode array that can increase the thickness of the electrode while forming the electrode in the embossed form through electroplating, increasing the roughness of the electrode surface.

전술한 목적을 달성하기 위해 본 발명의 일 실시예에 따른 미세전극 어레이 제조방법은, 미리 준비된 실리콘 기판 상에 희생층을 증착하는 단계; 상기 증착된 희생층 상에 제1 폴리머를 도포하여 패터닝한 후, 열 경화시키는 단계; 상기 제1 폴리머 상에 본딩 패드 영역과, 트랜스미션 라인과, 레코딩 패드 영역을 형성하도록 금속박막을 패터닝하는 단계; 상기 트랜스미션 라인을 폐쇄하고, 상기 본딩 패드 영역과 레코딩 패드 영역을 패터닝하도록 제2 폴리머를 도포하는 단계; 상기 제2 폴리머와 금속박막 상에 스퍼터 장비를 통해 시드층을 증착하는 단계; 상기 본딩 패드 영역과 레코딩 패드 영역에 대해 금속을 전기도금하여 전기도금층을 형성하는 단계; 상기 전기도금층의 상부가 개방되도록 포토레지스트를 패터닝하는 단계; 상기 포토레지스트와 전기도금층 상에 백금을 증착시키는 단계; 및 상기 포토레지스트를 제거하는 단계를 포함한다. In order to achieve the above object, a method of manufacturing a microelectrode array according to an embodiment of the present invention includes depositing a sacrificial layer on a silicon substrate prepared in advance; Applying and patterning a first polymer on the deposited sacrificial layer, followed by thermal curing; Patterning a metal thin film to form a bonding pad region, a transmission line, and a recording pad region on the first polymer; Closing the transmission line and applying a second polymer to pattern the bonding pad region and the recording pad region; Depositing a seed layer on the second polymer and the metal thin film through sputtering equipment; Electroplating a metal on the bonding pad region and the recording pad region to form an electroplating layer; Patterning the photoresist such that the top of the electroplating layer is open; Depositing platinum on the photoresist and electroplating layer; And removing the photoresist.

상기 희생층은 알루미늄(Al) 또는 산화규소(SiO2)로 이루어질 수 있다.The sacrificial layer may be made of aluminum (Al) or silicon oxide (SiO 2 ).

상기 금속박막을 패터닝하는 단계는, 전자빔 증발기로 접착층(adhesion layer)을 증착한 후, 상기 접착층 상에 금(Au) 또는 백금(Pt)을 증착하여 금속박막을 형성하는 단계를 포함하며, 상기 접착층은 크롬(Cr), 티탄(Ti), 질화티탄(TiN), 티탄-텅스텐(TiW) 또는 니켈(Ni)로 이루어질 수 있다.The patterning of the metal thin film includes depositing an adhesion layer with an electron beam evaporator, and then depositing gold or platinum (Pt) on the adhesive layer to form a metal thin film. It may be made of silver chromium (Cr), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW) or nickel (Ni).

상기 미세전극 어레이 제조방법은, 상기 전기도금을 실시하기 전, 상기 본딩 패드 영역과 레코딩 패드 영역을 패터닝하고, 나머지는 폐쇄시키는 몰드(mold)를 형성하도록 포토레지스트를 도포하며, 상기 전기도금층이 형성된 후에 상기 포토레지스트를 제거하는 단계를 더 포함할 수 있다.In the method of manufacturing the microelectrode array, before the electroplating, a photoresist is applied to form a mold for patterning the bonding pad region and the recording pad region and closing the rest, and the electroplating layer is formed. The method may further include removing the photoresist later.

상기 포토레지스트의 제거는 습식 식각 또는 건식 식각 방법이 사용될 수 있다. Removal of the photoresist may use a wet etching method or a dry etching method.

상기 전기도금 시, 전류 밀도를 조절하여 상기 전기도금층의 표면 거칠기가 제어될 수 있다. During the electroplating, the surface roughness of the electroplating layer may be controlled by adjusting the current density.

상기 전기도금층은 니켈(Ni), 구리(Cu), 금(Au), 백금(Pt), 은(Ag) 또는 니켈코발트(NiCo)로 이루어질 수 있다. The electroplating layer may be made of nickel (Ni), copper (Cu), gold (Au), platinum (Pt), silver (Ag), or nickel cobalt (NiCo).

상기 백금의 증착은 증발기 또는 스퍼터를 통해 이루어질 수 있다.The platinum may be deposited through an evaporator or a sputter.

상기 미세전극 어레이 제조방법은, 상기 백금을 어닐링(annealing) 처리하여, 상기 백금의 표면 거칠기를 조절하는 단계를 더 포함할 수 있다. The method of manufacturing the microelectrode array may further include adjusting the surface roughness of the platinum by annealing the platinum.

상기 미세전극 어레이 제조방법은, 상기 포토레지스트의 제거 후에, 알루미늄 식각액(Al etchant), 희석된 불산(diluted HF(hydrofluoric acid)) 또는 수산화 테트라메틸암모늄(TMAH(tetramethylammonium hydroxide)) 계열의 PR 현상액(developer)을 사용하여 희생층을 제거하는 단계를 더 포함할 수 있다. The method of manufacturing the microelectrode array may include, after removal of the photoresist, an aluminum etchant, diluted hydrofluoric acid (HF), or a PR developer of a tetramethylammonium hydroxide (TMAH) series. developer) to remove the sacrificial layer.

본 발명의 미세전극 어레이 제조방법은 전기도금을 통해 전극을 형성하여 전극 표면의 거칠기를 증가시키고, 전극의 금속 전자의 이동을 활발하게 하여 전극 표면에서의 접촉 임피던스(contact impedance)를 감소시키는 효과가 있다. 이에 따라, 전기적 자극에 따른 신호 추출 시, 잡음이 감소하고, 임피던스가 낮아질 수 있으며, 가역적 반응의 범위가 넓어져서 비가역 반응에 의한 신경계 조직의 손상이 최소화될 수 있다. The method of manufacturing a microelectrode array of the present invention has the effect of increasing the roughness of the electrode surface by forming the electrode through electroplating, and by actively moving the metal electrons of the electrode to reduce the contact impedance on the electrode surface. have. Accordingly, when extracting a signal due to electrical stimulation, noise may be reduced, impedance may be lowered, and a range of reversible responses may be widened, thereby minimizing damage to nervous system tissues due to irreversible responses.

또한, 본 발명의 미세전극 어레이 제조방법은 전기도금 시, 인가되는 전류의 세기를 조절함으로써, 전극 표면의 거칠기를 조절할 수 있는 효과가 있다. In addition, the method of manufacturing a microelectrode array of the present invention has the effect of controlling the roughness of the electrode surface by adjusting the intensity of the applied current during electroplating.

나아가, 본 발명의 미세전극 어레이 제조방법은 전기도금을 통해 양각 형태로 형성된 전극이 종래의 일반적인 박막(thin film) 형태의 전극보다 두꺼우므로, 전극의 수명(lifetime)을 연장시키고, 접촉 임피던스(contact impedance)를 감소시킬 수 있는 효과가 있다.Furthermore, in the method of manufacturing the microelectrode array of the present invention, since the electrode formed in the embossed shape through electroplating is thicker than the conventional thin film type electrode, the lifetime of the electrode is extended and the contact impedance Impedance can be reduced.

도 1은 종래의 미세전극 어레이를 도시한 도면이다.
도 2a 내지 2h는 본 발명의 일 실시예에 따른 미세전극 어레이 제조 과정을 개략적으로 도시한 도면들이다.
1 is a view showing a conventional microelectrode array.
2A to 2H are schematic views illustrating a process of manufacturing a microelectrode array according to an embodiment of the present invention.

이하에서는 첨부한 도면을 참조하여 본 발명의 바람직한 실시예들에 따른 미세전극 어레이 제조방법에 대하여 상세하게 설명한다. Hereinafter, a method of manufacturing a microelectrode array according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 2h는 본 발명의 일 실시예에 따른 미세전극 어레이 제조 과정을 개략적으로 도시한 도면들이다. 본 발명에 따른 미세전극 어레이의 전극은 표면의 거칠기가 크면서, 동시에 양각의 형태로 제조된다. 상기 전극은 전류, 전압 또는 임피던스 등 전기적 신호의 미미한 변화를 측정 시 측정대상에 부착된다. 2A to 2H are schematic views illustrating a process of manufacturing a microelectrode array according to an embodiment of the present invention. The electrodes of the microelectrode array according to the present invention have a large surface roughness and are simultaneously manufactured in an embossed form. The electrode is attached to the measurement object when measuring a slight change in the electrical signal such as current, voltage or impedance.

도 2a를 참조하면, 미리 준비된 기판(110) 상에 희생층(120)으로 사용되는 물질이 증착된다. 희생층(120)은 기판(110) 상에 유연한 미세전극 어레이를 형성한 후, 미세전극 어레이를 기판(110)으로부터 분리(release)시키기 위해 사용된다. 희생층(120)은 알루미늄 식각액(Al etchant), 희석된 불산(diluted HF(hydrofluoric acid)) 또는 수산화 테트라메틸암모늄(TMAH(tetramethylammonium hydroxide)) 계열의 PR 현상액(developer)을 사용하여 제거될 수 있다. Referring to FIG. 2A, a material used as the sacrificial layer 120 is deposited on the prepared substrate 110. The sacrificial layer 120 is used to form the flexible microelectrode array on the substrate 110 and then release the microelectrode array from the substrate 110. The sacrificial layer 120 may be removed using an aluminum etchant, diluted hydrofluoric acid (HF), or a PR developer based on tetramethylammonium hydroxide (TMAH). .

기판(110)은 예를 들어, 실리콘(silicon), 갈륨비소(GaAs), 유리(glass), 석영(Quartz) 등으로 구성될 수 있으며, 희생층(120)은 예를 들어, 알루미늄(Al) 같은 금속 또는 산화규소(SiO2)와 같은 유전체 막으로 구성될 수 있다. The substrate 110 may be formed of, for example, silicon, gallium arsenide (GaAs), glass, quartz, or the like, and the sacrificial layer 120 may be, for example, aluminum (Al). It may be composed of the same metal or a dielectric film such as silicon oxide (SiO 2 ).

상기 희생층(120) 상에는 제1 폴리머(130)가 도포되며, 상기 제1 폴리머(130)로는 제한됨이 없이, 예를 들어, 폴리이미드(polyimide) 또는 패럴린 C(parylene C) 등이 사용될 수 있다. 본 발명의 일 실시예에서는 폴리이미드가 사용되며, 도포 후에는 오븐(oven) 또는 퍼니스(furnace) 등을 통해 경화(curing)시킨다. The first polymer 130 is coated on the sacrificial layer 120, and is not limited to the first polymer 130. For example, polyimide or parylene C may be used. have. In one embodiment of the present invention, polyimide is used, and after application, curing is performed by using an oven or a furnace.

도 2b를 참조하면, 미세전극 어레이는 측정하고자 하는 부위와 직접 접촉하는 레코딩 패드(recording pad)와, 상기 레코딩 패드를 통해 입력된 전기생리적 신호를 처리하는 회로에 연결되는 본딩 패드(bonding pad)와, 상기 2개의 패드 사이를 연결하는 트랜스미션 라인(transmission line)을 포함한다. 상기 2개의 패드와 트랜스미션 라인을 형성하기 위해 리프트 오프(lift off) 공정에 따른 금속 박막 패터닝(metal thin film patterning)이 실시된다. Referring to FIG. 2B, the microelectrode array includes a recording pad in direct contact with a portion to be measured, a bonding pad connected to a circuit for processing an electrophysiological signal input through the recording pad, and a bonding pad. And a transmission line connecting the two pads. In order to form the two pads and the transmission line, metal thin film patterning according to a lift off process is performed.

리프트 오프 공정을 적용하기 위해 증발기(evaporator) 장비가 사용되며, 금속박막(140)이 제1 폴리머(130) 상에 증착된다. 여기서, 제 1폴리머로 사용되는 폴리이미드 상에 금(Au) 또는 백금(Pt)을 증착 시, 접착력(adhesion)을 개선하도록 전자빔 증발기 등의 장비로 접착층(adhesion layer)을 증착한 후, 그 위에 금(Au) 또는 백금(Pt) 등의 금속이 증착되어 금속박막(140)이 형성될 수 있다. 상기 접착층으로 사용되는 금속은, 예를 들어, 크롬(Cr), 티탄(Ti), 질화티탄(TiN), 티탄-텅스텐(TiW), 니켈(Ni) 등이 될 수 있다. Evaporator equipment is used to apply the lift off process, and the metal thin film 140 is deposited on the first polymer 130. Here, when depositing gold (Au) or platinum (Pt) on the polyimide used as the first polymer, to deposit the adhesion layer (adhesion layer) with equipment such as an electron beam evaporator to improve the adhesion (adhesion), thereon A metal such as gold (Au) or platinum (Pt) may be deposited to form a metal thin film 140. The metal used as the adhesive layer may be, for example, chromium (Cr), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), nickel (Ni), or the like.

도 2c를 참조하면, 레코딩 패드와 본딩 패드 영역을 패터닝하면서, 전기 간섭(electrical interference)을 제거하기 위해 트랜스미션 라인을 폐쇄하도록 제2 폴리머(150)가 도포된다. 상기 제2 폴리머(150)는 상기 제1 폴리머(130)와 마찬가지로 제한됨이 없이, 예를 들어, 폴리이미드(polyimide) 또는 패럴린 C(parylene C) 등이 사용될 수 있다. 본 발명의 일 실시예에서 제2 폴리머(150)로 폴리이미드가 사용되며, 도포 후에는 오븐 또는 퍼니스 등을 통해 경화(curing)시킨다. Referring to FIG. 2C, a second polymer 150 is applied to close the transmission line to eliminate electrical interference while patterning the recording pad and bonding pad regions. The second polymer 150 is not limited like the first polymer 130, and for example, polyimide or parylene C may be used. In an embodiment of the present invention, a polyimide is used as the second polymer 150, and after application, curing is performed through an oven or a furnace.

도 2d를 참조하면, 본 발명에서 적용하고자 하는 공정인 전기도금(electroplating)을 실시하기 전에 시드층(seed layer)(160)을 증착한다. 시드층(160)은 도 2c의 과정에서 형성된 패턴의 모든 면에 증착되어야 하므로 스퍼터(sputter) 장비를 사용한다. 사용되는 금속은 접착층으로 크롬, 티탄, 질화티탄, 티탄-텅스텐, 니켈 등이 될 수 있으며, 그 위에 금 등의 금속이 증착될 수 있다. Referring to FIG. 2D, a seed layer 160 is deposited before electroplating, which is a process to be applied in the present invention. Since the seed layer 160 is to be deposited on all sides of the pattern formed in the process of Figure 2c uses a sputter (sputter) equipment. The metal used may be chromium, titanium, titanium nitride, titanium-tungsten, nickel, or the like as the adhesive layer, and a metal such as gold may be deposited thereon.

도 2e를 참조하면, 전기도금이 수행되는 부분인 레코딩 패드 영역과 본딩 패드 영역을 패터닝하고, 나머지는 폐쇄시키는 몰드(mold)를 형성하도록 두꺼운 포토레지스트(thick photoresist)(170)가 도포된다. Referring to FIG. 2E, a thick photoresist 170 is applied to form a mold for patterning the recording pad region and the bonding pad region, which are the portions where electroplating is performed, and closing the rest.

도 2f를 참조하면, 니켈(Ni), 구리(Cu), 금(Au), 백금(Pt), 은(Ag) 또는 니켈코발트(NiCo)와 같은 금속을 전기도금하여 전기도금층(180)이 형성된 후, 몰드로 사용된 포토레지스트(170)가 제거된다. 상기 포토레지스트(170) 제거를 위해 아세톤(aceton)이나 EKC 같은 화학 물질(chemical)을 사용한 습식 식각 방법이 사용되거나, O2 플라즈마 애싱(plasma ashing) 같은 건식 식각 방법이 사용될 수 있다. Referring to FIG. 2F, an electroplating layer 180 is formed by electroplating a metal such as nickel (Ni), copper (Cu), gold (Au), platinum (Pt), silver (Ag), or nickel cobalt (NiCo). Thereafter, the photoresist 170 used as the mold is removed. In order to remove the photoresist 170, a wet etching method using acetone or a chemical substance such as EKC may be used, or a dry etching method such as O 2 plasma ashing may be used.

포토레지스트(170) 제거 후에는 몰드 하부에 있던 시드층(160)이 제거된다. 시드층(160) 제거를 위해, 예를 들어, 금속 식각액(metal etchant) 같은 화학 물질(chemical)에 의한 습식 식각 방법, 아르곤 에칭(Ar etching) 같은 물리적인(physical) 건식 식각 방법, 또는 염소(Cl) 계열의 가스(gas)를 이용한 화학적인 건식 식각 방법이 사용될 수 있다. After removing the photoresist 170, the seed layer 160 under the mold is removed. To remove the seed layer 160, for example, a wet etching method using a chemical such as a metal etchant, a physical dry etching method such as argon etching, or chlorine ( Chemical dry etching method using a Cl) gas may be used.

한편, 도 2f에서는 금속을 전기도금하여 본딩 패드와 레코딩 패드가 동시에 형성되는 것으로 도시하였으나, 본 발명의 다른 실시예에 따르면, 본딩 패드와 레코딩 패드는 각각 개별적인 공정으로 형성될 수 있다. 즉, 본딩 패드는 니켈(Ni), 구리(Cu), 금(Au), 백금(Pt), 은(Ag) 또는 니켈코발트(NiCo)와 같은 금속을 전기도금하여 형성될 수 있으며, 레코딩 패드는 증착기 또는 스퍼터를 통해 금(Au), 백금(Pt), 은(Ag), 텅스텐(W), 몰리브덴(Mo), 구리(Cu), 스테인레스강(SUS-27), 철(Fe) 또는 은-염화은(Ag-AgCl)과 같은 금속을 증착하여 형성될 수 있다.Meanwhile, in FIG. 2F, the bonding pad and the recording pad are simultaneously formed by electroplating metal, but according to another exemplary embodiment, the bonding pad and the recording pad may be formed by separate processes. That is, the bonding pad may be formed by electroplating a metal such as nickel (Ni), copper (Cu), gold (Au), platinum (Pt), silver (Ag), or nickel cobalt (NiCo). Gold (Au), Platinum (Pt), Silver (Ag), Tungsten (W), Molybdenum (Mo), Copper (Cu), Stainless Steel (SUS-27), Iron (Fe) or Silver It may be formed by depositing a metal such as silver chloride (Ag-AgCl).

도 2g를 참조하면, 본 발명에서 적용하고자 하는 백금(Pt)(200)을 증착하기 위해 포토레지스트(190)가 패터닝된다. Referring to FIG. 2G, the photoresist 190 is patterned to deposit platinum (Pt) 200 to be applied in the present invention.

도 2h를 참조하면, 백금은 습식 또는 건식 식각 방법으로는 잘 제거가 되지 않으므로, 리프트 오프 공정을 통해 패터닝이 실시된다. 백금(200)을 증착하도록 접착층으로 예를 들어, 크롬, 티탄, 질화티탄, 티탄-텅스텐, 니켈 등이 사용될 수 있으며, 증발기(evaporator)를 사용하여 백금이 상기 접착층 상에 증착된다. 백금(200)이 증착된 후에는 상기 도 2g의 과정에서 형성된 포토레지스트(190)를 제거하도록 리프트 오프 공정이 실시되며, 전기도금층(180) 위에만 백금(200)이 남겨진다. Referring to FIG. 2H, since platinum is not easily removed by a wet or dry etching method, patterning is performed through a lift-off process. For example, chromium, titanium, titanium nitride, titanium-tungsten, nickel, or the like may be used as an adhesive layer to deposit platinum 200, and platinum is deposited on the adhesive layer using an evaporator. After the platinum 200 is deposited, a lift-off process is performed to remove the photoresist 190 formed in the process of FIG. 2G, and the platinum 200 is left only on the electroplating layer 180.

상기 백금(200)의 증착 시, 백금(200)의 증착률(deposition rate)을 조절하거나, 백금(200)을 어닐링(annealing) 처리하여, 백금(200) 자체의 표면 거칠기도 조절할 수 있다. When depositing the platinum 200, the deposition rate of the platinum 200 may be adjusted or the annealing may be performed to anneal the platinum 200 to adjust the surface roughness of the platinum 200 itself.

본 발명에서는 전극 표면의 거칠기를 높이기 위한 방법으로 백금을 전기도금하는 대신 니켈, 구리 또는 금을 전기도금한 후, 그 위에 박막(thin film) 형태로 백금(200)을 증착시킴으로써, 공정 단가를 낮출 수 있다. In the present invention, instead of electroplating platinum as a method for increasing the roughness of the electrode surface, electroplating nickel, copper or gold, and then depositing platinum 200 in the form of a thin film thereon, thereby lowering the process cost. Can be.

일반적으로 스퍼터(sputter)나 증발기(evaporator)같은 박막(thin film)을 형성하는 장비를 사용하여 금속을 증착하게 되면 그 표면이 매끄러워 금속 전극 표면의 원하는 거칠기를 얻을 수 없다. In general, the deposition of metal using equipment for forming a thin film, such as a sputter or an evaporator, results in a smooth surface that does not provide the desired roughness of the metal electrode surface.

그러나, 본 발명은 전기도금을 통해 전극을 형성하며, 전기도금 시 인가되는 전류밀도(current density)를 조절하여 금속의 그레인 사이즈(grain size)를 조절할 수 있다. 따라서, 본 발명은 전기도금층(180)의 표면 거칠기를 조절할 수 있으며, 전기도금층(180) 상에 전자빔 증발기나 스퍼터 장비를 통해 증착되는 백금(200)의 두께는 전기도금층(180)의 표면 거칠기에 비해 매우 작으므로, 금속 전극 표면은 거칠게 형성된다. However, the present invention forms the electrode through electroplating, it is possible to control the grain size (grain size) of the metal by adjusting the current density (current density) applied during the electroplating. Accordingly, the present invention can control the surface roughness of the electroplating layer 180, the thickness of the platinum 200 deposited on the electroplating layer 180 through the electron beam evaporator or sputtering equipment is the surface roughness of the electroplating layer 180 Since it is very small in comparison, the metal electrode surface is roughened.

전극 표면의 거칠기가 너무 클 경우 전극과 전해질의 경계에 균일하지 못한 전류 밀도를 나타나게 되며, 비가역적 반응이 커져 신경계 조직의 손상이 커지는 현상이 발생할 수 있다. 그러나, 본 발명은 전기도금의 인가 전류를 조절하여 전극 표면의 거칠기를 조절할 수 있는 장점이 있다. If the surface roughness of the electrode is too large, an uneven current density appears at the boundary between the electrode and the electrolyte, and the irreversible reaction may increase, causing damage to the nervous system tissue. However, the present invention has the advantage of controlling the roughness of the electrode surface by adjusting the applied current of electroplating.

또한, 유연한 미세전극 어레이 제조에 사용되는 폴리머인 폴리이미드나 패럴린 C(parylene C)는 물리적, 기계적 강도를 고려하여 수 마이크로미터 두께 이상으로 형성하는데, 여기에 전극으로 사용되는 금속을 양각의 형태로 형성하기 위해서 일반적인 박막(thin film)을 증착하는 방법을 사용하면, 재료 소모가 크고 시간이 오래 걸리는 등의 문제가 발생한다. 그러나, 본 발명은 전기도금을 이용하여, 양각 형태의 전극을 형성함으로써, 상기 문제를 해결할 수 있다. In addition, polyimide or parylene C, which is a polymer used to manufacture flexible microelectrode arrays, is formed to a thickness of several micrometers or more in consideration of physical and mechanical strength, and the metal used as an electrode is embossed. In order to form a thin film, a method of depositing a general thin film generates a problem such as high material consumption and a long time. However, the present invention can solve the above problem by forming an embossed electrode using electroplating.

상기한 본 발명의 바람직한 실시예는 단지 예시의 목적을 위해 개시된 것이고, 본 발명에 대한 통상의 지식을 가지는 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가가 가능할 것이며, 이러한 수정, 변경 및 부가는 하기의 특허청구범위에 속하는 것으로 보아야 할 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, And additions should be considered as falling within the scope of the following claims.

110: 기판
120: 희생층
130: 제1 폴리머
140: 금속박막
150: 제2 폴리머
160: 시드층
170: 포토레지스트
180: 전기도금층
190: 포토레지스트
200: 백금
110: substrate
120: sacrificial layer
130: first polymer
140: metal thin film
150: second polymer
160: seed layer
170: photoresist
180: electroplating layer
190: photoresist
200: platinum

Claims (10)

미리 준비된 실리콘 기판 상에 희생층을 증착하는 단계;
상기 증착된 희생층 상에 제1 폴리머를 도포하여 패터닝한 후, 열 경화시키는 단계;
상기 제1 폴리머 상에 본딩 패드 영역과, 트랜스미션 라인과, 레코딩 패드 영역을 형성하도록 금속박막을 패터닝하는 단계;
상기 트랜스미션 라인 영역을 폐쇄하고, 상기 본딩 패드 영역과 레코딩 패드 영역을 패터닝하도록 제2 폴리머를 도포하는 단계;
상기 제2 폴리머와 금속박막 상에 스퍼터 장비를 통해 시드층을 증착하는 단계;
상기 본딩 패드 영역과 레코딩 패드 영역에 대해 금속을 전기도금하여 전기도금층을 형성하는 단계;
상기 전기도금층의 상부가 개방되도록 포토레지스트를 패터닝하는 단계;
상기 포토레지스트와 전기도금층 상에 백금을 증착시키는 단계; 및
상기 포토레지스트를 제거하는 단계를 포함하는 것을 특징으로 하는 미세전극 어레이 제조방법.
Depositing a sacrificial layer on a silicon substrate prepared in advance;
Applying and patterning a first polymer on the deposited sacrificial layer, followed by thermal curing;
Patterning a metal thin film to form a bonding pad region, a transmission line, and a recording pad region on the first polymer;
Closing the transmission line region and applying a second polymer to pattern the bonding pad region and the recording pad region;
Depositing a seed layer on the second polymer and the metal thin film through sputtering equipment;
Electroplating a metal on the bonding pad region and the recording pad region to form an electroplating layer;
Patterning the photoresist such that the top of the electroplating layer is open;
Depositing platinum on the photoresist and electroplating layer; And
And removing the photoresist.
제 1 항에 있어서, 상기 희생층은 알루미늄(Al) 또는 산화규소(SiO2)로 이루어지는 것을 특징으로 하는 미세전극 어레이 제조방법. The method of claim 1, wherein the sacrificial layer is made of aluminum (Al) or silicon oxide (SiO 2 ). 제 1 항에 있어서, 상기 금속박막을 패터닝하는 단계는, 전자빔 증발기로 접착층(adhesion layer)을 증착한 후, 상기 접착층 상에 금(Au) 또는 백금(Pt)을 증착하여 금속박막을 형성하는 단계를 포함하며, 상기 접착층은 크롬(Cr), 티탄(Ti), 질화티탄(TiN), 티탄-텅스텐(TiW) 또는 니켈(Ni)로 이루어지는 것을 특징으로 하는 미세전극 어레이 제조방법.The method of claim 1, wherein the patterning of the metal thin film comprises depositing an adhesion layer with an electron beam evaporator and then depositing gold or platinum on the adhesive layer to form a metal thin film. And the adhesive layer comprises chromium (Cr), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW) or nickel (Ni). 제 1 항에 있어서, 상기 전기도금을 실시하기 전, 상기 본딩 패드 영역과 레코딩 패드 영역을 패터닝하고, 나머지는 폐쇄시키는 몰드(mold)를 형성하도록 포토레지스트를 도포하며, 상기 전기도금층이 형성된 후에 상기 포토레지스트를 제거하는 단계를 더 포함하는 것을 특징으로 하는 미세전극 어레이 제조방법.The method of claim 1, wherein before the electroplating, a photoresist is applied to form a mold for patterning the bonding pad region and the recording pad region, and closing the rest, and after the electroplating layer is formed. The method of claim 1, further comprising removing the photoresist. 제 4 항에 있어서, 상기 포토레지스트의 제거는 습식 식각 또는 건식 식각 방법이 사용되는 것을 특징으로 하는 미세전극 어레이 제조방법. The method of claim 4, wherein the removal of the photoresist is performed using a wet etching method or a dry etching method. 제 1 항에 있어서, 상기 전기도금 시, 전류 밀도를 조절하여 상기 전기도금층의 표면 거칠기를 제어하는 것을 특징으로 하는 미세전극 어레이 제조방법. The method of claim 1, wherein the surface roughness of the electroplating layer is controlled by adjusting a current density during the electroplating. 제 1 항에 있어서, 상기 전기도금층은 니켈(Ni), 구리(Cu), 금(Au), 백금(Pt), 은(Ag) 또는 니켈코발트(NiCo)로 이루어지는 것을 특징으로 하는 미세전극 어레이 제조방법. The method of claim 1, wherein the electroplating layer is nickel (Ni), copper (Cu), gold (Au), platinum (Pt), silver (Ag) or nickel cobalt (NiCo) fabrication of the microelectrode array characterized in that Way. 제 1 항에 있어서, 상기 백금의 증착은 증발기 또는 스퍼터를 통해 이루어지는 것을 특징으로 하는 미세전극 어레이 제조방법. The method of claim 1, wherein the platinum is deposited through an evaporator or a sputter. 제 1 항에 있어서, 상기 백금을 어닐링(annealing) 처리하여, 상기 백금의 표면 거칠기를 조절하는 단계를 더 포함하는 것을 특징으로 하는 미세전극 어레이 제조방법. The method of claim 1, further comprising adjusting the surface roughness of the platinum by annealing the platinum. 제 1 항에 있어서, 상기 포토레지스트의 제거 후에, 알루미늄 식각액(Al etchant), 희석된 불산(diluted HF(hydrofluoric acid)) 또는 수산화 테트라메틸암모늄(TMAH(tetramethylammonium hydroxide)) 계열의 PR 현상액(developer)을 사용하여 희생층을 제거하는 단계를 더 포함하는 것을 특징으로 하는 미세전극 어레이 제조방법.The method of claim 1, wherein after removal of the photoresist, an aluminum etchant, diluted hydrofluoric acid (HF), or a tetramethylammonium hydroxide (TMAH) series PR developer is used. Microelectrode array manufacturing method further comprising the step of removing the sacrificial layer using.
KR1020100016300A 2010-02-23 2010-02-23 Manufacturing method of microelectrode array KR101125603B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020100016300A KR101125603B1 (en) 2010-02-23 2010-02-23 Manufacturing method of microelectrode array
PCT/KR2010/004850 WO2011105665A1 (en) 2010-02-23 2010-07-23 Manufacturing method of microelectrode array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100016300A KR101125603B1 (en) 2010-02-23 2010-02-23 Manufacturing method of microelectrode array

Publications (2)

Publication Number Publication Date
KR20110096825A KR20110096825A (en) 2011-08-31
KR101125603B1 true KR101125603B1 (en) 2012-03-27

Family

ID=44507049

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100016300A KR101125603B1 (en) 2010-02-23 2010-02-23 Manufacturing method of microelectrode array

Country Status (2)

Country Link
KR (1) KR101125603B1 (en)
WO (1) WO2011105665A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101362750B1 (en) * 2012-09-25 2014-02-18 (주) 마이크로핏 Thin film neural electrode, its manufacturing method and pcb connecting method using the same

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102556932B (en) * 2011-12-19 2015-01-21 上海交通大学 Microelectrode array with adjustable electrode point distance
WO2015038974A1 (en) * 2013-09-13 2015-03-19 University Of Utah Research Foundation Micro-molded electrodes, arrays, and methods of making the same
WO2015042539A1 (en) * 2013-09-20 2015-03-26 Board Of Regents, The University Of Texas System Fabrication of iridium oxide ph sensors and sensor arrays
CN111956218B (en) * 2020-08-10 2024-04-16 中国科学院上海微系统与信息技术研究所 Flexible brain electrode with electrochemical and electrophysiological detection functions and preparation method thereof
US20220157655A1 (en) * 2020-11-19 2022-05-19 Applied Materials, Inc. Electroplating with temporary features
CN114520070A (en) * 2021-12-31 2022-05-20 上海脑虎科技有限公司 Nerve electrical stimulation electrode and preparation method thereof
CN117766198A (en) * 2023-12-21 2024-03-26 深圳微灵医疗科技有限公司 Flexible electrode manufacturing method, flexible electrode and readable storage medium

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100705757B1 (en) * 2005-03-15 2007-04-10 한국과학기술원 Flip Chip Having Ultra-fine Pitch and Fabrication Method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750106A (en) * 1992-01-31 1995-02-21 Osaka Gas Co Ltd Micron and submicron order solid microelectrode of conductive polymer and its manufacture
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
TWI286372B (en) * 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
KR100896841B1 (en) * 2007-10-04 2009-05-12 주식회사 동부하이텍 Method for forming bond pad on fabricating a semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100705757B1 (en) * 2005-03-15 2007-04-10 한국과학기술원 Flip Chip Having Ultra-fine Pitch and Fabrication Method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101362750B1 (en) * 2012-09-25 2014-02-18 (주) 마이크로핏 Thin film neural electrode, its manufacturing method and pcb connecting method using the same

Also Published As

Publication number Publication date
WO2011105665A1 (en) 2011-09-01
KR20110096825A (en) 2011-08-31

Similar Documents

Publication Publication Date Title
KR101125603B1 (en) Manufacturing method of microelectrode array
US7706893B2 (en) High density array of micro-machined electrodes for neural stimulation
TWI288958B (en) A miniaturized contact spring
EP3551277B1 (en) Implantable electrode and method for manufacturing
KR101033907B1 (en) Manufacturing method of microelectrode array and connector connecting method using the same
JPH0817192B2 (en) Method for manufacturing probe head for semiconductor LSI inspection device
CN110088877A (en) For enhancing the biological sensor electrode of the nano-patterning of sensor signal and sensitivity
US20210371987A1 (en) Porous platinum nanorod electrode array flexible sensor devices and fabrication
CN103101878B (en) Method for preparing silicon-based microelectrode
US7653439B2 (en) Electrode structure and methods for making and using same
Bauerdick et al. Substrate-integrated microelectrodes with improved charge transfer capacity by 3-dimensional micro-fabrication
US20090246515A1 (en) Neuroelectrode Coating and Associated Methods
KR101362750B1 (en) Thin film neural electrode, its manufacturing method and pcb connecting method using the same
US8679221B2 (en) Method for producing alumina template of nanorods, alumina template, and nanorods
WO2004092435A1 (en) Metal structure and method for production thereof
Babaroud et al. Surface modification of multilayer graphene electrodes by local printing of platinum nanoparticles using spark ablation for neural interfacing
US20200232098A1 (en) Pattern formation using catalyst blocker
Cheung et al. Nanostructured electrodes for improved neural recording
Liu et al. Parylene-based stretchable neural electrodes with serpentine interconnects
JP4401531B2 (en) Method for forming fine pattern electrode and optical element
Röhler et al. Development and characterization of a needle-type microelectrode array for stimulation and recording of neuronal activity
KR20230139623A (en) Neural Interface and Manufacturing method thereof
JPH02119142A (en) Manufacture of semiconductor device
CN111725057A (en) Method for manufacturing semiconductor device
EP2453471A2 (en) Method for electrodeposition of an elctrode on a dielectric substrate

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20150303

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20160302

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20170302

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20180302

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20190226

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20200302

Year of fee payment: 9