KR101109555B1 - Nonvolatile memory device and reading method thereof - Google Patents
Nonvolatile memory device and reading method thereof Download PDFInfo
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- KR101109555B1 KR101109555B1 KR1020100057153A KR20100057153A KR101109555B1 KR 101109555 B1 KR101109555 B1 KR 101109555B1 KR 1020100057153 A KR1020100057153 A KR 1020100057153A KR 20100057153 A KR20100057153 A KR 20100057153A KR 101109555 B1 KR101109555 B1 KR 101109555B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Abstract
The present invention relates to a nonvolatile memory device. The nonvolatile memory device of the present invention includes a memory cell array including memory cells connected between first and second bit lines and a source line, and reference memory cells connected between first and second reference bit lines and a source line. And a read and write circuit connected to the first and second bit lines and the source line.
Description
The present invention relates to a memory, and more particularly to a nonvolatile memory device and a read method thereof.
A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge, Germanium), gallium arsenide (GaAs, gallium arsenide), or indium phospide (InP). to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.
Volatile memory devices lose their stored data when their power supplies are interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).
In order to reduce the production cost of semiconductor memory devices, various methods have been studied. One of the methods of reducing the production cost of the semiconductor memory device is to reduce the line width. When the line width is reduced, the degree of integration of the semiconductor memory device is improved. Improved integration increases the number of semiconductor memory chips produced from one wafer. Therefore, the production cost of the semiconductor memory device is reduced.
Another method of reducing the production cost of a semiconductor memory device is to improve the degree of integration of the semiconductor memory device through a design change. For example, when the number of conductive lines in a semiconductor memory chip is reduced, the degree of integration of the semiconductor memory device is improved and the unit cost is reduced.
It is an object of the present invention to provide a nonvolatile memory device having an improved degree of integration and a read method thereof.
In an embodiment, a nonvolatile memory device may include a memory cell array including memory cells connected between first and second bit lines and a source line; A reference memory cell array including reference memory cells coupled between first and second reference bit lines and the source line; And read and write circuits connected to the first and second bit lines and the source line.
In example embodiments, the reference memory cell array may include a first reference memory cell connected between the first reference bit line and the source line; And a second reference memory cell connected between the second reference bit line and the source line.
In an embodiment, the first reference memory cell includes a first select transistor coupled to the source line, the second reference memory cell includes a second select transistor coupled to the source line, and the first and second The two select transistors are controlled in response to a common reference word line.
In exemplary embodiments, the first reference memory cell may further include a first resistor connected to the first select transistor and the first bit line, and the second reference memory cell may include the second select transistor and the second bit. And a second resistor coupled to the line.
In an embodiment, the first resistor and the second resistor have different resistance values.
In an embodiment, in a read operation, the read and write circuit provides a second current to a selected bit line of the first and second bit lines and a first current to the first and second reference bit lines. It is configured to provide.
In an embodiment, the amount of the first current is greater than the amount of the second current.
In an embodiment, in a read operation, the read and write circuit may be configured to include a selected memory connected to the selected bit line based on a first voltage induced by the first current and a second voltage induced by the second current. And determine the resistance state of the cell.
In an embodiment, in a read operation, the read and write circuit is configured to determine the selected memory cell as a high resistance state when the second voltage has a level higher than the first voltage.
In an embodiment, in a read operation, the read and write circuit is configured to determine the selected memory cell as a low resistance state when the second voltage has a level lower than the first voltage.
In an embodiment, when the selected memory cell is written to a low resistance state, the read and write circuit is configured to provide a write current to the selected bit line of the first and second bit lines.
In an embodiment, when the selected memory cell is written to a high resistance state, the read and write circuit is configured to provide a write current to the source line, and an unselected bit line of the first and second bit lines floats. do.
In example embodiments, the read and write circuit may include first and second upper transistors connected to the first and second reference bit lines; And first and second lower transistors connected to the first and second bit lines.
In example embodiments, the read and write circuit may include a power supply circuit configured to supply a power voltage to the first and second lower transistors when the selected memory cell is written to a low resistance state; And a ground supply circuit configured to supply a ground voltage to the source line when the selected memory cell is written to a low resistance state.
In an embodiment, when the selected memory cell is written to the high resistance state, the power supply circuit is configured to supply a power voltage to the source line, and when the selected memory cell is written to the high resistance state, the ground The supply circuit is configured to supply a ground voltage to the first and second lower transistors.
In example embodiments, the read and write circuit may include a first current source configured to supply a first current to the first and second upper transistors in a read operation; A second current source configured to supply a second current to the first and second bottom transistors in a read operation; And an amplifier configured to sense a difference between the first voltage induced by the first current and the second voltage induced by the second current.
In an embodiment, the first and second upper transistors are turned on together in a read operation and turned off together in a memory cell write operation.
In example embodiments, when a selected reference memory cell of the first and second reference memory cells is written, the selected upper transistor of the first and second upper transistors is turned on and the other upper transistor is turned on. Is off.
In example embodiments, the first and second reference memory cells and the first and second memory cells each include a spin torque transfer magnetoresistive element.
According to an embodiment of the present disclosure, a method of reading a nonvolatile memory device may include: grounding a source line; Supplying a first current to an electrical path connected to the source line through two reference bit lines and two reference memory cells respectively corresponding to the two reference bit lines; Supplying a second current to an electrical path connected to the source line through a bit line and a selected memory cell; And determining a logic state of the selected memory cell based on voltages induced by the first and second currents, respectively.
According to the present invention, reference memory cells connected to two reference bit lines share one source line. Reference memory cells connected to two reference bit lines share one reference word line. Thus, a nonvolatile memory device having an improved degree of integration and a read method thereof are provided.
1 is a block diagram illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a memory cell array, a reference cell array, and read and write circuits of FIG. 1.
3 is a circuit diagram illustrating a first access unit of FIG. 2.
4 is a diagram illustrating an embodiment of a memory cell of FIG. 3.
FIG. 5 is a circuit diagram illustrating the first reference access unit of FIG. 2.
6 is a circuit diagram illustrating a first read and write unit of FIG. 2.
FIG. 7 is a circuit diagram illustrating a current path of a first access unit and a first read and write unit when a selected memory cell is written in a low resistance state. FIG.
8 is a circuit diagram showing a current path of a first access unit and a first read and write unit when the selected memory cell is written in a high resistance state.
9 and 10 are circuit diagrams showing current paths of a first access unit, a first reference access unit, and a first read and write unit when a selected memory cell is read.
FIG. 11 is a circuit diagram illustrating an equivalent circuit of the first access unit, the first reference access unit, and the first read and write unit shown in FIGS. 9 and 10.
12 is a circuit diagram showing a current path of a first reference access unit and a first read and write unit when reference memory cells in high and low resistance states are written.
13 is a flowchart illustrating a reading method of a nonvolatile memory device according to an embodiment of the present invention.
FIG. 14 is a block diagram illustrating a memory system including the nonvolatile memory device of FIG. 1.
FIG. 15 is a block diagram illustrating an application example of the memory system of FIG. 14.
FIG. 16 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 15.
DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . Identical components will be referred to using the same reference numerals. Similar components will be referred to using similar reference numerals.
1 is a block diagram illustrating a
The
Memory cells of the
In exemplary embodiments, memory cells may store data in the form of a resistance value. For example, memory cells having a first resistance value will correspond to the first logic state. Memory cells having a second resistance value will correspond to the second logic state. That is, the memory cells may be variable resistance memory cells.
The
In exemplary embodiments, the reference memory cells of the
The read and write
The read and write
The read and write
The
For example, the
2 is a block diagram illustrating the
Referring to FIG. 2, the
The first to
The first to nth access units 111-11n may be configured to share the word lines WL. For example, memory cells located in the same row among the memory cells of the first through
The first to nth
The first through nth reference access units 121-12n may be configured to share the reference word line RWL. For example, the reference memory cells of the first to nth
The first to nth read and write
3 is a circuit diagram illustrating the
Each memory cell MC includes a selection transistor ST and a variable resistance element VR. The variable resistance element VR is connected to the bit line BL and the selection transistor ST. The selection transistor ST is connected to the source line SL.
In an exemplary embodiment, the variable resistance element VR may be configured to store data in the form of a resistance value. The resistance value of the variable resistance element VR may be changed by a signal transmitted through the bit line BL and the source line SL, for example, a voltage or a current.
The selection transistor ST is connected between the variable resistance element VR and the source line SL and operates in response to the corresponding word line WL. That is, the selection transistor ST is turned on and off in accordance with the voltage level of the word line WL. Select transistors ST located in the same row are connected to a common word line WL. Thus, the memory cells MC in a row unit are selected and deselected by the word line voltage.
As shown in FIG. 3, memory cells MC located in the same column are connected to a common bit line BL. For example, the memory cells MC located in the first column are connected to the first bit line BL1, and the memory cells MC located in the second column are connected to the second bit line BL2 and are located in the third column. The memory cells MC are connected to the third bit line BL3, and the memory cells MC located in the fourth column are connected to the fourth bit line BL4.
Memory cells MC connected to two bit lines are configured to share one source line. In exemplary embodiments, the memory cells MC connected to the first and second bit lines BL1 and BL2 share the first source line SL1, and the third and fourth bit lines BL3 and BL4. Memory cells MC connected to are configured to share the second source line SL2. That is, the memory cells MC are connected between the first and second bit lines BL1 and BL2 and the first source line SL2, and the third and fourth bit lines BL3 and BL4 and the first and second bit lines BL3 and BL4. Memory cells MC are connected between the two source lines SL2.
Since the source line SL is shared by the two bit lines BL, the number of the source lines SL is reduced in comparison with a conventional nonvolatile memory device. Thus, the degree of integration of the
4 is a diagram illustrating an embodiment of a memory cell MC of FIG. 3. Referring to FIG. 4, the variable resistance element VR and the selection transistor ST are connected between the bit line BL and the source line SL.
The variable resistance device VR includes a pinned magnetization layer PL, a free magnetization layer FL, and an intermediate layer S. The pinned magnetization layer PL includes a ferroelectric material. The pinned magnetization layer PL has a fixed magnetization direction. For example, the magnetization direction of the pinned magnetization layer PL is indicated by an arrow.
The free magnetization layer FL includes a ferroelectric material. The free magnetization layer FL has a magnetization direction that changes according to a bias condition. For example, the magnetization direction of the free magnetization layer FL is indicated by an arrow.
The intermediate layer S acts as a tunnel barrier. In exemplary embodiments, the intermediate layer S may be composed of crystallized magnesium oxide (MgO).
When the magnetization directions of the fixed magnetization layer PL and the free magnetization layer FL coincide, the variable resistance element VR may correspond to a low resistance state. When the magnetization directions of the fixed magnetization layer PL and the free magnetization layer are different, the variable resistance element VR will correspond to a high resistance state.
In exemplary embodiments, the variable resistance element VR may be a spin torque transfer magnetoresistive element.
When the write current flows from the bit line BL to the source line SL, the variable resistance element VR will be written in a low resistance state. When the write current flows from the source line SL to the bit line BL, the variable resistance element VR will be written in a high resistance state.
For example, the
FIG. 5 is a circuit diagram illustrating the first
The reference memory cells RMC include a selection transistor ST and a resistor. The reference memory cells RMC are configured to include one of the high resistance element RH and the low resistance element RL.
The reference memory cells RMC are commonly connected to the reference word line RWL. That is, the selection transistors ST of the reference memory cells RMC are controlled by the common reference word line RWL.
One reference memory cell RMC is connected to each reference bit line RBL. Two reference bit lines RBL correspond to one reference source line RSL. That is, two reference memory cells RMC are connected to one reference source line RSL. Two reference memory cells RMC connected to one reference source line RSL include a high resistance element RH and a low resistance element RL, respectively.
In exemplary embodiments, each reference memory cell RMC may have the same structure as the memory cell MC. That is, the high resistance element RH of the reference memory cell RMC may be the magnetoresistive element VR written in the high resistance state. The low resistance element RL of the reference memory cell RMC may be a magnetoresistive element VR written in a low resistance state.
As shown in FIG. 5, reference memory cells RMC connected to two reference bit lines RBL are configured to share one reference source line RSL. Thus, the degree of integration of the
For example, the first
FIG. 6 is a circuit diagram illustrating the first read and write
The first to fourth lower transistors TB1 to TB4 are connected to the first to fourth bit lines BL1 to BL4 of the
The first to fourth upper transistors TT1 to TT4 are connected to the first to fourth reference bit lines RBL1 to RBL4 of the
The power supply circuit PSC is connected to the fifth transistor T5, the first to fourth lower transistors TB1 to TB4, and the source line SL and the reference source line RSL. The power supply circuit PSC is configured to supply the power supply voltage Vcc in response to the low resistance write inversion signal / WRL and the high resistance write inversion signal / WRH. The power supply circuit PSC operates in response to the low resistance write inversion signal / WRL and operates in response to the first transistor T1 connected to the power supply voltage Vcc and the high resistance write inversion signal / WRH. The second transistor T2 is connected to the power supply voltage Vcc.
The ground supply circuit GSC is connected to the fifth transistor T5, the first to fourth lower transistors TB1 to TB4, and the source line SL and the reference source line RSL. The ground supply circuit GSC is configured to supply the ground voltage Vss in response to the low resistance write signal WRL, the high resistance write signal WRH, and the read signal RD. The ground supply circuit GSC operates in response to the low resistance write signal WRL and the read signal RD, and responds to the third transistor T3 connected to the ground voltage Vss and the high resistance write signal WRH. It operates and includes a fourth transistor T4 connected to the ground voltage Vss.
The first reference source line RSL1 and the first source line SL1 are connected to each other, and the second reference source line RSL2 and the second source line SL2 are connected to each other. That is, the source lines SL or RSL are shared in the
The fifth transistor includes the power supply circuit PSC, the ground supply circuit GSC, and the first to fourth lower transistors TB1 to TB4 in response to the reference write signal WRR. Electrical connection to the TT1-TT4.
The sixth transistor T6 connects the reference node RN and the first current source CS1 of the amplifier SA to the first to fourth upper transistors TT1 to TT4 and the fifth in response to the read signal RD. It is electrically connected to the transistor T5.
The seventh transistor T7 connects the cell node CN and the second current source CS2 of the amplifier SA to the first to fourth lower transistors TB1 to TB4 and the fifth in response to the read signal RD. It is electrically connected to the transistor T5.
One end of the first current source CS1 is connected to the sixth transistor T6 and the reference node RN of the amplifier SA. The other end of the first current source CS1 is connected to the power supply voltage Vcc. The first current source CS1 is configured to supply the first current 2I to the reference node RN of the sixth transistor T6 and the amplifier SA.
One end of the second current source CS2 is connected to the cell node CN of the seventh transistor T7 and the amplifier SA. The other end of the second current source CS2 is connected to the power supply voltage Vcc. The second current source CS2 is configured to supply the second current I to the cell node CN of the seventh transistor T7 and the amplifier SA. By way of example, the amount of the first current is greater than the amount of the second current. For example, the amount of the first current 2I will be twice the amount of the second current I.
The amplifier SA is configured to compare the voltage of the reference node RN with the voltage of the cell node CN. The amplifier SA is configured to output the comparison result as the read data DOUT.
FIG. 7 is a circuit diagram illustrating a current path of the
Table 1 shows the bias conditions of the control signals when the selected memory cell MC is written to the low resistance state.
7 and 8 and Table 1, during the write operation, the first to fourth upper control signals WRT1 to WRT4 are controlled to be logic low. That is, the first to fourth upper transistors TT1 to TT4 are turned off.
The control signal WRB1 corresponding to the selected memory cell MC among the first to fourth lower control signals WRB1 to WRB4 is controlled to be logic high, and the remaining control signals WRB2 to WRB4 are controlled to be logic low. do. That is, the lower transistor TB1 connected to the bit line BL1 corresponding to the selected memory cell MC is turned on, and the remaining lower transistors TB2 to TB4 are turned off. For example, when the memory cell MC connected to the first bit line BL1 is written, the first lower control signal WRB1 may be controlled to be logic high. That is, the first lower transistor TB1 connected to the first bit line BL1 may be turned on.
In the low resistance write operation, the low resistance write signal WRL is controlled at logic high and the high resistance write signal WRH is controlled at logic low. Thus, the low resistance write inversion signal / WRL is controlled to logic low and the high resistance write inversion signal / WRH is controlled to logic high. That is, the first transistor T1 of the power supply circuit PSC is turned on and the second transistor T2 is turned off. The third transistor T3 of the ground supply circuit GSC is turned on and the fourth transistor T4 is turned off.
In the write operation, the read signal RD and the reference write signal WRR are controlled to be logic low.
In response to the bias conditions described in Table 1, the first read and write
As illustrated in FIG. 7, the power supply circuit PSC may include a first lower transistor TB1, a first bit line BL1, a variable resistance element VR, a select transistor ST, and a first source line. It is transmitted to the ground supply circuit GSC through SL1). That is, the power supply circuit PSC supplies the power supply voltage Vcc to the first bit line BL1, and the ground supply circuit GSC supplies the ground voltage Vss to the first source line SL1. Can be understood. Since current flows from the first bit line BL1 to the first source line SL1 through the variable resistance element VR, the variable resistance element VR of the selected memory cell MC will be written in a low resistance state. .
For example, the first bit line BL1 has been described as being selected. However, even when one of the second to fourth bit lines BL2 to BL4 is selected, the selected memory cell MC will be written in a low resistance state as described with reference to FIGS. 6 and 7.
For example, when the second bit line BL2 is selected, the power supply circuit PSC supplies the power supply voltage Vcc to the second bit line BL2 and the ground supply circuit GSC supplies the first source line. The ground voltage Vss will be supplied to SL1. That is, the current will flow from the second bit line BL2 to the first source line SL1 through the selected memory cell MC.
8 is a circuit diagram illustrating a current path of the
Table 2 shows the bias conditions of the control signals when the selected memory cell MC is written to the high resistance state.
6, 8, and 2, an operation of writing the selected memory cell MC in a high resistance state will be described.
Compared with the bias conditions of Table 1, the bias of the high resistance write signal (WRH), high resistance write inversion signal (/ WRH), low resistance write signal (WRL), and low resistance write inversion signal (/ WRL) in Table 2 The conditions are described differently. The high resistance write signal (WRH), the high resistance write inversion signal (/ WRH), the low resistance write signal (WRL), and the low resistance write inversion signal (/ WRL) are the power supply circuit (PSC) and the ground supply circuit (GSC). Are the signals provided to Thus, as compared with the low resistance write operation, the operations of the power supply circuit PSC and the ground supply circuit GSC during the high resistance write operation will be changed.
In the high resistance write operation, the low resistance write signal WRL is controlled to a logic low and the high resistance write signal WRH is controlled to a logic high. Thus, the low resistance write inversion signal / WRL is controlled at logic high and the high resistance write inversion signal / WRH is controlled at logic low.
In response to the bias conditions described in Table 2, the first read and write
It will be understood that the power supply circuit PSC supplies the power supply voltage Vcc to the first source line SL1, and the ground supply circuit GSC supplies the ground voltage Vss to the first bit line BL1. Can be. Since the current flows from the first source line SL1 to the first bit line BL1 through the variable resistance element VR, the variable resistance element VR is written in a high resistance state.
As described with reference to the low resistance write operation, the first bit line BL1 is not limited to being selected. For example, when the second bit line BL2 is selected, the power supply circuit PSC supplies the power supply voltage Vcc to the first source line SL1 and the ground supply circuit GSC supplies the second bit line. The ground voltage Vss will be supplied to BL2. That is, current may flow from the first source line SL1 to the second bit line BL2 through the selected memory cell MC.
9 and 10 are circuit diagrams showing current paths of the
Table 3 shows the bias conditions of the control signals when the selected memory cell MC is read.
6, 9, 10, and 3, the operation of reading the selected memory cell MC will be described.
In the read operation, the upper transistors TT1 and TT2 connected to the reference bit lines RBL1 and RBL2 of the first
In a read operation, the read signal RD is controlled to be logic high.
In response to the bias conditions described in Table 3, the first read and write
The current path between the first
In response to the read signal RD, the sixth transistor T6 is turned on. That is, the first current source CS1 supplies the first current 2I to the first and second upper transistors TT1 and TT2. The first current 2I is supplied to the reference memory cell RMC having the variable resistance element RH in the high resistance state and the reference memory cell RMC having the variable resistance element RL in the low resistance state.
In response to the read signal RD, the third transistor T3 of the ground supply circuit GSC supplies the ground voltage Vss to the selected reference source line RSL1. That is, the first current 2I is supplied to the variable resistance elements RL and RH in the low and high resistance states connected in parallel to the ground node provided by the ground supply circuit GSC.
The current path between the
In response to the read signal RD, the seventh transistor T7 is turned on. That is, the second current source CS2 supplies the second current I to the first lower transistor TB1. The second current I is supplied to the variable resistance element VR of the selected memory cell MC.
In response to the read signal RD, the third transistor T3 of the ground supply circuit GSC supplies the ground voltage Vss to the selected source line SL1. That is, the variable resistance element VR of the selected memory cell MC is connected to the ground node provided by the ground supply circuit GSC.
The
The voltage of the reference node RN of the amplifier SA is derived as shown in Equation (1).
The voltage of the cell node CN of the amplifier SA is derived as in Equation 2.
The amplifier SA is configured to compare the voltage of the cell node CN with the voltage of the reference node RN. The comparison result is output as read data DOUT.
When the voltage of the reference node RN described in
The variable resistance element VR has a high resistance value RH or a low resistance value RL. When the variable resistance element VR has a high resistance value RH, Equation 3 is derived as in Equation 4.
Equation 4 has a positive value. That is, when the variable resistance element VR has a high resistance value RH, the voltage level of the cell node CN is higher than the voltage level of the reference node RN.
When the variable resistance element VR has a low resistance RL value, Equation 3 is derived as in Equation 5.
Equation 5 has a negative value. That is, when the variable resistance element VR has a low resistance RL value, the voltage level of the cell node CN is lower than the voltage level of the reference node RN.
Therefore, when the variable resistance element VR has a high resistance value RH, the amplifier SA outputs a logic high as read data. When the variable resistance element VR has a low resistance RL value, the amplifier SA outputs a logic low as read data.
FIG. 12 is a circuit diagram illustrating a current path of the first
Table 4 shows the bias conditions of the control signals when the selected reference memory cell RMC is written.
12 and 4, in the write operation, the first to fourth lower control signals WRB1 to WRB4 are controlled to be logic low. That is, the first to fourth lower transistors TB1 to TB4 are turned off.
The selected control signal of the first and second upper control signals WRT1 and WRT2 corresponding to the selected first reference source line SL1 is controlled to be logic high, and the unselected control signal is controlled to be logic low.
When the selected reference memory cell RMC is written to the low resistance state RL, the low resistance write signal WRL is logic high, the low resistance write inversion signal / WRL is logic low, and the high resistance write signal WRH will be controlled at logic low and the low resistance write inversion signal (/ WRH) will be controlled at logic high.
When the selected reference memory cell RMC is written to the high resistance state RH, the low resistance write signal WRL is logic low, the low resistance write inversion signal / WRL is logic high, and the high resistance write signal WRH will be controlled at logic high and the low resistance write inversion signal (/ WRH) will be controlled at logic low.
FIG. 13 is a flowchart illustrating a read method of a
In operation S120, the first current 2I is supplied to a path connected to the reference source line RSL through two reference bit lines RBL and two reference memory cells RMC. For example, the first current source CS1 will supply the first current 2I.
In operation S130, the second current I is supplied to a path connected to the source line SL through the bit line BL and the selected memory cell MC. For example, the second current source CS2 will supply the second current I.
In step S140, the first and second voltages induced by the first and second currents 2I and I, respectively, are compared. For example, the amplifier SA will compare the voltage of the reference node RN induced by the first current 2I with the voltage of the cell node CN induced by the second current I.
In step S150, the first voltage (eg, the voltage of the reference node RN) and the second voltage (eg, the voltage of the cell node CN) are compared. If the second voltage (for example, the voltage of the cell node CN) is greater than the first voltage (for example, the voltage of the reference node RN), the selected memory cell MC is in the high resistance state (S160). RH). For example, the amplifier SA will output a logic high as data read.
If the second voltage (eg, the voltage of the cell node CN) is smaller than the first voltage (eg, the voltage of the reference node RN), the selected memory cell is determined to be in the low resistance state in step S170. . For example, amplifier SA will output a logic low as read data.
As described above, in the
In the above-described embodiment, each access unit has been described as being connected to four bit lines BL and two source lines SL. However, the number of bit lines BL and source lines of each access unit is not limited. Similarly, the number of reference bit lines RBL and reference source lines RSL of each reference access unit is not limited.
In the above-described embodiment, an access unit and a reference access unit have been described based on rows and columns. However, rows and columns are terms according to the relative positions of the access unit and the reference access unit, and are not limited.
FIG. 14 is a block diagram illustrating a
The
In exemplary embodiments, the
In exemplary embodiments, the
The host interface includes a protocol for performing data exchange between the host and the
The
The
The
As another example, the
In exemplary embodiments, the
FIG. 15 is a block diagram illustrating an application example of the
FIG. 16 is a block diagram illustrating a
The
In FIG. 16, the
In FIG. 16, the
In exemplary embodiments, the
In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.
100; Nonvolatile memory device
MC; Memory cell
RMC; Reference memory cell
BL; Bit line
RBL; Reference bit line
SL; Source lines
RSL; Reference source line
WL; Word line
RWL; Reference word line
SA; amplifier
PSC; Power supply circuit
GSC; Ground supply circuit
CS1; First current source
CS2; Second current source
Claims (20)
A reference memory cell array including reference memory cells coupled between first and second reference bit lines and the one source line; And
And a read and write circuit connected to the first and second bit lines and the one source line.
The reference memory cell array
A first reference memory cell coupled between the first reference bit line and the one source line; And
And a second reference memory cell coupled between the second reference bit line and the one source line.
The first reference memory cell includes a first select transistor connected to the one source line,
The second reference memory cell comprises a second select transistor coupled to the one source line, and
And the first and second select transistors are controlled in response to a common reference word line.
The first reference memory cell further comprises a first resistor coupled to the first select transistor and the first bit line, and
The second reference memory cell further includes a second resistor connected to the second select transistor and the second bit line.
The nonvolatile memory device of claim 1, wherein the first resistor and the second resistor have different resistance values.
In a read operation, the read and write circuit is configured to provide a second current to a selected bit line of the first and second bit lines and to provide a first current to the first and second reference bit lines. Nonvolatile memory device.
And the amount of the first current is greater than the amount of the second current.
In a read operation, the read and write circuit is based on the first voltage induced by the first current and the second voltage induced by the second current, the resistance state of the selected memory cell connected to the selected bit line. The nonvolatile memory device is configured to determine.
In a read operation, the read and write circuit is configured to determine the selected memory cell as a high resistance state when the second voltage has a level higher than the first voltage.
In a read operation, the read and write circuit is configured to determine the selected memory cell to a low resistance state when the second voltage has a level lower than the first voltage.
And when the selected memory cell is written to a low resistance state, the read and write circuit is configured to provide a write current to the selected bit line of the first and second bit lines.
When the selected memory cell is written to a high resistance state, the read and write circuit is configured to provide a write current to the one source line,
And a non-selected bit line of the first and second bit lines is floated.
The read and write circuit
First and second upper transistors connected to the first and second reference bit lines; And
And a first and second lower transistors connected to the first and second bit lines.
The read and write circuit
A power supply circuit configured to supply a power voltage to the first and second lower transistors when the selected memory cell is written to a low resistance state; And
And a ground supply circuit configured to supply a ground voltage to the one source line when the selected memory cell is written to a low resistance state.
When the selected memory cell is written to a high resistance state, the power supply circuit is configured to supply a power supply voltage to the one source line, and
And when the selected memory cell is written to a high resistance state, the ground supply circuit is configured to supply ground voltages to the first and second lower transistors.
The read and write circuit
A first current source supplying a first current to the first and second upper transistors in a read operation;
A second current source configured to supply a second current to the first and second bottom transistors in a read operation; And
And an amplifier configured to sense a difference between a first voltage induced by the first current and a second voltage induced by the second current.
And the first and second upper transistors are turned on together in a read operation and turned off together in a memory cell write operation.
When the selected reference memory cell of the first and second reference memory cells is written, the selected upper transistor of the first and second upper transistors is turned on, and the other upper transistor is turned off. Memory device.
And the first and second reference memory cells and the first and second memory cells each include a spin torque transfer magneto-resistive element.
Supplying a first current to an electrical path connected to the one source line through two reference bit lines and two reference memory cells respectively corresponding to the two reference bit lines;
Supplying a second current to an electrical path connected to the one source line through a bit line and a selected memory cell; And
Determining a logic state of the selected memory cell based on voltages induced by the first and second currents, respectively.
Priority Applications (2)
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KR1020100057153A KR101109555B1 (en) | 2010-06-16 | 2010-06-16 | Nonvolatile memory device and reading method thereof |
PCT/KR2011/004298 WO2011159070A2 (en) | 2010-06-16 | 2011-06-13 | Nonvolatile memory device and method for reading same |
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KR1020100057153A KR101109555B1 (en) | 2010-06-16 | 2010-06-16 | Nonvolatile memory device and reading method thereof |
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KR101109555B1 true KR101109555B1 (en) | 2012-01-31 |
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CN106856101B (en) * | 2015-12-08 | 2019-03-19 | 华邦电子股份有限公司 | Resistive memory and its memory cell |
KR102519458B1 (en) * | 2016-11-01 | 2023-04-11 | 삼성전자주식회사 | Nonvolatile memory device and operating method thereof |
US10727275B2 (en) | 2018-05-18 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory layout for reduced line loading |
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US20080239795A1 (en) * | 2005-10-19 | 2008-10-02 | Renesas Technology Corp | Nonvolatile memory device with write error suppressed in reading data |
US20100067283A1 (en) * | 2006-05-30 | 2010-03-18 | Yoshihiro Ueda | Sense amplifier |
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DE19914489C1 (en) * | 1999-03-30 | 2000-06-08 | Siemens Ag | Memory cell condition evaluation device for magnetoresistive memory |
JP4771631B2 (en) * | 2001-09-21 | 2011-09-14 | ルネサスエレクトロニクス株式会社 | Thin film magnetic memory device |
JP4443886B2 (en) * | 2003-09-30 | 2010-03-31 | 株式会社東芝 | Semiconductor memory device |
US8004880B2 (en) * | 2007-03-06 | 2011-08-23 | Qualcomm Incorporated | Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory |
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US20080239795A1 (en) * | 2005-10-19 | 2008-10-02 | Renesas Technology Corp | Nonvolatile memory device with write error suppressed in reading data |
US20100067283A1 (en) * | 2006-05-30 | 2010-03-18 | Yoshihiro Ueda | Sense amplifier |
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WO2011159070A2 (en) | 2011-12-22 |
KR20110137113A (en) | 2011-12-22 |
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