KR101109009B1 - A method for parallelizing irregular reduction on explicitly managed memory hierarchy - Google Patents

Abstract

The present invention relates to a method for parallelizing non-normal reduction, comprising the steps of: (a) dividing data into blocks having a predetermined size in accordance with an on-chip memory size of an explicit management memory structure; (B) generating the repetition cycles of the iterations from each of the same data blocks approaching each other as unit operations of distributed execution; (C) allocating the generated unit tasks to the plurality of devices on an event basis; It includes.

According to the present invention as described above, by the parallel processing having an explicit relational memory structure, the same data block is selected and the unit operations of distributed execution are allocated to a plurality of devices, thereby minimizing the time required for calculating the irregular reduction. In addition, it has the effect of deriving fast computational results.

Irregular, reduction, parallelism, IRREGULAR, REDUCTION

Description

A METHOD FOR PARALLELIZING IRREGULAR REDUCTION ON EXPLICITLY MANAGED MEMORY HIERARCHY}

The present invention relates to a method for parallelizing non-regular reduction, and more particularly, to a technique of dividing a calculation task and allocating to each processing unit in order to distribute and execute non-normal reduction in a parallel processing unit having an explicit management memory structure. .

Recently, due to the performance speed difference between the processor and the main memory, a problem of performance degradation in reading and writing data has been introduced. Therefore, an explicit managed memory structure has been proposed instead of the existing cache structure. The purpose of explicit managed memory structures is to expose memory hierarchies to programmers so that programmers can improve the execution performance of their programs by writing code using data access methods tailored to the characteristics of each application. In the existing cache-based environment, most of the data access process was automatically handled by the processor, which limited the programmer's ability to optimize for the application's characteristics. Because the programmer manages the movement directly, it is easy to perform various optimizations, such as keeping frequently used data in on-chip memory or importing data for future use in on-chip memory.

를 계산하고 그 값을 교환 법칙이 성립하는 연산자인 리덕션 연산자 '

'를 이용하여 배열

의 원소들에 누적하는 것을 특징으로 한다. 이 때 배열

를 접근하는 인덱스

,

등은 정규화된 수식으로 나타나지 않는 임의의 함수로서, 다른 배열에 의해 간접지정(indirection)되는 형태일 수 있다.Non-normal reduction is often used to solve problems in various scientific fields, such as molecular dynamics and fluid dynamics, using a computer, and is generally expressed in the form of FIG. 1. The loop of FIG. 1 has a specific value according to the purpose of calculation at every iteration.

And the value of the reduction operator '

Array using '

It accumulates in the elements of. Then array

Index to access

,

And the like are arbitrary functions that do not appear as normalized expressions, and may be indirectly designated by other arrays.

In general, calculations performed through non-normal reduction take a lot of time. Therefore, a technique for reducing execution time by distributing non-normal reduction using a high performance parallel processing unit has been developed. For example, a method of performing each repetition period in parallel using a critical section, or a method of simultaneously calculating partial results for each processing device and then combining the partial results into a final result has been proposed.

However, the existing methods related to distributed execution of non-regular reduction do not support data movement between memory hierarchies that occur during reading and writing of data, so they cannot be used in parallel processing units with explicit managed memory structures. There are many high performance parallel processing units on the market that employ explicit managed memory structures. In order to effectively execute scientific computation programs including irregular reduction using these devices, a new distributed execution method that takes into account the characteristics of the memory structure is introduced. need.

An object of the present invention is to provide a method for partitioning a calculation in consideration of characteristics of an explicit managed memory structure, a method for allocating each partitioned calculation task to each processing device, which is not considered in existing technologies, And by providing a method for minimizing the cost of reading and writing data in the main memory for each computational task, the purpose is to enable distributed execution of denormalization in a parallel processing unit having an explicit managed memory structure.

In accordance with an aspect of the present invention, there is provided a method of parallelizing non-normal reduction, comprising: dividing data into blocks having a predetermined size in accordance with an on-chip memory size of an explicit management memory structure; (B) generating the repetition cycles of the iterations from each of the same data blocks approaching each other as unit operations of distributed execution; (C) allocating the generated unit tasks to the plurality of devices on an event basis; It includes.

와, 반복주기공간의 차원 수

, 및 계산에 사용되는 배열

의 원소의 크기인

를 조합하는 하기의 [수학식 1]을 통해 상기 데이터 블록의 크기

를 연산하는 (a-1) 단계; 를 포함한다.In addition, in step (a), the size of the area available for data allocation in the on-chip memory

And the number of dimensions of the repeating cycle space.

, And arrays used for calculation

Is the size of the element of

The size of the data block through the following [Equation 1] to combine

Calculating (a-1); It includes.

[Equation 1]

In addition, step (b) comprises the steps of: (b-1) generating a unit operation of distributed execution by performing bucket sorting with the size of the block as the size of the bucket; It includes.

In addition, step (c) includes: (c-1) the scheduler thread passing a live-in parameter to the work thread informing the work thread of the start of the work; (C-2) the task thread requesting the scheduler thread to allocate a task; (C-3) determining whether a scheduler thread has a data independent task among tasks to be assigned to the task thread; (c-4) the scheduler thread allocates the data independent task to the task currently being processed as the task thread when there is a data independent task among the tasks to be assigned to the task thread as a result of the step (c-3). step; (C-5) performing a task assigned to a work thread and transferring a result variable (live-out) to the scheduler thread upon completion of the assigned task; It includes.

(C-6) If there is no data independent task among the tasks to be allocated to the work thread as a result of the determination of step (c-3), after waiting for a predetermined time until the currently processed task is completed, implementing the procedure to step (c-3); It includes.

According to the present invention as described above, by minimizing the same block of data by assigning the unit operations of distributed execution to a plurality of devices by the parallel processing having an explicit relation memory structure, the time required to calculate the non-rectification reduction is minimized In addition, it has the effect of deriving fast computational results.

Specific features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings. Prior to this, terms and words used in the present specification and claims are to be interpreted in accordance with the technical idea of the present invention based on the principle that the inventor can properly define the concept of the term in order to explain his invention in the best way. It should be interpreted in terms of meaning and concept. It is to be noted that the detailed description of known functions and constructions related to the present invention is omitted when it is determined that the gist of the present invention may be unnecessarily blurred.

2 is an exemplary diagram of non-normal reduction according to a molecular dynamics calculation algorithm of the method of parallelizing non-normal reduction according to the present invention.

The loop ('for') illustrated in FIG. 2 calculates an interaction force with respect to one molecular pair at each repetition period.

First, we obtain the indices p1 and p2 of each molecule from array interactions, which are lists of interacting molecular pairs.

Then, the position information of each molecule is extracted through the array positions.

The interaction force d_force is calculated and its value is accumulated in force, an array representing the force each molecule receives.

In the example of FIG. 2, the non-normal reduction is made of an array force. Hereinafter, the positions that are accessed by the indexes such as the 'reduction array', 'reduction array' and the 'secondary array' and 'reduction array' The interactions that determine the index are described as 'index arrays'.

In the loop of FIG. 2, since the addresses of the reduction array and the secondary array accessed in each iteration period are determined indirectly by the index array, the value cannot be predicted at the time of writing the code. Therefore, when writing code for an explicit managed memory structure, there is an inefficiency in generating code for data movement every repetition cycle.

On the other hand, FIG. 3 is an exemplary diagram showing which region each repetition period belongs to according to p1 and p2 values when 'reduction arrangement' and 'secondary arrangement' of FIG. 2 are divided into blocksize.

는 R(1, 2)에 속하며, 리덕션 배열과 보조 배열의 두 번째와 세 번째 블록을 접근한다. 이와 유사하게 p1의 값이 '150', p2의 값이 '220'인 반복주기

가 있다고 가정하면, 이 역시 R(1, 2)에 속하는 것을 알 수 있는데, 이 때

와

는 같은 데이터 블록을 접근하므로 한 번에 처리하면 추가적인 데이터 이동 코드를 실행할 필요가 없다.For example, if blocksize is '100', some iteration period

Belongs to R (1, 2) and accesses the second and third blocks of the reduction and auxiliary arrays. Similarly, the repetition period with p1 value '150' and p2 value '220'

If we assume that we also belong to R (1, 2),

Wow

Accesses the same block of data, so if you process it all at once, you don't need to run any additional data movement code.

As described above, when a plurality of repetition cycles using the same data block set are to be processed at once, all the data block sets required for the calculation must reside in the on-chip memory.

In the example of FIG. 3, the maximum number of data blocks needed to calculate R (a, b) is the number of dimensions of the repeating periodic space for each block of 'force' and 'positions'. It can be seen that each of the two.

As shown in FIG. 4, in the method of parallelizing non-normal reduction according to the present invention, first, data is divided into blocks having a predetermined size in accordance with the size of an on-chip memory (S10).

Subsequently, the data blocks that access the repetition cycles of the repetition statements are classified into the same ones to generate unit operations of distributed execution (S20).

In operation S30, the generated unit tasks are allocated to a processing device corresponding to each event.

Here, when dividing the data into blocks having a predetermined size in step (a), the block size is determined by Equation 1.

[Equation 1]

는 블록의 크기,

는 온 칩 메모리 중 데이터 할당에 사용할 수 있는 영역의 크기,

은 도 3과 같이 나타나는 반복주기공간(iteration space)의 차원 수,

는 배열

의 원소의 크기이다.At this time,

Is the size of the block,

Is the size of the on-chip memory available for data allocation,

Is the number of dimensions of the iteration space shown in Figure 3,

Is an array

Is the size of the element.

In addition, in the step (b), as shown in FIG. 5, each approaching data block collects the same repetition periods and generates them as unit operations of distributed execution.

에서 접근하는 배열의 인덱스인 (p1, p2)를 나타내는데, 도 5 의 상단과 같은 순서로 배치되어 있던 반복주기들을 각기 접근하는 블록에 따라 재배치하면, 도 5 의 하단과 같은 결과를 얻는다.Each rectangle in Fig. 5 is a repetition period

(P1, p2), which are the indexes of the arrays accessed in, are rearranged in the same order as in the upper part of FIG.

That is, step (b) of rearranging each repetition period may be performed through bucket sorting in which the size of the block determined in step (a) is the size of the bucket (S21).

In the step (c), the unit tasks determined in the step (b) are allocated to a plurality of devices in parallel according to the event delivery method shown in FIGS. 6 and 7.

When a unit task is newly allocated to a processing unit, only data-independent tasks should be allocated to tasks that are currently being processed in order to prevent a race condition from occurring in parallel execution.

Herein, a task is data independent when each task does not use the same data block. For example, in FIG. 3, R (0, 1) and R (2,3) use only different blocks. It is data independent, and R (1, 2) and R (1, 3) are data dependent because they use the same block.

6 and 7, the step (c) is specifically examined, and the scheduler thread delivers a live-in parameter for notifying the start of the work to the work thread (S31).

Subsequently, the work thread requests the scheduler thread to allocate the work (S32).

Subsequently, it is determined whether a scheduler thread has a data independent task among tasks to be allocated to the task thread (S33).

As a result of the determination in step S33, when there is a data independent task among the tasks to be allocated to the work thread, the scheduler thread allocates the data independent task to the task currently being processed as the work thread (S34).

Subsequently, the task thread performs the assigned task and delivers a result (live-out) variable upon completion of the assigned task (S35).

On the other hand, if there is no data independent task among the tasks to be allocated to the work thread as a result of the determination in step S33, after a predetermined time waits until the current processing task is completed, the procedure is performed in step S33. (S36).

As described above and described with reference to a preferred embodiment for illustrating the technical idea of the present invention, the present invention is not limited to the configuration and operation as shown and described as described above, it is a deviation from the scope of the technical idea It will be understood by those skilled in the art that many modifications and variations can be made to the invention without departing from the scope of the invention. And all such modifications and changes as fall within the scope of the present invention are therefore to be regarded as being within the scope of the present invention.

1 is an illustrative diagram generally illustrating code for implementing a non-normal reduction.

Figure 2 is an illustration of nonnormal reduction according to the molecular dynamics calculation algorithm of the method of parallelization of nonnormal normalization according to the present invention.

3 is a diagram illustrating which region each repetition period belongs to according to p1 and p2 values when the reduction array and the auxiliary array of FIG. 2 are divided into blocksize.

4 is a flow chart illustrating a parallelization method of non-normal reduction according to the present invention.

FIG. 5 is an exemplary view detailing step (b) of the method for parallelizing non-normal reduction according to the present invention. FIG.

Figure 6 is a flow chart showing step (c) of the method of parallelization of irregular reduction in accordance with the present invention.

FIG. 7 is an exemplary view illustrating a description of step (c) of the method for parallelizing non-normal reduction according to the present invention. FIG.

Claims (5)

In the parallelization method of irregular reduction, (a) dividing the data into blocks having a predetermined size in accordance with the on-chip memory size of the explicit management memory structure; (b) generating the repetition cycles of the iterations from each of the same data blocks approaching each other as unit operations of distributed execution; And (c) allocating the generated unit tasks to a plurality of devices on an event basis; , ≪ / RTI & Step (b) includes: generating a unit job of distributed execution by performing bucket sorting, wherein the size of the block is the size of a bucket; Parallelization method of irregular reduction comprising a. The method of claim 1, In step (a), (a-1) Size of the area available for data allocation in the on-chip memory

And the number of dimensions of the repeating cycle space.

, And arrays used for calculation

Is the size of the element of

The size of the data block through the following [Equation 1] to combine

Calculating a; Parallelization method of irregular reduction comprising a. [Equation 1]

delete The method of claim 1, In step (c), (c-1) the scheduler thread passing a live-in parameter to the work thread that informs the work thread of the start of the work; (c-2) the task thread requesting the scheduler thread to allocate a task; (c-3) determining whether the scheduler thread has a data independent task among tasks to be allocated to the task thread; (c-4) As a result of the determination in the step (c-3), if there is a data independent task among the tasks to be allocated to the task thread, the scheduler thread is data independent of the task currently being processed by the task thread. Assigning a task; And (c-5) performing a task assigned by the work thread and transferring a result variable (live-out) to the scheduler thread upon completion of the assigned task; Parallelization method of irregular reduction comprising a. The method of claim 4, wherein (c-6) As a result of the determination in the step (c-3), if there is no data independent task among the tasks to be allocated to the task thread, the processor waits for a predetermined time until the task currently being processed is completed. implementing the procedure to step (c-3); Parallelization method of irregular reduction comprising a.

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